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<div class="title">D:/123/stm32f4_blink_led-1.2.2-120323/inc/stm32f4xx.h</div>  </div>
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<a href="stm32f4xx_8h.html">Go to the documentation of this file.</a><div class="fragment"><pre class="fragment"><a name="l00001"></a>00001 
<a name="l00047"></a>00047 <span class="preprocessor">#ifndef __STM32F4xx_H</span>
<a name="l00048"></a>00048 <span class="preprocessor"></span><span class="preprocessor">#define __STM32F4xx_H</span>
<a name="l00049"></a>00049 <span class="preprocessor"></span>
<a name="l00050"></a>00050 <span class="preprocessor">#ifdef __cplusplus</span>
<a name="l00051"></a>00051 <span class="preprocessor"></span> <span class="keyword">extern</span> <span class="stringliteral">&quot;C&quot;</span> {
<a name="l00052"></a>00052 <span class="preprocessor">#endif </span><span class="comment">/* __cplusplus */</span>
<a name="l00053"></a>00053   
<a name="l00058"></a>00058 <span class="comment">/* Uncomment the line below according to the target STM32 device used in your</span>
<a name="l00059"></a>00059 <span class="comment">   application </span>
<a name="l00060"></a>00060 <span class="comment">  */</span>
<a name="l00061"></a>00061 
<a name="l00062"></a>00062 <span class="preprocessor">#if !defined (STM32F4XX) </span>
<a name="l00063"></a>00063 <span class="preprocessor"></span><span class="preprocessor">  #define STM32F4XX</span>
<a name="l00064"></a>00064 <span class="preprocessor"></span><span class="preprocessor">#endif</span>
<a name="l00065"></a>00065 <span class="preprocessor"></span>
<a name="l00066"></a>00066 <span class="comment">/*  Tip: To avoid modifying this file each time you need to switch between these</span>
<a name="l00067"></a>00067 <span class="comment">        devices, you can define the device in your toolchain compiler preprocessor.</span>
<a name="l00068"></a>00068 <span class="comment">  */</span>
<a name="l00069"></a>00069 
<a name="l00070"></a>00070 <span class="preprocessor">#if !defined (STM32F4XX)</span>
<a name="l00071"></a>00071 <span class="preprocessor"></span><span class="preprocessor"> #error &quot;Please select first the target STM32F4XX device used in your application (in stm32f4xx.h file)&quot;</span>
<a name="l00072"></a>00072 <span class="preprocessor"></span><span class="preprocessor">#endif</span>
<a name="l00073"></a>00073 <span class="preprocessor"></span>
<a name="l00074"></a>00074 <span class="preprocessor">#if !defined  (USE_STDPERIPH_DRIVER)</span>
<a name="l00075"></a>00075 <span class="preprocessor"></span>
<a name="l00080"></a>00080   <span class="comment">/*#define USE_STDPERIPH_DRIVER*/</span>
<a name="l00081"></a>00081 <span class="preprocessor">#endif </span><span class="comment">/* USE_STDPERIPH_DRIVER */</span>
<a name="l00082"></a>00082 
<a name="l00091"></a>00091 <span class="preprocessor">#if !defined  (HSE_VALUE) </span>
<a name="l00092"></a>00092 <span class="preprocessor"></span><span class="preprocessor">  #define HSE_VALUE    ((uint32_t)25000000) </span>
<a name="l00093"></a>00093 <span class="preprocessor">#endif </span><span class="comment">/* HSE_VALUE */</span>
<a name="l00094"></a>00094 
<a name="l00099"></a>00099 <span class="preprocessor">#if !defined  (HSE_STARTUP_TIMEOUT) </span>
<a name="l00100"></a>00100 <span class="preprocessor"></span><span class="preprocessor">  #define HSE_STARTUP_TIMEOUT    ((uint16_t)0x0500)   </span>
<a name="l00101"></a>00101 <span class="preprocessor">#endif </span><span class="comment">/* HSE_STARTUP_TIMEOUT */</span>   
<a name="l00102"></a>00102 
<a name="l00103"></a>00103 <span class="preprocessor">#if !defined  (HSI_VALUE)   </span>
<a name="l00104"></a>00104 <span class="preprocessor"></span><span class="preprocessor">  #define HSI_VALUE    ((uint32_t)16000000) </span>
<a name="l00105"></a>00105 <span class="preprocessor">#endif </span><span class="comment">/* HSI_VALUE */</span>   
<a name="l00106"></a>00106 
<a name="l00110"></a><a class="code" href="group___library__configuration__section.html#gab16ffe03509714c63d5e530131c494f4">00110</a> <span class="preprocessor">#define __STM32F4XX_STDPERIPH_VERSION_MAIN   (0x01) </span>
<a name="l00111"></a><a class="code" href="group___library__configuration__section.html#gadce716e810a51b042298fb21b63e5366">00111</a> <span class="preprocessor">#define __STM32F4XX_STDPERIPH_VERSION_SUB1   (0x00) </span>
<a name="l00112"></a><a class="code" href="group___library__configuration__section.html#ga4b16607e43a35289dc5ebb608b1261d4">00112</a> <span class="preprocessor">#define __STM32F4XX_STDPERIPH_VERSION_SUB2   (0x00) </span>
<a name="l00113"></a><a class="code" href="group___library__configuration__section.html#gad5bec5e54ac96b9238a6363f2088f85c">00113</a> <span class="preprocessor">#define __STM32F4XX_STDPERIPH_VERSION_RC     (0x00) </span>
<a name="l00114"></a>00114 <span class="preprocessor">#define __STM32F4XX_STDPERIPH_VERSION        ((__STM32F4XX_STDPERIPH_VERSION_MAIN &lt;&lt; 24)\</span>
<a name="l00115"></a>00115 <span class="preprocessor">                                             |(__STM32F4XX_STDPERIPH_VERSION_SUB1 &lt;&lt; 16)\</span>
<a name="l00116"></a>00116 <span class="preprocessor">                                             |(__STM32F4XX_STDPERIPH_VERSION_SUB2 &lt;&lt; 8)\</span>
<a name="l00117"></a>00117 <span class="preprocessor">                                             |(__STM32F4XX_STDPERIPH_VERSION_RC))</span>
<a name="l00118"></a>00118 <span class="preprocessor"></span>                                             
<a name="l00130"></a><a class="code" href="group___configuration__section__for___c_m_s_i_s.html#ga45a97e4bb8b6ce7c334acc5f45ace3ba">00130</a> <span class="preprocessor">#define __CM4_REV                 0x0001  </span>
<a name="l00131"></a><a class="code" href="group___configuration__section__for___c_m_s_i_s.html#ga4127d1b31aaf336fab3d7329d117f448">00131</a> <span class="preprocessor">#define __MPU_PRESENT             1       </span>
<a name="l00132"></a><a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gae3fe3587d5100c787e02102ce3944460">00132</a> <span class="preprocessor">#define __NVIC_PRIO_BITS          4       </span>
<a name="l00133"></a><a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gab58771b4ec03f9bdddc84770f7c95c68">00133</a> <span class="preprocessor">#define __Vendor_SysTickConfig    0       </span>
<a name="l00134"></a><a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gac1ba8a48ca926bddc88be9bfd7d42641">00134</a> <span class="preprocessor">#define __FPU_PRESENT             1       </span>
<a name="l00140"></a><a class="code" href="group___configuration__section__for___c_m_s_i_s.html#ga666eb0caeb12ec0e281415592ae89083">00140</a> <span class="preprocessor">typedef enum IRQn</span>
<a name="l00141"></a>00141 <span class="preprocessor"></span>{
<a name="l00142"></a>00142 <span class="comment">/******  Cortex-M4 Processor Exceptions Numbers ****************************************************************/</span>
<a name="l00143"></a><a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083ade177d9c70c89e084093024b932a4e30">00143</a>   <a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083ade177d9c70c89e084093024b932a4e30">NonMaskableInt_IRQn</a>         = -14,    
<a name="l00144"></a><a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083a33ff1cf7098de65d61b6354fee6cd5aa">00144</a>   <a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083a33ff1cf7098de65d61b6354fee6cd5aa">MemoryManagement_IRQn</a>       = -12,    
<a name="l00145"></a><a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083a8693500eff174f16119e96234fee73af">00145</a>   <a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083a8693500eff174f16119e96234fee73af">BusFault_IRQn</a>               = -11,    
<a name="l00146"></a><a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083a6895237c9443601ac832efa635dd8bbf">00146</a>   <a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083a6895237c9443601ac832efa635dd8bbf">UsageFault_IRQn</a>             = -10,    
<a name="l00147"></a><a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083a4ce820b3cc6cf3a796b41aadc0cf1237">00147</a>   <a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083a4ce820b3cc6cf3a796b41aadc0cf1237">SVCall_IRQn</a>                 = -5,     
<a name="l00148"></a><a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083a8e033fcef7aed98a31c60a7de206722c">00148</a>   <a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083a8e033fcef7aed98a31c60a7de206722c">DebugMonitor_IRQn</a>           = -4,     
<a name="l00149"></a><a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083a03c3cc89984928816d81793fc7bce4a2">00149</a>   <a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083a03c3cc89984928816d81793fc7bce4a2">PendSV_IRQn</a>                 = -2,     
<a name="l00150"></a><a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083a6dbff8f8543325f3474cbae2446776e7">00150</a>   <a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083a6dbff8f8543325f3474cbae2446776e7">SysTick_IRQn</a>                = -1,     
<a name="l00151"></a>00151 <span class="comment">/******  STM32 specific Interrupt Numbers **********************************************************************/</span>
<a name="l00152"></a><a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083a971089d7566ef902dfa0c80ac3a8fd52">00152</a>   <a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083a971089d7566ef902dfa0c80ac3a8fd52">WWDG_IRQn</a>                   = 0,      
<a name="l00153"></a><a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083ab0b51ffcc4dcf5661141b79c8e5bd924">00153</a>   <a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083ab0b51ffcc4dcf5661141b79c8e5bd924">PVD_IRQn</a>                    = 1,      
<a name="l00154"></a><a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083ac127cca7ae48bcf93924209f04e5e5a1">00154</a>   <a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083ac127cca7ae48bcf93924209f04e5e5a1">TAMP_STAMP_IRQn</a>             = 2,      
<a name="l00155"></a><a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083a173ccc3f31df1f7e43de2ddeab3d1777">00155</a>   <a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083a173ccc3f31df1f7e43de2ddeab3d1777">RTC_WKUP_IRQn</a>               = 3,      
<a name="l00156"></a><a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083a91b73963ce243a1d031576d49e137fab">00156</a>   <a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083a91b73963ce243a1d031576d49e137fab">FLASH_IRQn</a>                  = 4,      
<a name="l00157"></a><a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083a5710b22392997bac63daa5c999730f77">00157</a>   <a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083a5710b22392997bac63daa5c999730f77">RCC_IRQn</a>                    = 5,      
<a name="l00158"></a><a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083ab6aa6f87d26bbc6cf99b067b8d75c2f7">00158</a>   <a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083ab6aa6f87d26bbc6cf99b067b8d75c2f7">EXTI0_IRQn</a>                  = 6,      
<a name="l00159"></a><a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083ae4badcdecdb94eb10129c4c0577c5e19">00159</a>   <a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083ae4badcdecdb94eb10129c4c0577c5e19">EXTI1_IRQn</a>                  = 7,      
<a name="l00160"></a><a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083a082cb3f7839069a0715fd76c7eacbbc9">00160</a>   <a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083a082cb3f7839069a0715fd76c7eacbbc9">EXTI2_IRQn</a>                  = 8,      
<a name="l00161"></a><a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083add889c84ba5de466ced209069e05d602">00161</a>   <a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083add889c84ba5de466ced209069e05d602">EXTI3_IRQn</a>                  = 9,      
<a name="l00162"></a><a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083ab70a40106ca4486770df5d2072d9ac0e">00162</a>   <a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083ab70a40106ca4486770df5d2072d9ac0e">EXTI4_IRQn</a>                  = 10,     
<a name="l00163"></a><a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083a9ee33e72512c4cfb301b216f4fb9d68c">00163</a>   <a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083a9ee33e72512c4cfb301b216f4fb9d68c">DMA1_Stream0_IRQn</a>           = 11,     
<a name="l00164"></a><a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083aa45ca2c955060e2c2a7cbbe1d6753285">00164</a>   <a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083aa45ca2c955060e2c2a7cbbe1d6753285">DMA1_Stream1_IRQn</a>           = 12,     
<a name="l00165"></a><a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083a0d9ec75e4478e70235b705d5a6b3efd8">00165</a>   <a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083a0d9ec75e4478e70235b705d5a6b3efd8">DMA1_Stream2_IRQn</a>           = 13,     
<a name="l00166"></a><a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083af77770e080206a7558decf09344fb2e2">00166</a>   <a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083af77770e080206a7558decf09344fb2e2">DMA1_Stream3_IRQn</a>           = 14,     
<a name="l00167"></a><a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083aee2aaf365c6c297a63cee41ecae2301a">00167</a>   <a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083aee2aaf365c6c297a63cee41ecae2301a">DMA1_Stream4_IRQn</a>           = 15,     
<a name="l00168"></a><a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083ac92efa72399fe58fa615d8bf8fd64a4e">00168</a>   <a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083ac92efa72399fe58fa615d8bf8fd64a4e">DMA1_Stream5_IRQn</a>           = 16,     
<a name="l00169"></a><a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083aef5e2b68f62f6f1781fab894f0b8f486">00169</a>   <a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083aef5e2b68f62f6f1781fab894f0b8f486">DMA1_Stream6_IRQn</a>           = 17,     
<a name="l00170"></a><a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083a4d69175258ae261dd545001e810421b3">00170</a>   <a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083a4d69175258ae261dd545001e810421b3">ADC_IRQn</a>                    = 18,     
<a name="l00171"></a><a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083a9ceb5175f7c10cf436955173c2246877">00171</a>   <a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083a9ceb5175f7c10cf436955173c2246877">CAN1_TX_IRQn</a>                = 19,     
<a name="l00172"></a><a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083ab6bf73ac43a9856b3f2759a59f3d25b5">00172</a>   <a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083ab6bf73ac43a9856b3f2759a59f3d25b5">CAN1_RX0_IRQn</a>               = 20,     
<a name="l00173"></a><a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083af71ef06c4f9ff0e1691c21ff3670acd4">00173</a>   <a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083af71ef06c4f9ff0e1691c21ff3670acd4">CAN1_RX1_IRQn</a>               = 21,     
<a name="l00174"></a><a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083a0f5f129d88a5606a378811e43039e274">00174</a>   <a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083a0f5f129d88a5606a378811e43039e274">CAN1_SCE_IRQn</a>               = 22,     
<a name="l00175"></a><a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083aa3aa50e0353871985facf62d055faa52">00175</a>   <a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083aa3aa50e0353871985facf62d055faa52">EXTI9_5_IRQn</a>                = 23,     
<a name="l00176"></a><a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083ab35b4ce63cfb11453f84a3695c6df368">00176</a>   <a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083ab35b4ce63cfb11453f84a3695c6df368">TIM1_BRK_TIM9_IRQn</a>          = 24,     
<a name="l00177"></a><a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083aa3879e49013035601e17f83a51e0829f">00177</a>   <a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083aa3879e49013035601e17f83a51e0829f">TIM1_UP_TIM10_IRQn</a>          = 25,     
<a name="l00178"></a><a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083ab1a744bdceb8eface6ff57dd036e608e">00178</a>   <a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083ab1a744bdceb8eface6ff57dd036e608e">TIM1_TRG_COM_TIM11_IRQn</a>     = 26,     
<a name="l00179"></a><a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083af312f0a21f600f9b286427e50c549ca9">00179</a>   <a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083af312f0a21f600f9b286427e50c549ca9">TIM1_CC_IRQn</a>                = 27,     
<a name="l00180"></a><a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083a3a4e2095a926e4095d3c846eb1c98afa">00180</a>   <a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083a3a4e2095a926e4095d3c846eb1c98afa">TIM2_IRQn</a>                   = 28,     
<a name="l00181"></a><a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083a985574288f66e2a00e97387424a9a2d8">00181</a>   <a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083a985574288f66e2a00e97387424a9a2d8">TIM3_IRQn</a>                   = 29,     
<a name="l00182"></a><a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083a368b899ca740b9ae0d75841f3abf68c4">00182</a>   <a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083a368b899ca740b9ae0d75841f3abf68c4">TIM4_IRQn</a>                   = 30,     
<a name="l00183"></a><a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083a9852dbbe8c014e716ce7e03a7b809751">00183</a>   <a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083a9852dbbe8c014e716ce7e03a7b809751">I2C1_EV_IRQn</a>                = 31,     
<a name="l00184"></a><a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083a2ec363869f4488782dc10a60abce3b34">00184</a>   <a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083a2ec363869f4488782dc10a60abce3b34">I2C1_ER_IRQn</a>                = 32,     
<a name="l00185"></a><a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083a3020193786527c47d2e4d8c92ceee804">00185</a>   <a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083a3020193786527c47d2e4d8c92ceee804">I2C2_EV_IRQn</a>                = 33,     
<a name="l00186"></a><a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083a60c35f2d48d512bd6818bc9fef7053d7">00186</a>   <a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083a60c35f2d48d512bd6818bc9fef7053d7">I2C2_ER_IRQn</a>                = 34,     
<a name="l00187"></a><a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083aacdff1a9c42582ed663214cbe62c1174">00187</a>   <a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083aacdff1a9c42582ed663214cbe62c1174">SPI1_IRQn</a>                   = 35,     
<a name="l00188"></a><a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083a505fbd4ccf7c2a14c8b76dc9e58f7ede">00188</a>   <a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083a505fbd4ccf7c2a14c8b76dc9e58f7ede">SPI2_IRQn</a>                   = 36,     
<a name="l00189"></a><a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083ad97cb163e1f678367e37c50d54d161ab">00189</a>   <a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083ad97cb163e1f678367e37c50d54d161ab">USART1_IRQn</a>                 = 37,     
<a name="l00190"></a><a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083a3f9c48714d0e5baaba6613343f0da68e">00190</a>   <a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083a3f9c48714d0e5baaba6613343f0da68e">USART2_IRQn</a>                 = 38,     
<a name="l00191"></a><a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083afb13802afc1f5fdf5c90e73ee99e5ff3">00191</a>   <a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083afb13802afc1f5fdf5c90e73ee99e5ff3">USART3_IRQn</a>                 = 39,     
<a name="l00192"></a><a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083a9fb0ad0c850234d1983fafdb17378e2f">00192</a>   <a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083a9fb0ad0c850234d1983fafdb17378e2f">EXTI15_10_IRQn</a>              = 40,     
<a name="l00193"></a><a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083afe09d6563a21a1540f658163a76a3b37">00193</a>   <a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083afe09d6563a21a1540f658163a76a3b37">RTC_Alarm_IRQn</a>              = 41,     
<a name="l00194"></a><a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083aa612f35c4440359c35acbaa3c1458c5f">00194</a>   <a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083aa612f35c4440359c35acbaa3c1458c5f">OTG_FS_WKUP_IRQn</a>            = 42,     
<a name="l00195"></a><a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083a3e01328006d19f7d32354271b9f61dce">00195</a>   <a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083a3e01328006d19f7d32354271b9f61dce">TIM8_BRK_TIM12_IRQn</a>         = 43,     
<a name="l00196"></a><a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083aa8d8f67a98f24de6f0b36ad6b1f29a7d">00196</a>   <a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083aa8d8f67a98f24de6f0b36ad6b1f29a7d">TIM8_UP_TIM13_IRQn</a>          = 44,     
<a name="l00197"></a><a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083ae252b31c3a341acbe9a467e243137307">00197</a>   <a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083ae252b31c3a341acbe9a467e243137307">TIM8_TRG_COM_TIM14_IRQn</a>     = 45,     
<a name="l00198"></a><a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083a637750639eff4e2b4aae80ed6f3cf67f">00198</a>   <a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083a637750639eff4e2b4aae80ed6f3cf67f">TIM8_CC_IRQn</a>                = 46,     
<a name="l00199"></a><a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083aedaa9c14e7e5fa9c0dcbb0c2455546e8">00199</a>   <a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083aedaa9c14e7e5fa9c0dcbb0c2455546e8">DMA1_Stream7_IRQn</a>           = 47,     
<a name="l00200"></a><a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083a70450df88125476d5771f2ff3f562536">00200</a>   <a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083a70450df88125476d5771f2ff3f562536">FSMC_IRQn</a>                   = 48,     
<a name="l00201"></a><a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083a16fe70a39348f3f27906dc268b5654e3">00201</a>   <a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083a16fe70a39348f3f27906dc268b5654e3">SDIO_IRQn</a>                   = 49,     
<a name="l00202"></a><a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083aed2eb3f4bb721d55fcc1003125956645">00202</a>   <a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083aed2eb3f4bb721d55fcc1003125956645">TIM5_IRQn</a>                   = 50,     
<a name="l00203"></a><a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083a4e9331739fb76a2ca7781fede070ae44">00203</a>   <a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083a4e9331739fb76a2ca7781fede070ae44">SPI3_IRQn</a>                   = 51,     
<a name="l00204"></a><a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083aded5314b20c6e4e80cb6ab0668ffb8d5">00204</a>   <a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083aded5314b20c6e4e80cb6ab0668ffb8d5">UART4_IRQn</a>                  = 52,     
<a name="l00205"></a><a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083ac55a11a64aae7432544d0ab0d4f7de09">00205</a>   <a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083ac55a11a64aae7432544d0ab0d4f7de09">UART5_IRQn</a>                  = 53,     
<a name="l00206"></a><a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083a5f581e9aedfaccd9b1db9ec793804b45">00206</a>   <a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083a5f581e9aedfaccd9b1db9ec793804b45">TIM6_DAC_IRQn</a>               = 54,     
<a name="l00207"></a><a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083a53cadc1e164ec85d0ea4cd143608e8e1">00207</a>   <a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083a53cadc1e164ec85d0ea4cd143608e8e1">TIM7_IRQn</a>                   = 55,     
<a name="l00208"></a><a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083a1e5055722630fd4b12aff421964c2ebb">00208</a>   <a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083a1e5055722630fd4b12aff421964c2ebb">DMA2_Stream0_IRQn</a>           = 56,     
<a name="l00209"></a><a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083a98abb3f02c1feb3831706bc1b82307cb">00209</a>   <a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083a98abb3f02c1feb3831706bc1b82307cb">DMA2_Stream1_IRQn</a>           = 57,     
<a name="l00210"></a><a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083abf5e189f3ac7aad9f65e65ea5a0f3b36">00210</a>   <a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083abf5e189f3ac7aad9f65e65ea5a0f3b36">DMA2_Stream2_IRQn</a>           = 58,     
<a name="l00211"></a><a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083a3ff8f3439f509e6e985eb960e63e1be4">00211</a>   <a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083a3ff8f3439f509e6e985eb960e63e1be4">DMA2_Stream3_IRQn</a>           = 59,     
<a name="l00212"></a><a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083ae54eb8b30273b38a0576f75aba24eec0">00212</a>   <a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083ae54eb8b30273b38a0576f75aba24eec0">DMA2_Stream4_IRQn</a>           = 60,     
<a name="l00213"></a><a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083ad71328dd95461b7c55b568cf25966f6a">00213</a>   <a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083ad71328dd95461b7c55b568cf25966f6a">ETH_IRQn</a>                    = 61,     
<a name="l00214"></a><a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083a0485578005e12c2e2c0fb253a844ec6f">00214</a>   <a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083a0485578005e12c2e2c0fb253a844ec6f">ETH_WKUP_IRQn</a>               = 62,     
<a name="l00215"></a><a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083af6b8fbc990ac71c8425647bb684788a4">00215</a>   <a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083af6b8fbc990ac71c8425647bb684788a4">CAN2_TX_IRQn</a>                = 63,     
<a name="l00216"></a><a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083a851fd2f2ab1418710e7da80e1bdf348a">00216</a>   <a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083a851fd2f2ab1418710e7da80e1bdf348a">CAN2_RX0_IRQn</a>               = 64,     
<a name="l00217"></a><a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083ab5023ff845be31a488ab63a0b8cf2b7a">00217</a>   <a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083ab5023ff845be31a488ab63a0b8cf2b7a">CAN2_RX1_IRQn</a>               = 65,     
<a name="l00218"></a><a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083a56c0b5758f26f31494e74aab9273f9fd">00218</a>   <a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083a56c0b5758f26f31494e74aab9273f9fd">CAN2_SCE_IRQn</a>               = 66,     
<a name="l00219"></a><a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083aa60a30b7ef03446a46fd72e084911f7e">00219</a>   <a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083aa60a30b7ef03446a46fd72e084911f7e">OTG_FS_IRQn</a>                 = 67,     
<a name="l00220"></a><a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083a933d4686213973abc01845a3da1c8a03">00220</a>   <a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083a933d4686213973abc01845a3da1c8a03">DMA2_Stream5_IRQn</a>           = 68,     
<a name="l00221"></a><a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083a21570761ad0b5ed751adc831691b7800">00221</a>   <a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083a21570761ad0b5ed751adc831691b7800">DMA2_Stream6_IRQn</a>           = 69,     
<a name="l00222"></a><a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083a3d4cc0cd9b4d71e7ee002c4f8c1f8a77">00222</a>   <a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083a3d4cc0cd9b4d71e7ee002c4f8c1f8a77">DMA2_Stream7_IRQn</a>           = 70,     
<a name="l00223"></a><a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083aa92bcb2bc3a87be869f05c5b07f04b8c">00223</a>   <a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083aa92bcb2bc3a87be869f05c5b07f04b8c">USART6_IRQn</a>                 = 71,     
<a name="l00224"></a><a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083a8326db2d570cb865ffa1d49fa29d562a">00224</a>   <a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083a8326db2d570cb865ffa1d49fa29d562a">I2C3_EV_IRQn</a>                = 72,     
<a name="l00225"></a><a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083a6e954232d164a6942ebc7a6bd6f7736e">00225</a>   <a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083a6e954232d164a6942ebc7a6bd6f7736e">I2C3_ER_IRQn</a>                = 73,     
<a name="l00226"></a><a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083a60b6cc4b6dbeca39e29a475d26c9e080">00226</a>   <a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083a60b6cc4b6dbeca39e29a475d26c9e080">OTG_HS_EP1_OUT_IRQn</a>         = 74,     
<a name="l00227"></a><a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083a1b040a7f76278a73cf5ea4c51f1be047">00227</a>   <a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083a1b040a7f76278a73cf5ea4c51f1be047">OTG_HS_EP1_IN_IRQn</a>          = 75,     
<a name="l00228"></a><a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083a9e5c9d81dd3985a88094f8158c0f0267">00228</a>   <a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083a9e5c9d81dd3985a88094f8158c0f0267">OTG_HS_WKUP_IRQn</a>            = 76,     
<a name="l00229"></a><a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083aad2d5e47d27fe3a02f7059b20bb729c0">00229</a>   <a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083aad2d5e47d27fe3a02f7059b20bb729c0">OTG_HS_IRQn</a>                 = 77,     
<a name="l00230"></a><a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083ace3c0fc2c4d05a7c02e3c987da5bc8e8">00230</a>   <a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083ace3c0fc2c4d05a7c02e3c987da5bc8e8">DCMI_IRQn</a>                   = 78,     
<a name="l00231"></a><a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083a70c9645bf48ca539510cc8f7d974f017">00231</a>   <a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083a70c9645bf48ca539510cc8f7d974f017">CRYP_IRQn</a>                   = 79,     
<a name="l00232"></a><a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083a86a161642b54055f9bbea3937e6352de">00232</a>   <a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083a86a161642b54055f9bbea3937e6352de">HASH_RNG_IRQn</a>               = 80,      
<a name="l00233"></a><a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083aa6b8ff01b016a798c6e639728c179e4f">00233</a>   <a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083aa6b8ff01b016a798c6e639728c179e4f">FPU_IRQn</a>                    = 81      
<a name="l00234"></a>00234 } <a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gac3af4a32370fb28c4ade8bf2add80251" title="STM32F4XX Interrupt Number Definition, according to the selected device in Library_configuration_sect...">IRQn_Type</a>;
<a name="l00235"></a>00235 
<a name="l00240"></a>00240 <span class="preprocessor">#include &quot;<a class="code" href="core__cm4_8h.html" title="CMSIS Cortex-M4 Core Peripheral Access Layer Header File.">core_cm4.h</a>&quot;</span>             <span class="comment">/* Cortex-M4 processor and core peripherals */</span>
<a name="l00241"></a>00241 <span class="preprocessor">#include &quot;<a class="code" href="system__stm32f4xx_8h.html" title="CMSIS Cortex-M4 Device System Source File for STM32F4xx devices.">system_stm32f4xx.h</a>&quot;</span>
<a name="l00242"></a>00242 <span class="preprocessor">#include &lt;stdint.h&gt;</span>
<a name="l00243"></a>00243 
<a name="l00248"></a><a class="code" href="group___exported__types.html#gae9b1af5c037e57a98884758875d3a7c4">00248</a> <span class="keyword">typedef</span> int32_t  <a class="code" href="group___exported__types.html#gae9b1af5c037e57a98884758875d3a7c4">s32</a>;
<a name="l00249"></a>00249 <span class="keyword">typedef</span> int16_t s16;
<a name="l00250"></a>00250 <span class="keyword">typedef</span> int8_t  s8;
<a name="l00251"></a>00251 
<a name="l00252"></a><a class="code" href="group___exported__types.html#gad97679599f3791409523fdb1c6156a28">00252</a> <span class="keyword">typedef</span> <span class="keyword">const</span> int32_t <a class="code" href="group___exported__types.html#gad97679599f3791409523fdb1c6156a28">sc32</a>;  
<a name="l00253"></a><a class="code" href="group___exported__types.html#ga66ab742a0751bb4e7661b8e874f2ddda">00253</a> <span class="keyword">typedef</span> <span class="keyword">const</span> int16_t <a class="code" href="group___exported__types.html#ga66ab742a0751bb4e7661b8e874f2ddda">sc16</a>;  
<a name="l00254"></a><a class="code" href="group___exported__types.html#ga30e6c0f6718e1b6d26dc9d94ddcf9d11">00254</a> <span class="keyword">typedef</span> <span class="keyword">const</span> int8_t <a class="code" href="group___exported__types.html#ga30e6c0f6718e1b6d26dc9d94ddcf9d11">sc8</a>;   
<a name="l00256"></a>00256 <span class="keyword">typedef</span> __IO int32_t  vs32;
<a name="l00257"></a>00257 <span class="keyword">typedef</span> __IO int16_t  vs16;
<a name="l00258"></a>00258 <span class="keyword">typedef</span> __IO int8_t   vs8;
<a name="l00259"></a>00259 
<a name="l00260"></a><a class="code" href="group___exported__types.html#gaec1d22666cf030b79051e5daa372fbc8">00260</a> <span class="keyword">typedef</span> __I int32_t <a class="code" href="group___exported__types.html#gaec1d22666cf030b79051e5daa372fbc8">vsc32</a>;  
<a name="l00261"></a><a class="code" href="group___exported__types.html#ga369ae0177b957e5afa7c1e62312f97c3">00261</a> <span class="keyword">typedef</span> __I int16_t <a class="code" href="group___exported__types.html#ga369ae0177b957e5afa7c1e62312f97c3">vsc16</a>;  
<a name="l00262"></a><a class="code" href="group___exported__types.html#ga47463bcded079ac61d5da46aff497803">00262</a> <span class="keyword">typedef</span> __I int8_t <a class="code" href="group___exported__types.html#ga47463bcded079ac61d5da46aff497803">vsc8</a>;   
<a name="l00264"></a>00264 <span class="keyword">typedef</span> uint32_t  u32;
<a name="l00265"></a>00265 <span class="keyword">typedef</span> uint16_t u16;
<a name="l00266"></a>00266 <span class="keyword">typedef</span> uint8_t  u8;
<a name="l00267"></a>00267 
<a name="l00268"></a><a class="code" href="group___exported__types.html#ga5b628e6a05856ff67e535fa391a57683">00268</a> <span class="keyword">typedef</span> <span class="keyword">const</span> uint32_t <a class="code" href="group___exported__types.html#ga5b628e6a05856ff67e535fa391a57683">uc32</a>;  
<a name="l00269"></a><a class="code" href="group___exported__types.html#gabc715ea3779494b5a4f53173a397f7cb">00269</a> <span class="keyword">typedef</span> <span class="keyword">const</span> uint16_t <a class="code" href="group___exported__types.html#gabc715ea3779494b5a4f53173a397f7cb">uc16</a>;  
<a name="l00270"></a><a class="code" href="group___exported__types.html#gac74022c74a461f810e0d4fdc9bfea480">00270</a> <span class="keyword">typedef</span> <span class="keyword">const</span> uint8_t <a class="code" href="group___exported__types.html#gac74022c74a461f810e0d4fdc9bfea480">uc8</a>;   
<a name="l00272"></a>00272 <span class="keyword">typedef</span> __IO uint32_t  vu32;
<a name="l00273"></a>00273 <span class="keyword">typedef</span> __IO uint16_t vu16;
<a name="l00274"></a>00274 <span class="keyword">typedef</span> __IO uint8_t  vu8;
<a name="l00275"></a>00275 
<a name="l00276"></a><a class="code" href="group___exported__types.html#ga2e08e321a35a55e72c5b3a507e76371f">00276</a> <span class="keyword">typedef</span> __I uint32_t <a class="code" href="group___exported__types.html#ga2e08e321a35a55e72c5b3a507e76371f">vuc32</a>;  
<a name="l00277"></a><a class="code" href="group___exported__types.html#ga7f6037565f0caa27727c8b871daf0d56">00277</a> <span class="keyword">typedef</span> __I uint16_t <a class="code" href="group___exported__types.html#ga7f6037565f0caa27727c8b871daf0d56">vuc16</a>;  
<a name="l00278"></a><a class="code" href="group___exported__types.html#gab0ec90ac9b2c5864755998c8d37c264a">00278</a> <span class="keyword">typedef</span> __I uint8_t <a class="code" href="group___exported__types.html#gab0ec90ac9b2c5864755998c8d37c264a">vuc8</a>;   
<a name="l00280"></a>00280 <span class="keyword">typedef</span> <span class="keyword">enum</span> {RESET = 0, SET = !RESET} FlagStatus, ITStatus;
<a name="l00281"></a>00281 
<a name="l00282"></a>00282 <span class="keyword">typedef</span> <span class="keyword">enum</span> {DISABLE = 0, ENABLE = !DISABLE} FunctionalState;
<a name="l00283"></a>00283 <span class="preprocessor">#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))</span>
<a name="l00284"></a>00284 <span class="preprocessor"></span>
<a name="l00285"></a>00285 <span class="keyword">typedef</span> <span class="keyword">enum</span> {ERROR = 0, SUCCESS = !ERROR} ErrorStatus;
<a name="l00286"></a>00286 
<a name="l00299"></a><a class="code" href="struct_a_d_c___type_def.html">00299</a> <span class="keyword">typedef</span> <span class="keyword">struct</span>
<a name="l00300"></a>00300 {
<a name="l00301"></a><a class="code" href="struct_a_d_c___type_def.html#af6aca2bbd40c0fb6df7c3aebe224a360">00301</a>   __IO uint32_t <a class="code" href="struct_a_d_c___type_def.html#af6aca2bbd40c0fb6df7c3aebe224a360">SR</a>;     
<a name="l00302"></a><a class="code" href="struct_a_d_c___type_def.html#ab0ec7102960640751d44e92ddac994f0">00302</a>   __IO uint32_t <a class="code" href="struct_a_d_c___type_def.html#ab0ec7102960640751d44e92ddac994f0">CR1</a>;    
<a name="l00303"></a><a class="code" href="struct_a_d_c___type_def.html#afdfa307571967afb1d97943e982b6586">00303</a>   __IO uint32_t <a class="code" href="struct_a_d_c___type_def.html#afdfa307571967afb1d97943e982b6586">CR2</a>;    
<a name="l00304"></a><a class="code" href="struct_a_d_c___type_def.html#af9d6c604e365c7d9d7601bf4ef373498">00304</a>   __IO uint32_t <a class="code" href="struct_a_d_c___type_def.html#af9d6c604e365c7d9d7601bf4ef373498">SMPR1</a>;  
<a name="l00305"></a><a class="code" href="struct_a_d_c___type_def.html#a6ac83fae8377c7b7fcae50fa4211b0e8">00305</a>   __IO uint32_t <a class="code" href="struct_a_d_c___type_def.html#a6ac83fae8377c7b7fcae50fa4211b0e8">SMPR2</a>;  
<a name="l00306"></a><a class="code" href="struct_a_d_c___type_def.html#a427dda1678f254bd98b1f321d7194a3b">00306</a>   __IO uint32_t <a class="code" href="struct_a_d_c___type_def.html#a427dda1678f254bd98b1f321d7194a3b">JOFR1</a>;  
<a name="l00307"></a><a class="code" href="struct_a_d_c___type_def.html#a11e65074b9f06b48c17cdfa5bea9f125">00307</a>   __IO uint32_t <a class="code" href="struct_a_d_c___type_def.html#a11e65074b9f06b48c17cdfa5bea9f125">JOFR2</a>;  
<a name="l00308"></a><a class="code" href="struct_a_d_c___type_def.html#a613f6b76d20c1a513976b920ecd7f4f8">00308</a>   __IO uint32_t <a class="code" href="struct_a_d_c___type_def.html#a613f6b76d20c1a513976b920ecd7f4f8">JOFR3</a>;  
<a name="l00309"></a><a class="code" href="struct_a_d_c___type_def.html#a2fd59854223e38158b4138ee8e913ab3">00309</a>   __IO uint32_t <a class="code" href="struct_a_d_c___type_def.html#a2fd59854223e38158b4138ee8e913ab3">JOFR4</a>;  
<a name="l00310"></a><a class="code" href="struct_a_d_c___type_def.html#a24c3512abcc90ef75cf3e9145e5dbe9b">00310</a>   __IO uint32_t <a class="code" href="struct_a_d_c___type_def.html#a24c3512abcc90ef75cf3e9145e5dbe9b">HTR</a>;    
<a name="l00311"></a><a class="code" href="struct_a_d_c___type_def.html#a9f8712dfef7125c0bb39db11f2b7416b">00311</a>   __IO uint32_t <a class="code" href="struct_a_d_c___type_def.html#a9f8712dfef7125c0bb39db11f2b7416b">LTR</a>;    
<a name="l00312"></a><a class="code" href="struct_a_d_c___type_def.html#a3302e1bcfdfbbfeb58779d0761fb377c">00312</a>   __IO uint32_t <a class="code" href="struct_a_d_c___type_def.html#a3302e1bcfdfbbfeb58779d0761fb377c">SQR1</a>;   
<a name="l00313"></a><a class="code" href="struct_a_d_c___type_def.html#aab440b0ad8631f5666dd32768a89cf60">00313</a>   __IO uint32_t <a class="code" href="struct_a_d_c___type_def.html#aab440b0ad8631f5666dd32768a89cf60">SQR2</a>;   
<a name="l00314"></a><a class="code" href="struct_a_d_c___type_def.html#a97e40d9928fa25a5628d6442f0aa6c0f">00314</a>   __IO uint32_t <a class="code" href="struct_a_d_c___type_def.html#a97e40d9928fa25a5628d6442f0aa6c0f">SQR3</a>;   
<a name="l00315"></a><a class="code" href="struct_a_d_c___type_def.html#a75e0cc079831adcc051df456737d3ae4">00315</a>   __IO uint32_t <a class="code" href="struct_a_d_c___type_def.html#a75e0cc079831adcc051df456737d3ae4">JSQR</a>;   
<a name="l00316"></a><a class="code" href="struct_a_d_c___type_def.html#a22fa21352be442bd02f9c26a1013d598">00316</a>   __IO uint32_t <a class="code" href="struct_a_d_c___type_def.html#a22fa21352be442bd02f9c26a1013d598">JDR1</a>;   
<a name="l00317"></a><a class="code" href="struct_a_d_c___type_def.html#ae9156af81694b7a85923348be45a2167">00317</a>   __IO uint32_t <a class="code" href="struct_a_d_c___type_def.html#ae9156af81694b7a85923348be45a2167">JDR2</a>;   
<a name="l00318"></a><a class="code" href="struct_a_d_c___type_def.html#a3a54028253a75a470fccf841178cba46">00318</a>   __IO uint32_t <a class="code" href="struct_a_d_c___type_def.html#a3a54028253a75a470fccf841178cba46">JDR3</a>;   
<a name="l00319"></a><a class="code" href="struct_a_d_c___type_def.html#a9274ceea3b2c6d5c1903d0a7abad91a1">00319</a>   __IO uint32_t <a class="code" href="struct_a_d_c___type_def.html#a9274ceea3b2c6d5c1903d0a7abad91a1">JDR4</a>;   
<a name="l00320"></a><a class="code" href="struct_a_d_c___type_def.html#a3df0d8dfcd1ec958659ffe21eb64fa94">00320</a>   __IO uint32_t <a class="code" href="struct_a_d_c___type_def.html#a3df0d8dfcd1ec958659ffe21eb64fa94">DR</a>;     
<a name="l00321"></a>00321 } <a class="code" href="struct_a_d_c___type_def.html" title="Analog to Digital Converter.">ADC_TypeDef</a>;
<a name="l00322"></a>00322 
<a name="l00323"></a><a class="code" href="struct_a_d_c___common___type_def.html">00323</a> <span class="keyword">typedef</span> <span class="keyword">struct</span>
<a name="l00324"></a>00324 {
<a name="l00325"></a><a class="code" href="struct_a_d_c___common___type_def.html#a876dd0a8546697065f406b7543e27af2">00325</a>   __IO uint32_t <a class="code" href="struct_a_d_c___common___type_def.html#a876dd0a8546697065f406b7543e27af2">CSR</a>;    
<a name="l00326"></a><a class="code" href="struct_a_d_c___common___type_def.html#a5e1322e27c40bf91d172f9673f205c97">00326</a>   __IO uint32_t <a class="code" href="struct_a_d_c___common___type_def.html#a5e1322e27c40bf91d172f9673f205c97">CCR</a>;    
<a name="l00327"></a><a class="code" href="struct_a_d_c___common___type_def.html#a760f86a1a18dffffda54fc15a977979f">00327</a>   __IO uint32_t CDR;    
<a name="l00329"></a>00329 } <a class="code" href="struct_a_d_c___common___type_def.html">ADC_Common_TypeDef</a>;
<a name="l00330"></a>00330 
<a name="l00331"></a>00331 
<a name="l00336"></a><a class="code" href="struct_c_a_n___tx_mail_box___type_def.html">00336</a> <span class="keyword">typedef</span> <span class="keyword">struct</span>
<a name="l00337"></a>00337 {
<a name="l00338"></a><a class="code" href="struct_c_a_n___tx_mail_box___type_def.html#a6921aa1c578a7d17c6e0eb33a73b6630">00338</a>   __IO uint32_t <a class="code" href="struct_c_a_n___tx_mail_box___type_def.html#a6921aa1c578a7d17c6e0eb33a73b6630">TIR</a>;  
<a name="l00339"></a><a class="code" href="struct_c_a_n___tx_mail_box___type_def.html#aed87bed042dd9523ce086119a3bab0ea">00339</a>   __IO uint32_t <a class="code" href="struct_c_a_n___tx_mail_box___type_def.html#aed87bed042dd9523ce086119a3bab0ea">TDTR</a>; 
<a name="l00340"></a><a class="code" href="struct_c_a_n___tx_mail_box___type_def.html#aded1359e1a32512910bff534d57ade68">00340</a>   __IO uint32_t <a class="code" href="struct_c_a_n___tx_mail_box___type_def.html#aded1359e1a32512910bff534d57ade68">TDLR</a>; 
<a name="l00341"></a><a class="code" href="struct_c_a_n___tx_mail_box___type_def.html#a90f7c1cf22683459c632d6040366eddf">00341</a>   __IO uint32_t <a class="code" href="struct_c_a_n___tx_mail_box___type_def.html#a90f7c1cf22683459c632d6040366eddf">TDHR</a>; 
<a name="l00342"></a>00342 } <a class="code" href="struct_c_a_n___tx_mail_box___type_def.html" title="Controller Area Network TxMailBox.">CAN_TxMailBox_TypeDef</a>;
<a name="l00343"></a>00343 
<a name="l00348"></a><a class="code" href="struct_c_a_n___f_i_f_o_mail_box___type_def.html">00348</a> <span class="keyword">typedef</span> <span class="keyword">struct</span>
<a name="l00349"></a>00349 {
<a name="l00350"></a><a class="code" href="struct_c_a_n___f_i_f_o_mail_box___type_def.html#a0acc8eb90b17bef5b9e03c7ddaacfb0b">00350</a>   __IO uint32_t <a class="code" href="struct_c_a_n___f_i_f_o_mail_box___type_def.html#a0acc8eb90b17bef5b9e03c7ddaacfb0b">RIR</a>;  
<a name="l00351"></a><a class="code" href="struct_c_a_n___f_i_f_o_mail_box___type_def.html#a9563d8a88d0db403b8357331bea83a2e">00351</a>   __IO uint32_t <a class="code" href="struct_c_a_n___f_i_f_o_mail_box___type_def.html#a9563d8a88d0db403b8357331bea83a2e">RDTR</a>; 
<a name="l00352"></a><a class="code" href="struct_c_a_n___f_i_f_o_mail_box___type_def.html#ae1c569688eedd49219cd505b9c22121b">00352</a>   __IO uint32_t <a class="code" href="struct_c_a_n___f_i_f_o_mail_box___type_def.html#ae1c569688eedd49219cd505b9c22121b">RDLR</a>; 
<a name="l00353"></a><a class="code" href="struct_c_a_n___f_i_f_o_mail_box___type_def.html#a7f11f42ba9d3bc5cd4a4f5ea0214608e">00353</a>   __IO uint32_t <a class="code" href="struct_c_a_n___f_i_f_o_mail_box___type_def.html#a7f11f42ba9d3bc5cd4a4f5ea0214608e">RDHR</a>; 
<a name="l00354"></a>00354 } <a class="code" href="struct_c_a_n___f_i_f_o_mail_box___type_def.html" title="Controller Area Network FIFOMailBox.">CAN_FIFOMailBox_TypeDef</a>;
<a name="l00355"></a>00355 
<a name="l00360"></a><a class="code" href="struct_c_a_n___filter_register___type_def.html">00360</a> <span class="keyword">typedef</span> <span class="keyword">struct</span>
<a name="l00361"></a>00361 {
<a name="l00362"></a><a class="code" href="struct_c_a_n___filter_register___type_def.html#a92036953ac673803fe001d843fea508b">00362</a>   __IO uint32_t <a class="code" href="struct_c_a_n___filter_register___type_def.html#a92036953ac673803fe001d843fea508b">FR1</a>; 
<a name="l00363"></a><a class="code" href="struct_c_a_n___filter_register___type_def.html#a7f7d80b45b7574463d7030fc8a464582">00363</a>   __IO uint32_t <a class="code" href="struct_c_a_n___filter_register___type_def.html#a7f7d80b45b7574463d7030fc8a464582">FR2</a>; 
<a name="l00364"></a>00364 } <a class="code" href="struct_c_a_n___filter_register___type_def.html" title="Controller Area Network FilterRegister.">CAN_FilterRegister_TypeDef</a>;
<a name="l00365"></a>00365 
<a name="l00370"></a><a class="code" href="struct_c_a_n___type_def.html">00370</a> <span class="keyword">typedef</span> <span class="keyword">struct</span>
<a name="l00371"></a>00371 {
<a name="l00372"></a><a class="code" href="struct_c_a_n___type_def.html#a27af4e9f888f0b7b1e8da7e002d98798">00372</a>   __IO uint32_t              <a class="code" href="struct_c_a_n___type_def.html#a27af4e9f888f0b7b1e8da7e002d98798">MCR</a>;                 
<a name="l00373"></a><a class="code" href="struct_c_a_n___type_def.html#acdd4c1b5466be103fb2bb2a225b1d3a9">00373</a>   __IO uint32_t              <a class="code" href="struct_c_a_n___type_def.html#acdd4c1b5466be103fb2bb2a225b1d3a9">MSR</a>;                 
<a name="l00374"></a><a class="code" href="struct_c_a_n___type_def.html#a87e3001757a0cd493785f1f3337dd0e8">00374</a>   __IO uint32_t              <a class="code" href="struct_c_a_n___type_def.html#a87e3001757a0cd493785f1f3337dd0e8">TSR</a>;                 
<a name="l00375"></a><a class="code" href="struct_c_a_n___type_def.html#accf4141cee239380d0ad4634ee21dbf6">00375</a>   __IO uint32_t              <a class="code" href="struct_c_a_n___type_def.html#accf4141cee239380d0ad4634ee21dbf6">RF0R</a>;                
<a name="l00376"></a><a class="code" href="struct_c_a_n___type_def.html#a02b589bb589df4f39e549dca4d5abb08">00376</a>   __IO uint32_t              <a class="code" href="struct_c_a_n___type_def.html#a02b589bb589df4f39e549dca4d5abb08">RF1R</a>;                
<a name="l00377"></a><a class="code" href="struct_c_a_n___type_def.html#a6566f8cfbd1d8aa7e8db046aa35e77db">00377</a>   __IO uint32_t              <a class="code" href="struct_c_a_n___type_def.html#a6566f8cfbd1d8aa7e8db046aa35e77db">IER</a>;                 
<a name="l00378"></a><a class="code" href="struct_c_a_n___type_def.html#a2b39f943954e0e7d177b511d9074a0b7">00378</a>   __IO uint32_t              <a class="code" href="struct_c_a_n___type_def.html#a2b39f943954e0e7d177b511d9074a0b7">ESR</a>;                 
<a name="l00379"></a><a class="code" href="struct_c_a_n___type_def.html#a5c0fcd3e7b4c59ab1dd68f6bd8f74e07">00379</a>   __IO uint32_t              <a class="code" href="struct_c_a_n___type_def.html#a5c0fcd3e7b4c59ab1dd68f6bd8f74e07">BTR</a>;                 
<a name="l00380"></a><a class="code" href="struct_c_a_n___type_def.html#aae28ab86a4ae57ed057ed1ea89a6d34b">00380</a>   uint32_t                   RESERVED0[88];       
<a name="l00381"></a><a class="code" href="struct_c_a_n___type_def.html#ae37503ab1a7bbd29846f94cdadf0a9ef">00381</a>   <a class="code" href="struct_c_a_n___tx_mail_box___type_def.html" title="Controller Area Network TxMailBox.">CAN_TxMailBox_TypeDef</a>      sTxMailBox[3];       
<a name="l00382"></a><a class="code" href="struct_c_a_n___type_def.html#a21b030b34e131f7ef6ea273416449fe4">00382</a>   <a class="code" href="struct_c_a_n___f_i_f_o_mail_box___type_def.html" title="Controller Area Network FIFOMailBox.">CAN_FIFOMailBox_TypeDef</a>    sFIFOMailBox[2];     
<a name="l00383"></a><a class="code" href="struct_c_a_n___type_def.html#a4bb07a7828fbd5fe86f6a5a3545c177d">00383</a>   uint32_t                   RESERVED1[12];       
<a name="l00384"></a><a class="code" href="struct_c_a_n___type_def.html#a1cb734df34f6520a7204c4c70634ebba">00384</a>   __IO uint32_t              <a class="code" href="struct_c_a_n___type_def.html#a1cb734df34f6520a7204c4c70634ebba">FMR</a>;                 
<a name="l00385"></a><a class="code" href="struct_c_a_n___type_def.html#aaa6f4cf1f16aaa6d17ec6c410db76acf">00385</a>   __IO uint32_t              <a class="code" href="struct_c_a_n___type_def.html#aaa6f4cf1f16aaa6d17ec6c410db76acf">FM1R</a>;                
<a name="l00386"></a><a class="code" href="struct_c_a_n___type_def.html#a4c9b972a304c0e08ca27cbe57627c496">00386</a>   uint32_t                   <a class="code" href="struct_c_a_n___type_def.html#a4c9b972a304c0e08ca27cbe57627c496">RESERVED2</a>;           
<a name="l00387"></a><a class="code" href="struct_c_a_n___type_def.html#aae0256ae42106ee7f87fc7e5bdb779d4">00387</a>   __IO uint32_t              <a class="code" href="struct_c_a_n___type_def.html#aae0256ae42106ee7f87fc7e5bdb779d4">FS1R</a>;                
<a name="l00388"></a><a class="code" href="struct_c_a_n___type_def.html#af2b40c5e36a5e861490988275499e158">00388</a>   uint32_t                   <a class="code" href="struct_c_a_n___type_def.html#af2b40c5e36a5e861490988275499e158">RESERVED3</a>;           
<a name="l00389"></a><a class="code" href="struct_c_a_n___type_def.html#af1405e594e39e5b34f9499f680157a25">00389</a>   __IO uint32_t              <a class="code" href="struct_c_a_n___type_def.html#af1405e594e39e5b34f9499f680157a25">FFA1R</a>;               
<a name="l00390"></a><a class="code" href="struct_c_a_n___type_def.html#ac0018930ee9f18afda25b695b9a4ec16">00390</a>   uint32_t                   <a class="code" href="struct_c_a_n___type_def.html#ac0018930ee9f18afda25b695b9a4ec16">RESERVED4</a>;           
<a name="l00391"></a><a class="code" href="struct_c_a_n___type_def.html#aaf76271f4ab0b3deb3ceb6e2ac0d62d0">00391</a>   __IO uint32_t              <a class="code" href="struct_c_a_n___type_def.html#aaf76271f4ab0b3deb3ceb6e2ac0d62d0">FA1R</a>;                
<a name="l00392"></a><a class="code" href="struct_c_a_n___type_def.html#a269f31b91d0f38a48061b76ecc346f55">00392</a>   uint32_t                   RESERVED5[8];        
<a name="l00393"></a><a class="code" href="struct_c_a_n___type_def.html#a31bd74513e6e599319702ad34113bf59">00393</a>   <a class="code" href="struct_c_a_n___filter_register___type_def.html" title="Controller Area Network FilterRegister.">CAN_FilterRegister_TypeDef</a> sFilterRegister[28]; 
<a name="l00394"></a>00394 } <a class="code" href="struct_c_a_n___type_def.html" title="Controller Area Network.">CAN_TypeDef</a>;
<a name="l00395"></a>00395 
<a name="l00400"></a><a class="code" href="struct_c_r_c___type_def.html">00400</a> <span class="keyword">typedef</span> <span class="keyword">struct</span>
<a name="l00401"></a>00401 {
<a name="l00402"></a><a class="code" href="struct_c_r_c___type_def.html#a3df0d8dfcd1ec958659ffe21eb64fa94">00402</a>   __IO uint32_t <a class="code" href="struct_c_r_c___type_def.html#a3df0d8dfcd1ec958659ffe21eb64fa94">DR</a>;         
<a name="l00403"></a><a class="code" href="struct_c_r_c___type_def.html#a601d7b0ba761c987db359b2d7173b7e0">00403</a>   __IO uint8_t  <a class="code" href="struct_c_r_c___type_def.html#a601d7b0ba761c987db359b2d7173b7e0">IDR</a>;        
<a name="l00404"></a><a class="code" href="struct_c_r_c___type_def.html#aa7d2bd5481ee985778c410a7e5826b71">00404</a>   uint8_t       <a class="code" href="struct_c_r_c___type_def.html#aa7d2bd5481ee985778c410a7e5826b71">RESERVED0</a>;  
<a name="l00405"></a><a class="code" href="struct_c_r_c___type_def.html#a8249a3955aace28d92109b391311eb30">00405</a>   uint16_t      <a class="code" href="struct_c_r_c___type_def.html#a8249a3955aace28d92109b391311eb30">RESERVED1</a>;  
<a name="l00406"></a><a class="code" href="struct_c_r_c___type_def.html#ab40c89c59391aaa9d9a8ec011dd0907a">00406</a>   __IO uint32_t <a class="code" href="struct_c_r_c___type_def.html#ab40c89c59391aaa9d9a8ec011dd0907a">CR</a>;         
<a name="l00407"></a>00407 } <a class="code" href="struct_c_r_c___type_def.html" title="CRC calculation unit.">CRC_TypeDef</a>;
<a name="l00408"></a>00408 
<a name="l00413"></a><a class="code" href="struct_d_a_c___type_def.html">00413</a> <span class="keyword">typedef</span> <span class="keyword">struct</span>
<a name="l00414"></a>00414 {
<a name="l00415"></a><a class="code" href="struct_d_a_c___type_def.html#ab40c89c59391aaa9d9a8ec011dd0907a">00415</a>   __IO uint32_t <a class="code" href="struct_d_a_c___type_def.html#ab40c89c59391aaa9d9a8ec011dd0907a">CR</a>;       
<a name="l00416"></a><a class="code" href="struct_d_a_c___type_def.html#a896bbb7153af0b67ad772360feaceeb4">00416</a>   __IO uint32_t <a class="code" href="struct_d_a_c___type_def.html#a896bbb7153af0b67ad772360feaceeb4">SWTRIGR</a>;  
<a name="l00417"></a><a class="code" href="struct_d_a_c___type_def.html#ac2bb55b037b800a25852736afdd7a258">00417</a>   __IO uint32_t <a class="code" href="struct_d_a_c___type_def.html#ac2bb55b037b800a25852736afdd7a258">DHR12R1</a>;  
<a name="l00418"></a><a class="code" href="struct_d_a_c___type_def.html#ae9028b8bcb5118b7073165fb50fcd559">00418</a>   __IO uint32_t <a class="code" href="struct_d_a_c___type_def.html#ae9028b8bcb5118b7073165fb50fcd559">DHR12L1</a>;  
<a name="l00419"></a><a class="code" href="struct_d_a_c___type_def.html#ad0a200e12acad17a5c7d2059159ea7e1">00419</a>   __IO uint32_t <a class="code" href="struct_d_a_c___type_def.html#ad0a200e12acad17a5c7d2059159ea7e1">DHR8R1</a>;   
<a name="l00420"></a><a class="code" href="struct_d_a_c___type_def.html#a804c7e15dbb587c7ea25511f6a7809f7">00420</a>   __IO uint32_t <a class="code" href="struct_d_a_c___type_def.html#a804c7e15dbb587c7ea25511f6a7809f7">DHR12R2</a>;  
<a name="l00421"></a><a class="code" href="struct_d_a_c___type_def.html#a2e45f9c9d67e384187b25334ba0a3e3d">00421</a>   __IO uint32_t <a class="code" href="struct_d_a_c___type_def.html#a2e45f9c9d67e384187b25334ba0a3e3d">DHR12L2</a>;  
<a name="l00422"></a><a class="code" href="struct_d_a_c___type_def.html#a4c435f0e34ace4421241cd5c3ae87fc2">00422</a>   __IO uint32_t <a class="code" href="struct_d_a_c___type_def.html#a4c435f0e34ace4421241cd5c3ae87fc2">DHR8R2</a>;   
<a name="l00423"></a><a class="code" href="struct_d_a_c___type_def.html#a1590b77e57f17e75193da259da72095e">00423</a>   __IO uint32_t <a class="code" href="struct_d_a_c___type_def.html#a1590b77e57f17e75193da259da72095e">DHR12RD</a>;  
<a name="l00424"></a><a class="code" href="struct_d_a_c___type_def.html#acc269320aff0a6482730224a4b641a59">00424</a>   __IO uint32_t <a class="code" href="struct_d_a_c___type_def.html#acc269320aff0a6482730224a4b641a59">DHR12LD</a>;  
<a name="l00425"></a><a class="code" href="struct_d_a_c___type_def.html#a9590269cba8412f1be96b0ddb846ef44">00425</a>   __IO uint32_t <a class="code" href="struct_d_a_c___type_def.html#a9590269cba8412f1be96b0ddb846ef44">DHR8RD</a>;   
<a name="l00426"></a><a class="code" href="struct_d_a_c___type_def.html#aa710505be03a41981c35bacc7ce20746">00426</a>   __IO uint32_t <a class="code" href="struct_d_a_c___type_def.html#aa710505be03a41981c35bacc7ce20746">DOR1</a>;     
<a name="l00427"></a><a class="code" href="struct_d_a_c___type_def.html#aba9fb810b0cf6cbc1280c5c63be2418b">00427</a>   __IO uint32_t <a class="code" href="struct_d_a_c___type_def.html#aba9fb810b0cf6cbc1280c5c63be2418b">DOR2</a>;     
<a name="l00428"></a><a class="code" href="struct_d_a_c___type_def.html#af6aca2bbd40c0fb6df7c3aebe224a360">00428</a>   __IO uint32_t <a class="code" href="struct_d_a_c___type_def.html#af6aca2bbd40c0fb6df7c3aebe224a360">SR</a>;       
<a name="l00429"></a>00429 } <a class="code" href="struct_d_a_c___type_def.html" title="Digital to Analog Converter.">DAC_TypeDef</a>;
<a name="l00430"></a>00430 
<a name="l00435"></a><a class="code" href="struct_d_b_g_m_c_u___type_def.html">00435</a> <span class="keyword">typedef</span> <span class="keyword">struct</span>
<a name="l00436"></a>00436 {
<a name="l00437"></a><a class="code" href="struct_d_b_g_m_c_u___type_def.html#a24df28d0e440321b21f6f07b3bb93dea">00437</a>   __IO uint32_t <a class="code" href="struct_d_b_g_m_c_u___type_def.html#a24df28d0e440321b21f6f07b3bb93dea">IDCODE</a>;  
<a name="l00438"></a><a class="code" href="struct_d_b_g_m_c_u___type_def.html#ab40c89c59391aaa9d9a8ec011dd0907a">00438</a>   __IO uint32_t <a class="code" href="struct_d_b_g_m_c_u___type_def.html#ab40c89c59391aaa9d9a8ec011dd0907a">CR</a>;      
<a name="l00439"></a><a class="code" href="struct_d_b_g_m_c_u___type_def.html#a5eaefc557573ae7bdc632ef6b6d574b5">00439</a>   __IO uint32_t <a class="code" href="struct_d_b_g_m_c_u___type_def.html#a5eaefc557573ae7bdc632ef6b6d574b5">APB1FZ</a>;  
<a name="l00440"></a><a class="code" href="struct_d_b_g_m_c_u___type_def.html#a4628a8c32f97ef93b15b2b503ef90c75">00440</a>   __IO uint32_t <a class="code" href="struct_d_b_g_m_c_u___type_def.html#a4628a8c32f97ef93b15b2b503ef90c75">APB2FZ</a>;  
<a name="l00441"></a>00441 }<a class="code" href="struct_d_b_g_m_c_u___type_def.html" title="Debug MCU.">DBGMCU_TypeDef</a>;
<a name="l00442"></a>00442 
<a name="l00447"></a><a class="code" href="struct_d_c_m_i___type_def.html">00447</a> <span class="keyword">typedef</span> <span class="keyword">struct</span>
<a name="l00448"></a>00448 {
<a name="l00449"></a><a class="code" href="struct_d_c_m_i___type_def.html#ab40c89c59391aaa9d9a8ec011dd0907a">00449</a>   __IO uint32_t <a class="code" href="struct_d_c_m_i___type_def.html#ab40c89c59391aaa9d9a8ec011dd0907a">CR</a>;       
<a name="l00450"></a><a class="code" href="struct_d_c_m_i___type_def.html#af6aca2bbd40c0fb6df7c3aebe224a360">00450</a>   __IO uint32_t <a class="code" href="struct_d_c_m_i___type_def.html#af6aca2bbd40c0fb6df7c3aebe224a360">SR</a>;       
<a name="l00451"></a><a class="code" href="struct_d_c_m_i___type_def.html#aa196fddf0ba7d6e3ce29bdb04eb38b94">00451</a>   __IO uint32_t <a class="code" href="struct_d_c_m_i___type_def.html#aa196fddf0ba7d6e3ce29bdb04eb38b94">RISR</a>;     
<a name="l00452"></a><a class="code" href="struct_d_c_m_i___type_def.html#a6566f8cfbd1d8aa7e8db046aa35e77db">00452</a>   __IO uint32_t <a class="code" href="struct_d_c_m_i___type_def.html#a6566f8cfbd1d8aa7e8db046aa35e77db">IER</a>;      
<a name="l00453"></a><a class="code" href="struct_d_c_m_i___type_def.html#a524e134cec519206cb41d0545e382978">00453</a>   __IO uint32_t <a class="code" href="struct_d_c_m_i___type_def.html#a524e134cec519206cb41d0545e382978">MISR</a>;     
<a name="l00454"></a><a class="code" href="struct_d_c_m_i___type_def.html#a0a8c8230846fd8ff154b9fde8dfa0399">00454</a>   __IO uint32_t <a class="code" href="struct_d_c_m_i___type_def.html#a0a8c8230846fd8ff154b9fde8dfa0399">ICR</a>;      
<a name="l00455"></a><a class="code" href="struct_d_c_m_i___type_def.html#a9cc4ec74be864c929261e0810f2fd7f0">00455</a>   __IO uint32_t <a class="code" href="struct_d_c_m_i___type_def.html#a9cc4ec74be864c929261e0810f2fd7f0">ESCR</a>;     
<a name="l00456"></a><a class="code" href="struct_d_c_m_i___type_def.html#af751d49ef824c1636c78822ecae066f4">00456</a>   __IO uint32_t <a class="code" href="struct_d_c_m_i___type_def.html#af751d49ef824c1636c78822ecae066f4">ESUR</a>;     
<a name="l00457"></a><a class="code" href="struct_d_c_m_i___type_def.html#a919b70dd8762e44263a02dfbafc7b8ce">00457</a>   __IO uint32_t <a class="code" href="struct_d_c_m_i___type_def.html#a919b70dd8762e44263a02dfbafc7b8ce">CWSTRTR</a>;  
<a name="l00458"></a><a class="code" href="struct_d_c_m_i___type_def.html#aa3ccc5d081bbee3c61ae9aa5e0c83af9">00458</a>   __IO uint32_t <a class="code" href="struct_d_c_m_i___type_def.html#aa3ccc5d081bbee3c61ae9aa5e0c83af9">CWSIZER</a>;  
<a name="l00459"></a><a class="code" href="struct_d_c_m_i___type_def.html#a3df0d8dfcd1ec958659ffe21eb64fa94">00459</a>   __IO uint32_t <a class="code" href="struct_d_c_m_i___type_def.html#a3df0d8dfcd1ec958659ffe21eb64fa94">DR</a>;       
<a name="l00460"></a>00460 } <a class="code" href="struct_d_c_m_i___type_def.html" title="DCMI.">DCMI_TypeDef</a>;
<a name="l00461"></a>00461 
<a name="l00466"></a><a class="code" href="struct_d_m_a___stream___type_def.html">00466</a> <span class="keyword">typedef</span> <span class="keyword">struct</span>
<a name="l00467"></a>00467 {
<a name="l00468"></a><a class="code" href="struct_d_m_a___stream___type_def.html#ab40c89c59391aaa9d9a8ec011dd0907a">00468</a>   __IO uint32_t <a class="code" href="struct_d_m_a___stream___type_def.html#ab40c89c59391aaa9d9a8ec011dd0907a">CR</a>;     
<a name="l00469"></a><a class="code" href="struct_d_m_a___stream___type_def.html#af60258ad5a25addc1e8969665d0c1731">00469</a>   __IO uint32_t <a class="code" href="struct_d_m_a___stream___type_def.html#af60258ad5a25addc1e8969665d0c1731">NDTR</a>;   
<a name="l00470"></a><a class="code" href="struct_d_m_a___stream___type_def.html#aef55be3d948c22dd32a97e8d4f8761fd">00470</a>   __IO uint32_t <a class="code" href="struct_d_m_a___stream___type_def.html#aef55be3d948c22dd32a97e8d4f8761fd">PAR</a>;    
<a name="l00471"></a><a class="code" href="struct_d_m_a___stream___type_def.html#a63b4d166f4ab5024db6b493a7ab7b640">00471</a>   __IO uint32_t <a class="code" href="struct_d_m_a___stream___type_def.html#a63b4d166f4ab5024db6b493a7ab7b640">M0AR</a>;   
<a name="l00472"></a><a class="code" href="struct_d_m_a___stream___type_def.html#aee7782244ceb4791d9a3891804ac47ac">00472</a>   __IO uint32_t <a class="code" href="struct_d_m_a___stream___type_def.html#aee7782244ceb4791d9a3891804ac47ac">M1AR</a>;   
<a name="l00473"></a><a class="code" href="struct_d_m_a___stream___type_def.html#a5d5cc7f32884945503dd29f8f6cbb415">00473</a>   __IO uint32_t <a class="code" href="struct_d_m_a___stream___type_def.html#a5d5cc7f32884945503dd29f8f6cbb415">FCR</a>;    
<a name="l00474"></a>00474 } <a class="code" href="struct_d_m_a___stream___type_def.html" title="DMA Controller.">DMA_Stream_TypeDef</a>;
<a name="l00475"></a>00475 
<a name="l00476"></a><a class="code" href="struct_d_m_a___type_def.html">00476</a> <span class="keyword">typedef</span> <span class="keyword">struct</span>
<a name="l00477"></a>00477 {
<a name="l00478"></a><a class="code" href="struct_d_m_a___type_def.html#a5cdef358e9e95b570358e1f6a3a7f492">00478</a>   __IO uint32_t <a class="code" href="struct_d_m_a___type_def.html#a5cdef358e9e95b570358e1f6a3a7f492">LISR</a>;   
<a name="l00479"></a><a class="code" href="struct_d_m_a___type_def.html#a6fe40f7ac1a18c2726b328b5ec02b262">00479</a>   __IO uint32_t <a class="code" href="struct_d_m_a___type_def.html#a6fe40f7ac1a18c2726b328b5ec02b262">HISR</a>;   
<a name="l00480"></a><a class="code" href="struct_d_m_a___type_def.html#ac4f7bf4cb172024bfc940c00167cd04e">00480</a>   __IO uint32_t <a class="code" href="struct_d_m_a___type_def.html#ac4f7bf4cb172024bfc940c00167cd04e">LIFCR</a>;  
<a name="l00481"></a><a class="code" href="struct_d_m_a___type_def.html#ac55c27aeea4107813c1e7da3fcf46961">00481</a>   __IO uint32_t <a class="code" href="struct_d_m_a___type_def.html#ac55c27aeea4107813c1e7da3fcf46961">HIFCR</a>;  
<a name="l00482"></a>00482 } <a class="code" href="struct_d_m_a___type_def.html">DMA_TypeDef</a>;
<a name="l00483"></a>00483 
<a name="l00488"></a><a class="code" href="struct_e_t_h___type_def.html">00488</a> <span class="keyword">typedef</span> <span class="keyword">struct</span>
<a name="l00489"></a>00489 {
<a name="l00490"></a>00490   __IO uint32_t MACCR;
<a name="l00491"></a>00491   __IO uint32_t MACFFR;
<a name="l00492"></a>00492   __IO uint32_t MACHTHR;
<a name="l00493"></a>00493   __IO uint32_t MACHTLR;
<a name="l00494"></a>00494   __IO uint32_t MACMIIAR;
<a name="l00495"></a>00495   __IO uint32_t MACMIIDR;
<a name="l00496"></a>00496   __IO uint32_t MACFCR;
<a name="l00497"></a>00497   __IO uint32_t MACVLANTR;             <span class="comment">/*    8 */</span>
<a name="l00498"></a>00498   uint32_t      RESERVED0[2];
<a name="l00499"></a>00499   __IO uint32_t MACRWUFFR;             <span class="comment">/*   11 */</span>
<a name="l00500"></a>00500   __IO uint32_t MACPMTCSR;
<a name="l00501"></a>00501   uint32_t      RESERVED1[2];
<a name="l00502"></a>00502   __IO uint32_t MACSR;                 <span class="comment">/*   15 */</span>
<a name="l00503"></a>00503   __IO uint32_t MACIMR;
<a name="l00504"></a>00504   __IO uint32_t MACA0HR;
<a name="l00505"></a>00505   __IO uint32_t MACA0LR;
<a name="l00506"></a>00506   __IO uint32_t MACA1HR;
<a name="l00507"></a>00507   __IO uint32_t MACA1LR;
<a name="l00508"></a>00508   __IO uint32_t MACA2HR;
<a name="l00509"></a>00509   __IO uint32_t MACA2LR;
<a name="l00510"></a>00510   __IO uint32_t MACA3HR;
<a name="l00511"></a>00511   __IO uint32_t MACA3LR;               <span class="comment">/*   24 */</span>
<a name="l00512"></a>00512   uint32_t      RESERVED2[40];
<a name="l00513"></a>00513   __IO uint32_t MMCCR;                 <span class="comment">/*   65 */</span>
<a name="l00514"></a>00514   __IO uint32_t MMCRIR;
<a name="l00515"></a>00515   __IO uint32_t MMCTIR;
<a name="l00516"></a>00516   __IO uint32_t MMCRIMR;
<a name="l00517"></a>00517   __IO uint32_t MMCTIMR;               <span class="comment">/*   69 */</span>
<a name="l00518"></a>00518   uint32_t      RESERVED3[14];
<a name="l00519"></a>00519   __IO uint32_t MMCTGFSCCR;            <span class="comment">/*   84 */</span>
<a name="l00520"></a>00520   __IO uint32_t MMCTGFMSCCR;
<a name="l00521"></a>00521   uint32_t      RESERVED4[5];
<a name="l00522"></a>00522   __IO uint32_t MMCTGFCR;
<a name="l00523"></a>00523   uint32_t      RESERVED5[10];
<a name="l00524"></a>00524   __IO uint32_t MMCRFCECR;
<a name="l00525"></a>00525   __IO uint32_t MMCRFAECR;
<a name="l00526"></a>00526   uint32_t      RESERVED6[10];
<a name="l00527"></a>00527   __IO uint32_t MMCRGUFCR;
<a name="l00528"></a>00528   uint32_t      RESERVED7[334];
<a name="l00529"></a>00529   __IO uint32_t PTPTSCR;
<a name="l00530"></a>00530   __IO uint32_t PTPSSIR;
<a name="l00531"></a>00531   __IO uint32_t PTPTSHR;
<a name="l00532"></a>00532   __IO uint32_t PTPTSLR;
<a name="l00533"></a>00533   __IO uint32_t PTPTSHUR;
<a name="l00534"></a>00534   __IO uint32_t PTPTSLUR;
<a name="l00535"></a>00535   __IO uint32_t PTPTSAR;
<a name="l00536"></a>00536   __IO uint32_t PTPTTHR;
<a name="l00537"></a>00537   __IO uint32_t PTPTTLR;
<a name="l00538"></a>00538   __IO uint32_t RESERVED8;
<a name="l00539"></a>00539   __IO uint32_t PTPTSSR;
<a name="l00540"></a>00540   uint32_t      RESERVED9[565];
<a name="l00541"></a>00541   __IO uint32_t DMABMR;
<a name="l00542"></a>00542   __IO uint32_t DMATPDR;
<a name="l00543"></a>00543   __IO uint32_t DMARPDR;
<a name="l00544"></a>00544   __IO uint32_t DMARDLAR;
<a name="l00545"></a>00545   __IO uint32_t DMATDLAR;
<a name="l00546"></a>00546   __IO uint32_t DMASR;
<a name="l00547"></a>00547   __IO uint32_t DMAOMR;
<a name="l00548"></a>00548   __IO uint32_t DMAIER;
<a name="l00549"></a>00549   __IO uint32_t DMAMFBOCR;
<a name="l00550"></a>00550   __IO uint32_t DMARSWTR;
<a name="l00551"></a>00551   uint32_t      RESERVED10[8];
<a name="l00552"></a>00552   __IO uint32_t DMACHTDR;
<a name="l00553"></a>00553   __IO uint32_t DMACHRDR;
<a name="l00554"></a>00554   __IO uint32_t DMACHTBAR;
<a name="l00555"></a>00555   __IO uint32_t DMACHRBAR;
<a name="l00556"></a>00556 } <a class="code" href="struct_e_t_h___type_def.html" title="Ethernet MAC.">ETH_TypeDef</a>;
<a name="l00557"></a>00557 
<a name="l00562"></a><a class="code" href="struct_e_x_t_i___type_def.html">00562</a> <span class="keyword">typedef</span> <span class="keyword">struct</span>
<a name="l00563"></a>00563 {
<a name="l00564"></a><a class="code" href="struct_e_x_t_i___type_def.html#ae845b86e973b4bf8a33c447c261633f6">00564</a>   __IO uint32_t <a class="code" href="struct_e_x_t_i___type_def.html#ae845b86e973b4bf8a33c447c261633f6">IMR</a>;    
<a name="l00565"></a><a class="code" href="struct_e_x_t_i___type_def.html#a6034c7458d8e6030f6dacecf0f1a3a89">00565</a>   __IO uint32_t <a class="code" href="struct_e_x_t_i___type_def.html#a6034c7458d8e6030f6dacecf0f1a3a89">EMR</a>;    
<a name="l00566"></a><a class="code" href="struct_e_x_t_i___type_def.html#a0d952a17455687d6e9053730d028fa1d">00566</a>   __IO uint32_t <a class="code" href="struct_e_x_t_i___type_def.html#a0d952a17455687d6e9053730d028fa1d">RTSR</a>;   
<a name="l00567"></a><a class="code" href="struct_e_x_t_i___type_def.html#aa0f7c828c46ae6f6bc9f66f11720bbe6">00567</a>   __IO uint32_t <a class="code" href="struct_e_x_t_i___type_def.html#aa0f7c828c46ae6f6bc9f66f11720bbe6">FTSR</a>;   
<a name="l00568"></a><a class="code" href="struct_e_x_t_i___type_def.html#a9eae93b6cc13d4d25e12f2224e2369c9">00568</a>   __IO uint32_t <a class="code" href="struct_e_x_t_i___type_def.html#a9eae93b6cc13d4d25e12f2224e2369c9">SWIER</a>;  
<a name="l00569"></a><a class="code" href="struct_e_x_t_i___type_def.html#af8d25514079514d38c104402f46470af">00569</a>   __IO uint32_t <a class="code" href="struct_e_x_t_i___type_def.html#af8d25514079514d38c104402f46470af">PR</a>;     
<a name="l00570"></a>00570 } <a class="code" href="struct_e_x_t_i___type_def.html" title="External Interrupt/Event Controller.">EXTI_TypeDef</a>;
<a name="l00571"></a>00571 
<a name="l00576"></a><a class="code" href="struct_f_l_a_s_h___type_def.html">00576</a> <span class="keyword">typedef</span> <span class="keyword">struct</span>
<a name="l00577"></a>00577 {
<a name="l00578"></a><a class="code" href="struct_f_l_a_s_h___type_def.html#a9cb55206b29a8c16354747c556ab8bea">00578</a>   __IO uint32_t <a class="code" href="struct_f_l_a_s_h___type_def.html#a9cb55206b29a8c16354747c556ab8bea">ACR</a>;      
<a name="l00579"></a><a class="code" href="struct_f_l_a_s_h___type_def.html#a84c491be6c66b1d5b6a2efd0740b3d0c">00579</a>   __IO uint32_t <a class="code" href="struct_f_l_a_s_h___type_def.html#a84c491be6c66b1d5b6a2efd0740b3d0c">KEYR</a>;     
<a name="l00580"></a><a class="code" href="struct_f_l_a_s_h___type_def.html#afc4900646681dfe1ca43133d376c4423">00580</a>   __IO uint32_t <a class="code" href="struct_f_l_a_s_h___type_def.html#afc4900646681dfe1ca43133d376c4423">OPTKEYR</a>;  
<a name="l00581"></a><a class="code" href="struct_f_l_a_s_h___type_def.html#af6aca2bbd40c0fb6df7c3aebe224a360">00581</a>   __IO uint32_t <a class="code" href="struct_f_l_a_s_h___type_def.html#af6aca2bbd40c0fb6df7c3aebe224a360">SR</a>;       
<a name="l00582"></a><a class="code" href="struct_f_l_a_s_h___type_def.html#ab40c89c59391aaa9d9a8ec011dd0907a">00582</a>   __IO uint32_t <a class="code" href="struct_f_l_a_s_h___type_def.html#ab40c89c59391aaa9d9a8ec011dd0907a">CR</a>;       
<a name="l00583"></a><a class="code" href="struct_f_l_a_s_h___type_def.html#acfef9b6d7da4271943edc04d7dfdf595">00583</a>   __IO uint32_t <a class="code" href="struct_f_l_a_s_h___type_def.html#acfef9b6d7da4271943edc04d7dfdf595">OPTCR</a>;    
<a name="l00584"></a>00584 } <a class="code" href="struct_f_l_a_s_h___type_def.html" title="FLASH Registers.">FLASH_TypeDef</a>;
<a name="l00585"></a>00585 
<a name="l00590"></a><a class="code" href="struct_f_s_m_c___bank1___type_def.html">00590</a> <span class="keyword">typedef</span> <span class="keyword">struct</span>
<a name="l00591"></a>00591 {
<a name="l00592"></a><a class="code" href="struct_f_s_m_c___bank1___type_def.html#a80a6708b507f6eecbc10424fdb088b79">00592</a>   __IO uint32_t BTCR[8];    
<a name="l00593"></a>00593 } <a class="code" href="struct_f_s_m_c___bank1___type_def.html" title="Flexible Static Memory Controller.">FSMC_Bank1_TypeDef</a>; 
<a name="l00594"></a>00594 
<a name="l00599"></a><a class="code" href="struct_f_s_m_c___bank1_e___type_def.html">00599</a> <span class="keyword">typedef</span> <span class="keyword">struct</span>
<a name="l00600"></a>00600 {
<a name="l00601"></a><a class="code" href="struct_f_s_m_c___bank1_e___type_def.html#a20f13b79c0f8670af319af0c5ebd5c91">00601</a>   __IO uint32_t BWTR[7];    
<a name="l00602"></a>00602 } <a class="code" href="struct_f_s_m_c___bank1_e___type_def.html" title="Flexible Static Memory Controller Bank1E.">FSMC_Bank1E_TypeDef</a>;
<a name="l00603"></a>00603 
<a name="l00608"></a><a class="code" href="struct_f_s_m_c___bank2___type_def.html">00608</a> <span class="keyword">typedef</span> <span class="keyword">struct</span>
<a name="l00609"></a>00609 {
<a name="l00610"></a><a class="code" href="struct_f_s_m_c___bank2___type_def.html#ab0cb1d704ee64c62ad5be55522a2683a">00610</a>   __IO uint32_t <a class="code" href="struct_f_s_m_c___bank2___type_def.html#ab0cb1d704ee64c62ad5be55522a2683a">PCR2</a>;       
<a name="l00611"></a><a class="code" href="struct_f_s_m_c___bank2___type_def.html#a89623ee198737b29dc0a803310605a83">00611</a>   __IO uint32_t <a class="code" href="struct_f_s_m_c___bank2___type_def.html#a89623ee198737b29dc0a803310605a83">SR2</a>;        
<a name="l00612"></a><a class="code" href="struct_f_s_m_c___bank2___type_def.html#a2e5a7a96de68a6612affa6df8c309c3d">00612</a>   __IO uint32_t <a class="code" href="struct_f_s_m_c___bank2___type_def.html#a2e5a7a96de68a6612affa6df8c309c3d">PMEM2</a>;      
<a name="l00613"></a><a class="code" href="struct_f_s_m_c___bank2___type_def.html#a9c1bc909ec5ed32df45444488ea6668b">00613</a>   __IO uint32_t <a class="code" href="struct_f_s_m_c___bank2___type_def.html#a9c1bc909ec5ed32df45444488ea6668b">PATT2</a>;      
<a name="l00614"></a><a class="code" href="struct_f_s_m_c___bank2___type_def.html#af86c61a5d38a4fc9cef942a12744486b">00614</a>   uint32_t      <a class="code" href="struct_f_s_m_c___bank2___type_def.html#af86c61a5d38a4fc9cef942a12744486b">RESERVED0</a>;  
<a name="l00615"></a><a class="code" href="struct_f_s_m_c___bank2___type_def.html#a05a47a1664adc7a3db3fa3e83fe883b4">00615</a>   __IO uint32_t <a class="code" href="struct_f_s_m_c___bank2___type_def.html#a05a47a1664adc7a3db3fa3e83fe883b4">ECCR2</a>;      
<a name="l00616"></a>00616 } <a class="code" href="struct_f_s_m_c___bank2___type_def.html" title="Flexible Static Memory Controller Bank2.">FSMC_Bank2_TypeDef</a>;
<a name="l00617"></a>00617 
<a name="l00622"></a><a class="code" href="struct_f_s_m_c___bank3___type_def.html">00622</a> <span class="keyword">typedef</span> <span class="keyword">struct</span>
<a name="l00623"></a>00623 {
<a name="l00624"></a><a class="code" href="struct_f_s_m_c___bank3___type_def.html#a73861fa74b83973fa1b5f92735c042ef">00624</a>   __IO uint32_t <a class="code" href="struct_f_s_m_c___bank3___type_def.html#a73861fa74b83973fa1b5f92735c042ef">PCR3</a>;       
<a name="l00625"></a><a class="code" href="struct_f_s_m_c___bank3___type_def.html#af30c34f7c606cb9416a413ec5fa36491">00625</a>   __IO uint32_t <a class="code" href="struct_f_s_m_c___bank3___type_def.html#af30c34f7c606cb9416a413ec5fa36491">SR3</a>;        
<a name="l00626"></a><a class="code" href="struct_f_s_m_c___bank3___type_def.html#aba8981e4f06cfb3db7d9959242052f80">00626</a>   __IO uint32_t <a class="code" href="struct_f_s_m_c___bank3___type_def.html#aba8981e4f06cfb3db7d9959242052f80">PMEM3</a>;      
<a name="l00627"></a><a class="code" href="struct_f_s_m_c___bank3___type_def.html#aba03fea9c1bb2242d963e29f1b94d25e">00627</a>   __IO uint32_t <a class="code" href="struct_f_s_m_c___bank3___type_def.html#aba03fea9c1bb2242d963e29f1b94d25e">PATT3</a>;      
<a name="l00628"></a><a class="code" href="struct_f_s_m_c___bank3___type_def.html#af86c61a5d38a4fc9cef942a12744486b">00628</a>   uint32_t      <a class="code" href="struct_f_s_m_c___bank3___type_def.html#af86c61a5d38a4fc9cef942a12744486b">RESERVED0</a>;  
<a name="l00629"></a><a class="code" href="struct_f_s_m_c___bank3___type_def.html#a6062be7dc144c07e01c303cb49d69ce2">00629</a>   __IO uint32_t <a class="code" href="struct_f_s_m_c___bank3___type_def.html#a6062be7dc144c07e01c303cb49d69ce2">ECCR3</a>;      
<a name="l00630"></a>00630 } <a class="code" href="struct_f_s_m_c___bank3___type_def.html" title="Flexible Static Memory Controller Bank3.">FSMC_Bank3_TypeDef</a>;
<a name="l00631"></a>00631 
<a name="l00636"></a><a class="code" href="struct_f_s_m_c___bank4___type_def.html">00636</a> <span class="keyword">typedef</span> <span class="keyword">struct</span>
<a name="l00637"></a>00637 {
<a name="l00638"></a><a class="code" href="struct_f_s_m_c___bank4___type_def.html#a2f02e7acfbd7e549ede84633215eb6a1">00638</a>   __IO uint32_t <a class="code" href="struct_f_s_m_c___bank4___type_def.html#a2f02e7acfbd7e549ede84633215eb6a1">PCR4</a>;       
<a name="l00639"></a><a class="code" href="struct_f_s_m_c___bank4___type_def.html#a8218d6e11dae5d4468c69303dec0b4fc">00639</a>   __IO uint32_t <a class="code" href="struct_f_s_m_c___bank4___type_def.html#a8218d6e11dae5d4468c69303dec0b4fc">SR4</a>;        
<a name="l00640"></a><a class="code" href="struct_f_s_m_c___bank4___type_def.html#a3f82cc749845fb0dd7dfa8121d96b663">00640</a>   __IO uint32_t <a class="code" href="struct_f_s_m_c___bank4___type_def.html#a3f82cc749845fb0dd7dfa8121d96b663">PMEM4</a>;      
<a name="l00641"></a><a class="code" href="struct_f_s_m_c___bank4___type_def.html#a955cad1aab7fb2d5b6e216cb29b5e7e2">00641</a>   __IO uint32_t <a class="code" href="struct_f_s_m_c___bank4___type_def.html#a955cad1aab7fb2d5b6e216cb29b5e7e2">PATT4</a>;      
<a name="l00642"></a><a class="code" href="struct_f_s_m_c___bank4___type_def.html#ac53cd7a08093a4ae8f4de4bcff67a64f">00642</a>   __IO uint32_t <a class="code" href="struct_f_s_m_c___bank4___type_def.html#ac53cd7a08093a4ae8f4de4bcff67a64f">PIO4</a>;       
<a name="l00643"></a>00643 } <a class="code" href="struct_f_s_m_c___bank4___type_def.html" title="Flexible Static Memory Controller Bank4.">FSMC_Bank4_TypeDef</a>; 
<a name="l00644"></a>00644 
<a name="l00649"></a><a class="code" href="struct_g_p_i_o___type_def.html">00649</a> <span class="keyword">typedef</span> <span class="keyword">struct</span>
<a name="l00650"></a>00650 {
<a name="l00651"></a><a class="code" href="struct_g_p_i_o___type_def.html#a2b671a94c63a612f81e0e9de8152d01c">00651</a>   __IO uint32_t <a class="code" href="struct_g_p_i_o___type_def.html#a2b671a94c63a612f81e0e9de8152d01c">MODER</a>;    
<a name="l00652"></a><a class="code" href="struct_g_p_i_o___type_def.html#a9543592bda60cb5261075594bdeedac9">00652</a>   __IO uint32_t <a class="code" href="struct_g_p_i_o___type_def.html#a9543592bda60cb5261075594bdeedac9">OTYPER</a>;   
<a name="l00653"></a><a class="code" href="struct_g_p_i_o___type_def.html#a328d16cc6213783ede54e4059ffd50a3">00653</a>   __IO uint32_t <a class="code" href="struct_g_p_i_o___type_def.html#a328d16cc6213783ede54e4059ffd50a3">OSPEEDR</a>;  
<a name="l00654"></a><a class="code" href="struct_g_p_i_o___type_def.html#abeed38529bd7b8de082e490e5d4f1727">00654</a>   __IO uint32_t <a class="code" href="struct_g_p_i_o___type_def.html#abeed38529bd7b8de082e490e5d4f1727">PUPDR</a>;    
<a name="l00655"></a><a class="code" href="struct_g_p_i_o___type_def.html#a328d2fe9ef1d513c3a97d30f98f0047c">00655</a>   __IO uint32_t <a class="code" href="struct_g_p_i_o___type_def.html#a328d2fe9ef1d513c3a97d30f98f0047c">IDR</a>;      
<a name="l00656"></a><a class="code" href="struct_g_p_i_o___type_def.html#abff7fffd2b5a718715a130006590c75c">00656</a>   __IO uint32_t <a class="code" href="struct_g_p_i_o___type_def.html#abff7fffd2b5a718715a130006590c75c">ODR</a>;      
<a name="l00657"></a><a class="code" href="struct_g_p_i_o___type_def.html#aa79204c9bcc8c481da0a5ffe7c74d8b0">00657</a>   __IO uint16_t <a class="code" href="struct_g_p_i_o___type_def.html#aa79204c9bcc8c481da0a5ffe7c74d8b0">BSRRL</a>;    
<a name="l00658"></a><a class="code" href="struct_g_p_i_o___type_def.html#a35f89f65edca7ed58738166424aeef48">00658</a>   __IO uint16_t <a class="code" href="struct_g_p_i_o___type_def.html#a35f89f65edca7ed58738166424aeef48">BSRRH</a>;    
<a name="l00659"></a><a class="code" href="struct_g_p_i_o___type_def.html#a2612a0f4b3fbdbb6293f6dc70105e190">00659</a>   __IO uint32_t <a class="code" href="struct_g_p_i_o___type_def.html#a2612a0f4b3fbdbb6293f6dc70105e190">LCKR</a>;     
<a name="l00660"></a><a class="code" href="struct_g_p_i_o___type_def.html#ab67c1158c04450d19ad483dcd2192e43">00660</a>   __IO uint32_t AFR[2];   
<a name="l00661"></a>00661 } <a class="code" href="struct_g_p_i_o___type_def.html" title="General Purpose I/O.">GPIO_TypeDef</a>;
<a name="l00662"></a>00662 
<a name="l00667"></a><a class="code" href="struct_s_y_s_c_f_g___type_def.html">00667</a> <span class="keyword">typedef</span> <span class="keyword">struct</span>
<a name="l00668"></a>00668 {
<a name="l00669"></a><a class="code" href="struct_s_y_s_c_f_g___type_def.html#ab36c409d0a009e3ce5a89ac55d3ff194">00669</a>   __IO uint32_t <a class="code" href="struct_s_y_s_c_f_g___type_def.html#ab36c409d0a009e3ce5a89ac55d3ff194">MEMRMP</a>;       
<a name="l00670"></a><a class="code" href="struct_s_y_s_c_f_g___type_def.html#a2130abf1fefb63ce4c4b138fd8c9822a">00670</a>   __IO uint32_t <a class="code" href="struct_s_y_s_c_f_g___type_def.html#a2130abf1fefb63ce4c4b138fd8c9822a">PMC</a>;          
<a name="l00671"></a><a class="code" href="struct_s_y_s_c_f_g___type_def.html#a52f7bf8003ba69d66a4e86dea6eeab65">00671</a>   __IO uint32_t EXTICR[4];    
<a name="l00672"></a><a class="code" href="struct_s_y_s_c_f_g___type_def.html#afaf27b66c1edc60064db3fa6e693fb59">00672</a>   uint32_t      RESERVED[2];  
<a name="l00673"></a><a class="code" href="struct_s_y_s_c_f_g___type_def.html#a08ddbac546fa9928256654d31255c8c3">00673</a>   __IO uint32_t <a class="code" href="struct_s_y_s_c_f_g___type_def.html#a08ddbac546fa9928256654d31255c8c3">CMPCR</a>;        
<a name="l00674"></a>00674 } <a class="code" href="struct_s_y_s_c_f_g___type_def.html" title="System configuration controller.">SYSCFG_TypeDef</a>;
<a name="l00675"></a>00675 
<a name="l00680"></a><a class="code" href="struct_i2_c___type_def.html">00680</a> <span class="keyword">typedef</span> <span class="keyword">struct</span>
<a name="l00681"></a>00681 {
<a name="l00682"></a><a class="code" href="struct_i2_c___type_def.html#a61400ce239355b62aa25c95fcc18a5e1">00682</a>   __IO uint16_t <a class="code" href="struct_i2_c___type_def.html#a61400ce239355b62aa25c95fcc18a5e1">CR1</a>;        
<a name="l00683"></a><a class="code" href="struct_i2_c___type_def.html#a149feba01f9c4a49570c6d88619f504f">00683</a>   uint16_t      <a class="code" href="struct_i2_c___type_def.html#a149feba01f9c4a49570c6d88619f504f">RESERVED0</a>;  
<a name="l00684"></a><a class="code" href="struct_i2_c___type_def.html#a2a3e81bd118d1bc52d24a0b0772e6a0c">00684</a>   __IO uint16_t <a class="code" href="struct_i2_c___type_def.html#a2a3e81bd118d1bc52d24a0b0772e6a0c">CR2</a>;        
<a name="l00685"></a><a class="code" href="struct_i2_c___type_def.html#a8249a3955aace28d92109b391311eb30">00685</a>   uint16_t      <a class="code" href="struct_i2_c___type_def.html#a8249a3955aace28d92109b391311eb30">RESERVED1</a>;  
<a name="l00686"></a><a class="code" href="struct_i2_c___type_def.html#aaab934113da0a8bcacd1ffa148046569">00686</a>   __IO uint16_t <a class="code" href="struct_i2_c___type_def.html#aaab934113da0a8bcacd1ffa148046569">OAR1</a>;       
<a name="l00687"></a><a class="code" href="struct_i2_c___type_def.html#a5573848497a716a9947fd87487709feb">00687</a>   uint16_t      <a class="code" href="struct_i2_c___type_def.html#a5573848497a716a9947fd87487709feb">RESERVED2</a>;  
<a name="l00688"></a><a class="code" href="struct_i2_c___type_def.html#a692c0f6e38cde9ec1c3c50c36aa79817">00688</a>   __IO uint16_t <a class="code" href="struct_i2_c___type_def.html#a692c0f6e38cde9ec1c3c50c36aa79817">OAR2</a>;       
<a name="l00689"></a><a class="code" href="struct_i2_c___type_def.html#a6c3b31022e6f59b800e9f5cc2a89d54c">00689</a>   uint16_t      <a class="code" href="struct_i2_c___type_def.html#a6c3b31022e6f59b800e9f5cc2a89d54c">RESERVED3</a>;  
<a name="l00690"></a><a class="code" href="struct_i2_c___type_def.html#a0a1acc0425516ff7969709d118b96a3b">00690</a>   __IO uint16_t <a class="code" href="struct_i2_c___type_def.html#a0a1acc0425516ff7969709d118b96a3b">DR</a>;         
<a name="l00691"></a><a class="code" href="struct_i2_c___type_def.html#aa0223808025f5bf9c056185038c9d545">00691</a>   uint16_t      <a class="code" href="struct_i2_c___type_def.html#aa0223808025f5bf9c056185038c9d545">RESERVED4</a>;  
<a name="l00692"></a><a class="code" href="struct_i2_c___type_def.html#a1e79a16729e8d1032d9fe552d50dce41">00692</a>   __IO uint16_t <a class="code" href="struct_i2_c___type_def.html#a1e79a16729e8d1032d9fe552d50dce41">SR1</a>;        
<a name="l00693"></a><a class="code" href="struct_i2_c___type_def.html#abd36010ac282682d1f3c641b183b1b6f">00693</a>   uint16_t      <a class="code" href="struct_i2_c___type_def.html#abd36010ac282682d1f3c641b183b1b6f">RESERVED5</a>;  
<a name="l00694"></a><a class="code" href="struct_i2_c___type_def.html#a682809d3f8187cdefb9d615e89b67e65">00694</a>   __IO uint16_t <a class="code" href="struct_i2_c___type_def.html#a682809d3f8187cdefb9d615e89b67e65">SR2</a>;        
<a name="l00695"></a><a class="code" href="struct_i2_c___type_def.html#aab502dde158ab7da8e7823d1f8a06edb">00695</a>   uint16_t      <a class="code" href="struct_i2_c___type_def.html#aab502dde158ab7da8e7823d1f8a06edb">RESERVED6</a>;  
<a name="l00696"></a><a class="code" href="struct_i2_c___type_def.html#a7ac198788f460fa6379bceecab79c5f7">00696</a>   __IO uint16_t <a class="code" href="struct_i2_c___type_def.html#a7ac198788f460fa6379bceecab79c5f7">CCR</a>;        
<a name="l00697"></a><a class="code" href="struct_i2_c___type_def.html#ab1820c97e368d349f5f4121f015d9fab">00697</a>   uint16_t      <a class="code" href="struct_i2_c___type_def.html#ab1820c97e368d349f5f4121f015d9fab">RESERVED7</a>;  
<a name="l00698"></a><a class="code" href="struct_i2_c___type_def.html#a7fbb70132ee565bb179078b6ee20cc2b">00698</a>   __IO uint16_t <a class="code" href="struct_i2_c___type_def.html#a7fbb70132ee565bb179078b6ee20cc2b">TRISE</a>;      
<a name="l00699"></a><a class="code" href="struct_i2_c___type_def.html#afc22764fbf9ee7ce28174d65d0260f18">00699</a>   uint16_t      <a class="code" href="struct_i2_c___type_def.html#afc22764fbf9ee7ce28174d65d0260f18">RESERVED8</a>;  
<a name="l00700"></a>00700 } <a class="code" href="struct_i2_c___type_def.html" title="Inter-integrated Circuit Interface.">I2C_TypeDef</a>;
<a name="l00701"></a>00701 
<a name="l00706"></a><a class="code" href="struct_i_w_d_g___type_def.html">00706</a> <span class="keyword">typedef</span> <span class="keyword">struct</span>
<a name="l00707"></a>00707 {
<a name="l00708"></a><a class="code" href="struct_i_w_d_g___type_def.html#a2f692354bde770f2a5e3e1b294ec064b">00708</a>   __IO uint32_t <a class="code" href="struct_i_w_d_g___type_def.html#a2f692354bde770f2a5e3e1b294ec064b">KR</a>;   
<a name="l00709"></a><a class="code" href="struct_i_w_d_g___type_def.html#af8d25514079514d38c104402f46470af">00709</a>   __IO uint32_t <a class="code" href="struct_i_w_d_g___type_def.html#af8d25514079514d38c104402f46470af">PR</a>;   
<a name="l00710"></a><a class="code" href="struct_i_w_d_g___type_def.html#a7015e1046dbd3ea8783b33dc11a69e52">00710</a>   __IO uint32_t <a class="code" href="struct_i_w_d_g___type_def.html#a7015e1046dbd3ea8783b33dc11a69e52">RLR</a>;  
<a name="l00711"></a><a class="code" href="struct_i_w_d_g___type_def.html#af6aca2bbd40c0fb6df7c3aebe224a360">00711</a>   __IO uint32_t <a class="code" href="struct_i_w_d_g___type_def.html#af6aca2bbd40c0fb6df7c3aebe224a360">SR</a>;   
<a name="l00712"></a>00712 } <a class="code" href="struct_i_w_d_g___type_def.html" title="Independent WATCHDOG.">IWDG_TypeDef</a>;
<a name="l00713"></a>00713 
<a name="l00718"></a><a class="code" href="struct_p_w_r___type_def.html">00718</a> <span class="keyword">typedef</span> <span class="keyword">struct</span>
<a name="l00719"></a>00719 {
<a name="l00720"></a><a class="code" href="struct_p_w_r___type_def.html#ab40c89c59391aaa9d9a8ec011dd0907a">00720</a>   __IO uint32_t <a class="code" href="struct_p_w_r___type_def.html#ab40c89c59391aaa9d9a8ec011dd0907a">CR</a>;   
<a name="l00721"></a><a class="code" href="struct_p_w_r___type_def.html#a876dd0a8546697065f406b7543e27af2">00721</a>   __IO uint32_t <a class="code" href="struct_p_w_r___type_def.html#a876dd0a8546697065f406b7543e27af2">CSR</a>;  
<a name="l00722"></a>00722 } <a class="code" href="struct_p_w_r___type_def.html" title="Power Control.">PWR_TypeDef</a>;
<a name="l00723"></a>00723 
<a name="l00728"></a><a class="code" href="struct_r_c_c___type_def.html">00728</a> <span class="keyword">typedef</span> <span class="keyword">struct</span>
<a name="l00729"></a>00729 {
<a name="l00730"></a><a class="code" href="struct_r_c_c___type_def.html#ab40c89c59391aaa9d9a8ec011dd0907a">00730</a>   __IO uint32_t <a class="code" href="struct_r_c_c___type_def.html#ab40c89c59391aaa9d9a8ec011dd0907a">CR</a>;            
<a name="l00731"></a><a class="code" href="struct_r_c_c___type_def.html#ae6ff257862eba6b4b367feea786bf1fd">00731</a>   __IO uint32_t <a class="code" href="struct_r_c_c___type_def.html#ae6ff257862eba6b4b367feea786bf1fd">PLLCFGR</a>;       
<a name="l00732"></a><a class="code" href="struct_r_c_c___type_def.html#a26f1e746ccbf9c9f67e7c60e61085ec1">00732</a>   __IO uint32_t <a class="code" href="struct_r_c_c___type_def.html#a26f1e746ccbf9c9f67e7c60e61085ec1">CFGR</a>;          
<a name="l00733"></a><a class="code" href="struct_r_c_c___type_def.html#a907d8154c80b7e385478943f90b17a3b">00733</a>   __IO uint32_t <a class="code" href="struct_r_c_c___type_def.html#a907d8154c80b7e385478943f90b17a3b">CIR</a>;           
<a name="l00734"></a><a class="code" href="struct_r_c_c___type_def.html#a46c20c598e9e12f919f0ea47ebcbc90f">00734</a>   __IO uint32_t <a class="code" href="struct_r_c_c___type_def.html#a46c20c598e9e12f919f0ea47ebcbc90f">AHB1RSTR</a>;      
<a name="l00735"></a><a class="code" href="struct_r_c_c___type_def.html#a78a5aa9dd5694c48a7d8e66888a46450">00735</a>   __IO uint32_t <a class="code" href="struct_r_c_c___type_def.html#a78a5aa9dd5694c48a7d8e66888a46450">AHB2RSTR</a>;      
<a name="l00736"></a><a class="code" href="struct_r_c_c___type_def.html#a28560c5bfeb45326ea7f2019dba57bea">00736</a>   __IO uint32_t <a class="code" href="struct_r_c_c___type_def.html#a28560c5bfeb45326ea7f2019dba57bea">AHB3RSTR</a>;      
<a name="l00737"></a><a class="code" href="struct_r_c_c___type_def.html#af86c61a5d38a4fc9cef942a12744486b">00737</a>   uint32_t      <a class="code" href="struct_r_c_c___type_def.html#af86c61a5d38a4fc9cef942a12744486b">RESERVED0</a>;     
<a name="l00738"></a><a class="code" href="struct_r_c_c___type_def.html#a7da5d372374bc59e9b9af750b01d6a78">00738</a>   __IO uint32_t <a class="code" href="struct_r_c_c___type_def.html#a7da5d372374bc59e9b9af750b01d6a78">APB1RSTR</a>;      
<a name="l00739"></a><a class="code" href="struct_r_c_c___type_def.html#ab2c5389c9ff4ac188cd498b8f7170968">00739</a>   __IO uint32_t <a class="code" href="struct_r_c_c___type_def.html#ab2c5389c9ff4ac188cd498b8f7170968">APB2RSTR</a>;      
<a name="l00740"></a><a class="code" href="struct_r_c_c___type_def.html#a28d88d9a08aab1adbebea61c42ef901e">00740</a>   uint32_t      RESERVED1[2];  
<a name="l00741"></a><a class="code" href="struct_r_c_c___type_def.html#a1e9c75b06c99d0611535f38c7b4aa845">00741</a>   __IO uint32_t <a class="code" href="struct_r_c_c___type_def.html#a1e9c75b06c99d0611535f38c7b4aa845">AHB1ENR</a>;       
<a name="l00742"></a><a class="code" href="struct_r_c_c___type_def.html#a5e92ed32c33c92e7ebf6919400ad535b">00742</a>   __IO uint32_t <a class="code" href="struct_r_c_c___type_def.html#a5e92ed32c33c92e7ebf6919400ad535b">AHB2ENR</a>;       
<a name="l00743"></a><a class="code" href="struct_r_c_c___type_def.html#acdaa650fcd63730825479f6e8f70d4c0">00743</a>   __IO uint32_t <a class="code" href="struct_r_c_c___type_def.html#acdaa650fcd63730825479f6e8f70d4c0">AHB3ENR</a>;       
<a name="l00744"></a><a class="code" href="struct_r_c_c___type_def.html#a4c9b972a304c0e08ca27cbe57627c496">00744</a>   uint32_t      <a class="code" href="struct_r_c_c___type_def.html#a4c9b972a304c0e08ca27cbe57627c496">RESERVED2</a>;     
<a name="l00745"></a><a class="code" href="struct_r_c_c___type_def.html#ac88901e2eb35079b7b58a185e6bf554c">00745</a>   __IO uint32_t <a class="code" href="struct_r_c_c___type_def.html#ac88901e2eb35079b7b58a185e6bf554c">APB1ENR</a>;       
<a name="l00746"></a><a class="code" href="struct_r_c_c___type_def.html#acc7bb47dddd2d94de124f74886d919be">00746</a>   __IO uint32_t <a class="code" href="struct_r_c_c___type_def.html#acc7bb47dddd2d94de124f74886d919be">APB2ENR</a>;       
<a name="l00747"></a><a class="code" href="struct_r_c_c___type_def.html#ab6f0f833dbe064708de75d95c68c32fd">00747</a>   uint32_t      RESERVED3[2];  
<a name="l00748"></a><a class="code" href="struct_r_c_c___type_def.html#aae70b1922167eb58d564cb82d39fd10b">00748</a>   __IO uint32_t <a class="code" href="struct_r_c_c___type_def.html#aae70b1922167eb58d564cb82d39fd10b">AHB1LPENR</a>;     
<a name="l00749"></a><a class="code" href="struct_r_c_c___type_def.html#a2b30982547fae7d545d260312771b5c9">00749</a>   __IO uint32_t <a class="code" href="struct_r_c_c___type_def.html#a2b30982547fae7d545d260312771b5c9">AHB2LPENR</a>;     
<a name="l00750"></a><a class="code" href="struct_r_c_c___type_def.html#a2ff82b9bf0231645108965aa0febd766">00750</a>   __IO uint32_t <a class="code" href="struct_r_c_c___type_def.html#a2ff82b9bf0231645108965aa0febd766">AHB3LPENR</a>;     
<a name="l00751"></a><a class="code" href="struct_r_c_c___type_def.html#ac0018930ee9f18afda25b695b9a4ec16">00751</a>   uint32_t      <a class="code" href="struct_r_c_c___type_def.html#ac0018930ee9f18afda25b695b9a4ec16">RESERVED4</a>;     
<a name="l00752"></a><a class="code" href="struct_r_c_c___type_def.html#ad85a9951a7be79fe08ffc90f796f071b">00752</a>   __IO uint32_t <a class="code" href="struct_r_c_c___type_def.html#ad85a9951a7be79fe08ffc90f796f071b">APB1LPENR</a>;     
<a name="l00753"></a><a class="code" href="struct_r_c_c___type_def.html#aba51c57f9506e14a6f5983526c78943b">00753</a>   __IO uint32_t <a class="code" href="struct_r_c_c___type_def.html#aba51c57f9506e14a6f5983526c78943b">APB2LPENR</a>;     
<a name="l00754"></a><a class="code" href="struct_r_c_c___type_def.html#ac0eb05794aeee3b4ed69c8fe54c9be3b">00754</a>   uint32_t      RESERVED5[2];  
<a name="l00755"></a><a class="code" href="struct_r_c_c___type_def.html#a0b9a3ced775287c8585a6a61af4b40e9">00755</a>   __IO uint32_t <a class="code" href="struct_r_c_c___type_def.html#a0b9a3ced775287c8585a6a61af4b40e9">BDCR</a>;          
<a name="l00756"></a><a class="code" href="struct_r_c_c___type_def.html#a876dd0a8546697065f406b7543e27af2">00756</a>   __IO uint32_t <a class="code" href="struct_r_c_c___type_def.html#a876dd0a8546697065f406b7543e27af2">CSR</a>;           
<a name="l00757"></a><a class="code" href="struct_r_c_c___type_def.html#a10da398d74a1f88d5b42bd40718d9447">00757</a>   uint32_t      RESERVED6[2];  
<a name="l00758"></a><a class="code" href="struct_r_c_c___type_def.html#aaef3da59eaf7c6dfdf9a12fd60ce58a8">00758</a>   __IO uint32_t <a class="code" href="struct_r_c_c___type_def.html#aaef3da59eaf7c6dfdf9a12fd60ce58a8">SSCGR</a>;         
<a name="l00759"></a><a class="code" href="struct_r_c_c___type_def.html#a2d08d5f995ed77228eb56741184a1bb6">00759</a>   __IO uint32_t <a class="code" href="struct_r_c_c___type_def.html#a2d08d5f995ed77228eb56741184a1bb6">PLLI2SCFGR</a>;    
<a name="l00760"></a>00760 } <a class="code" href="struct_r_c_c___type_def.html" title="Reset and Clock Control.">RCC_TypeDef</a>;
<a name="l00761"></a>00761 
<a name="l00766"></a><a class="code" href="struct_r_t_c___type_def.html">00766</a> <span class="keyword">typedef</span> <span class="keyword">struct</span>
<a name="l00767"></a>00767 {
<a name="l00768"></a><a class="code" href="struct_r_t_c___type_def.html#a63d179b7a36a715dce7203858d3be132">00768</a>   __IO uint32_t <a class="code" href="struct_r_t_c___type_def.html#a63d179b7a36a715dce7203858d3be132">TR</a>;      
<a name="l00769"></a><a class="code" href="struct_r_t_c___type_def.html#a3df0d8dfcd1ec958659ffe21eb64fa94">00769</a>   __IO uint32_t <a class="code" href="struct_r_t_c___type_def.html#a3df0d8dfcd1ec958659ffe21eb64fa94">DR</a>;      
<a name="l00770"></a><a class="code" href="struct_r_t_c___type_def.html#ab40c89c59391aaa9d9a8ec011dd0907a">00770</a>   __IO uint32_t <a class="code" href="struct_r_t_c___type_def.html#ab40c89c59391aaa9d9a8ec011dd0907a">CR</a>;      
<a name="l00771"></a><a class="code" href="struct_r_t_c___type_def.html#ab3c49a96815fcbee63d95e1e74f20e75">00771</a>   __IO uint32_t <a class="code" href="struct_r_t_c___type_def.html#ab3c49a96815fcbee63d95e1e74f20e75">ISR</a>;     
<a name="l00772"></a><a class="code" href="struct_r_t_c___type_def.html#ac9b4c6c5b29f3461ce3f875eea69f35b">00772</a>   __IO uint32_t <a class="code" href="struct_r_t_c___type_def.html#ac9b4c6c5b29f3461ce3f875eea69f35b">PRER</a>;    
<a name="l00773"></a><a class="code" href="struct_r_t_c___type_def.html#ac5b3c8be61045a304d3076d4714d29f2">00773</a>   __IO uint32_t <a class="code" href="struct_r_t_c___type_def.html#ac5b3c8be61045a304d3076d4714d29f2">WUTR</a>;    
<a name="l00774"></a><a class="code" href="struct_r_t_c___type_def.html#ab97f3e9584dda705dc10a5f4c5f6e636">00774</a>   __IO uint32_t <a class="code" href="struct_r_t_c___type_def.html#ab97f3e9584dda705dc10a5f4c5f6e636">CALIBR</a>;  
<a name="l00775"></a><a class="code" href="struct_r_t_c___type_def.html#ac005b1a5bc52634d5a34578cc9d2c3f6">00775</a>   __IO uint32_t <a class="code" href="struct_r_t_c___type_def.html#ac005b1a5bc52634d5a34578cc9d2c3f6">ALRMAR</a>;  
<a name="l00776"></a><a class="code" href="struct_r_t_c___type_def.html#a4e513deb9f58a138ad9f317cc5a3555d">00776</a>   __IO uint32_t <a class="code" href="struct_r_t_c___type_def.html#a4e513deb9f58a138ad9f317cc5a3555d">ALRMBR</a>;  
<a name="l00777"></a><a class="code" href="struct_r_t_c___type_def.html#a6204786b050eb135fabb15784698e86e">00777</a>   __IO uint32_t <a class="code" href="struct_r_t_c___type_def.html#a6204786b050eb135fabb15784698e86e">WPR</a>;     
<a name="l00778"></a><a class="code" href="struct_r_t_c___type_def.html#a8a868e5e76b52ced04c536be3dee08ec">00778</a>   __IO uint32_t <a class="code" href="struct_r_t_c___type_def.html#a8a868e5e76b52ced04c536be3dee08ec">SSR</a>;     
<a name="l00779"></a><a class="code" href="struct_r_t_c___type_def.html#a2372c05a6c5508e0a9adada793f68b4f">00779</a>   __IO uint32_t <a class="code" href="struct_r_t_c___type_def.html#a2372c05a6c5508e0a9adada793f68b4f">SHIFTR</a>;  
<a name="l00780"></a><a class="code" href="struct_r_t_c___type_def.html#a042059c8b4168681d6aecf30211dd7b8">00780</a>   __IO uint32_t <a class="code" href="struct_r_t_c___type_def.html#a042059c8b4168681d6aecf30211dd7b8">TSTR</a>;    
<a name="l00781"></a><a class="code" href="struct_r_t_c___type_def.html#abeb6fb580a8fd128182aa9ba2738ac2c">00781</a>   __IO uint32_t <a class="code" href="struct_r_t_c___type_def.html#abeb6fb580a8fd128182aa9ba2738ac2c">TSDR</a>;    
<a name="l00782"></a><a class="code" href="struct_r_t_c___type_def.html#a1d6c2bc4c067d6a64ef30d16a5925796">00782</a>   __IO uint32_t <a class="code" href="struct_r_t_c___type_def.html#a1d6c2bc4c067d6a64ef30d16a5925796">TSSSR</a>;   
<a name="l00783"></a><a class="code" href="struct_r_t_c___type_def.html#a2ce7c3842792c506635bb87a21588b58">00783</a>   __IO uint32_t <a class="code" href="struct_r_t_c___type_def.html#a2ce7c3842792c506635bb87a21588b58">CALR</a>;    
<a name="l00784"></a><a class="code" href="struct_r_t_c___type_def.html#a14d03244a7fda1d94b51ae9ed144ca12">00784</a>   __IO uint32_t <a class="code" href="struct_r_t_c___type_def.html#a14d03244a7fda1d94b51ae9ed144ca12">TAFCR</a>;   
<a name="l00785"></a><a class="code" href="struct_r_t_c___type_def.html#a61282fa74cede526af85fd9d20513646">00785</a>   __IO uint32_t <a class="code" href="struct_r_t_c___type_def.html#a61282fa74cede526af85fd9d20513646">ALRMASSR</a>;
<a name="l00786"></a><a class="code" href="struct_r_t_c___type_def.html#a4ef7499da5d5beb1cfc81f7be057a7b2">00786</a>   __IO uint32_t <a class="code" href="struct_r_t_c___type_def.html#a4ef7499da5d5beb1cfc81f7be057a7b2">ALRMBSSR</a>;
<a name="l00787"></a><a class="code" href="struct_r_t_c___type_def.html#a6be3d40baea405ecaf6b38462357dac0">00787</a>   uint32_t <a class="code" href="struct_r_t_c___type_def.html#a6be3d40baea405ecaf6b38462357dac0">RESERVED7</a>;    
<a name="l00788"></a><a class="code" href="struct_r_t_c___type_def.html#a4808ec597e5a5fefd8a83a9127dd1aec">00788</a>   __IO uint32_t <a class="code" href="struct_r_t_c___type_def.html#a4808ec597e5a5fefd8a83a9127dd1aec">BKP0R</a>;   
<a name="l00789"></a><a class="code" href="struct_r_t_c___type_def.html#af85290529fb82acef7c9fcea3718346c">00789</a>   __IO uint32_t <a class="code" href="struct_r_t_c___type_def.html#af85290529fb82acef7c9fcea3718346c">BKP1R</a>;   
<a name="l00790"></a><a class="code" href="struct_r_t_c___type_def.html#aaa251a80daa57ad0bd7db75cb3b9cdec">00790</a>   __IO uint32_t <a class="code" href="struct_r_t_c___type_def.html#aaa251a80daa57ad0bd7db75cb3b9cdec">BKP2R</a>;   
<a name="l00791"></a><a class="code" href="struct_r_t_c___type_def.html#a0b1eeda834c3cfd4d2c67f242f7b2a1c">00791</a>   __IO uint32_t <a class="code" href="struct_r_t_c___type_def.html#a0b1eeda834c3cfd4d2c67f242f7b2a1c">BKP3R</a>;   
<a name="l00792"></a><a class="code" href="struct_r_t_c___type_def.html#ab13e106cc2eca92d1f4022df3bfdbcd7">00792</a>   __IO uint32_t <a class="code" href="struct_r_t_c___type_def.html#ab13e106cc2eca92d1f4022df3bfdbcd7">BKP4R</a>;   
<a name="l00793"></a><a class="code" href="struct_r_t_c___type_def.html#ab6bed862c0d0476ff4f89f7b9bf3e130">00793</a>   __IO uint32_t <a class="code" href="struct_r_t_c___type_def.html#ab6bed862c0d0476ff4f89f7b9bf3e130">BKP5R</a>;   
<a name="l00794"></a><a class="code" href="struct_r_t_c___type_def.html#a1d854d2d7f0452f4c90035952b92d2ba">00794</a>   __IO uint32_t <a class="code" href="struct_r_t_c___type_def.html#a1d854d2d7f0452f4c90035952b92d2ba">BKP6R</a>;   
<a name="l00795"></a><a class="code" href="struct_r_t_c___type_def.html#a2ca54ce1a8d2fa9d1ba6d5987ed5e2cf">00795</a>   __IO uint32_t <a class="code" href="struct_r_t_c___type_def.html#a2ca54ce1a8d2fa9d1ba6d5987ed5e2cf">BKP7R</a>;   
<a name="l00796"></a><a class="code" href="struct_r_t_c___type_def.html#ac1085f6aae54b353c30871fe90c59851">00796</a>   __IO uint32_t <a class="code" href="struct_r_t_c___type_def.html#ac1085f6aae54b353c30871fe90c59851">BKP8R</a>;   
<a name="l00797"></a><a class="code" href="struct_r_t_c___type_def.html#a6c33564df6eaf97400e0457dde9b14ef">00797</a>   __IO uint32_t <a class="code" href="struct_r_t_c___type_def.html#a6c33564df6eaf97400e0457dde9b14ef">BKP9R</a>;   
<a name="l00798"></a><a class="code" href="struct_r_t_c___type_def.html#aade2881a3e408bfd106b27f78bbbcfc9">00798</a>   __IO uint32_t <a class="code" href="struct_r_t_c___type_def.html#aade2881a3e408bfd106b27f78bbbcfc9">BKP10R</a>;  
<a name="l00799"></a><a class="code" href="struct_r_t_c___type_def.html#ac66d5e2d3459cff89794c47dbc8f7228">00799</a>   __IO uint32_t <a class="code" href="struct_r_t_c___type_def.html#ac66d5e2d3459cff89794c47dbc8f7228">BKP11R</a>;  
<a name="l00800"></a><a class="code" href="struct_r_t_c___type_def.html#a6f7eee5ae8a32c07f9c8fe14281bdaf3">00800</a>   __IO uint32_t <a class="code" href="struct_r_t_c___type_def.html#a6f7eee5ae8a32c07f9c8fe14281bdaf3">BKP12R</a>;  
<a name="l00801"></a><a class="code" href="struct_r_t_c___type_def.html#a6ed4c3a0d4588a75078e9f8e376b4d06">00801</a>   __IO uint32_t <a class="code" href="struct_r_t_c___type_def.html#a6ed4c3a0d4588a75078e9f8e376b4d06">BKP13R</a>;  
<a name="l00802"></a><a class="code" href="struct_r_t_c___type_def.html#ac60f13e6619724747e61cfbff55b9fab">00802</a>   __IO uint32_t <a class="code" href="struct_r_t_c___type_def.html#ac60f13e6619724747e61cfbff55b9fab">BKP14R</a>;  
<a name="l00803"></a><a class="code" href="struct_r_t_c___type_def.html#afafaddc3a983eb71332b7526d82191ad">00803</a>   __IO uint32_t <a class="code" href="struct_r_t_c___type_def.html#afafaddc3a983eb71332b7526d82191ad">BKP15R</a>;  
<a name="l00804"></a><a class="code" href="struct_r_t_c___type_def.html#ad2f2eb2fb4b93e21515b10e920e719b6">00804</a>   __IO uint32_t <a class="code" href="struct_r_t_c___type_def.html#ad2f2eb2fb4b93e21515b10e920e719b6">BKP16R</a>;  
<a name="l00805"></a><a class="code" href="struct_r_t_c___type_def.html#a2842aa523df62f3508316eb3b2e08f4e">00805</a>   __IO uint32_t <a class="code" href="struct_r_t_c___type_def.html#a2842aa523df62f3508316eb3b2e08f4e">BKP17R</a>;  
<a name="l00806"></a><a class="code" href="struct_r_t_c___type_def.html#a640ccb2ccfb6316b88c070362dc29339">00806</a>   __IO uint32_t <a class="code" href="struct_r_t_c___type_def.html#a640ccb2ccfb6316b88c070362dc29339">BKP18R</a>;  
<a name="l00807"></a><a class="code" href="struct_r_t_c___type_def.html#a4ec1dd54d976989b7c9e59fb14d974fb">00807</a>   __IO uint32_t <a class="code" href="struct_r_t_c___type_def.html#a4ec1dd54d976989b7c9e59fb14d974fb">BKP19R</a>;  
<a name="l00808"></a>00808 } <a class="code" href="struct_r_t_c___type_def.html" title="Real-Time Clock.">RTC_TypeDef</a>;
<a name="l00809"></a>00809 
<a name="l00814"></a><a class="code" href="struct_s_d_i_o___type_def.html">00814</a> <span class="keyword">typedef</span> <span class="keyword">struct</span>
<a name="l00815"></a>00815 {
<a name="l00816"></a><a class="code" href="struct_s_d_i_o___type_def.html#a65bff76f3af24c37708a1006d54720c7">00816</a>   __IO uint32_t <a class="code" href="struct_s_d_i_o___type_def.html#a65bff76f3af24c37708a1006d54720c7">POWER</a>;          
<a name="l00817"></a><a class="code" href="struct_s_d_i_o___type_def.html#aa94197378e20fc739d269be49d9c5d40">00817</a>   __IO uint32_t <a class="code" href="struct_s_d_i_o___type_def.html#aa94197378e20fc739d269be49d9c5d40">CLKCR</a>;          
<a name="l00818"></a><a class="code" href="struct_s_d_i_o___type_def.html#a07d4e63efcbde252c667e64a8d818aa9">00818</a>   __IO uint32_t <a class="code" href="struct_s_d_i_o___type_def.html#a07d4e63efcbde252c667e64a8d818aa9">ARG</a>;            
<a name="l00819"></a><a class="code" href="struct_s_d_i_o___type_def.html#adcf812cbe5147d300507d59d4a55935d">00819</a>   __IO uint32_t <a class="code" href="struct_s_d_i_o___type_def.html#adcf812cbe5147d300507d59d4a55935d">CMD</a>;            
<a name="l00820"></a><a class="code" href="struct_s_d_i_o___type_def.html#aad371db807e2db4a2edf05b3f2f4b6cd">00820</a>   __I uint32_t  <a class="code" href="struct_s_d_i_o___type_def.html#aad371db807e2db4a2edf05b3f2f4b6cd">RESPCMD</a>;        
<a name="l00821"></a><a class="code" href="struct_s_d_i_o___type_def.html#a7b0ee0dc541683266dfab6335abca891">00821</a>   __I uint32_t  <a class="code" href="struct_s_d_i_o___type_def.html#a7b0ee0dc541683266dfab6335abca891">RESP1</a>;          
<a name="l00822"></a><a class="code" href="struct_s_d_i_o___type_def.html#a4d99c78dffdb6e81e8f6b7abec263419">00822</a>   __I uint32_t  <a class="code" href="struct_s_d_i_o___type_def.html#a4d99c78dffdb6e81e8f6b7abec263419">RESP2</a>;          
<a name="l00823"></a><a class="code" href="struct_s_d_i_o___type_def.html#a3da04fbdd44f48a1840e5e0a6295f3cf">00823</a>   __I uint32_t  <a class="code" href="struct_s_d_i_o___type_def.html#a3da04fbdd44f48a1840e5e0a6295f3cf">RESP3</a>;          
<a name="l00824"></a><a class="code" href="struct_s_d_i_o___type_def.html#ac760383de212de696f504e744c6fca7e">00824</a>   __I uint32_t  <a class="code" href="struct_s_d_i_o___type_def.html#ac760383de212de696f504e744c6fca7e">RESP4</a>;          
<a name="l00825"></a><a class="code" href="struct_s_d_i_o___type_def.html#a1dd219eaeee8d9def822da843028bd02">00825</a>   __IO uint32_t <a class="code" href="struct_s_d_i_o___type_def.html#a1dd219eaeee8d9def822da843028bd02">DTIMER</a>;         
<a name="l00826"></a><a class="code" href="struct_s_d_i_o___type_def.html#a612edc78d2fa6288392f8ea32c36f7fb">00826</a>   __IO uint32_t <a class="code" href="struct_s_d_i_o___type_def.html#a612edc78d2fa6288392f8ea32c36f7fb">DLEN</a>;           
<a name="l00827"></a><a class="code" href="struct_s_d_i_o___type_def.html#a96a3d1a050982fccc23c2e6dbe0de068">00827</a>   __IO uint32_t <a class="code" href="struct_s_d_i_o___type_def.html#a96a3d1a050982fccc23c2e6dbe0de068">DCTRL</a>;          
<a name="l00828"></a><a class="code" href="struct_s_d_i_o___type_def.html#a4273e2b5aeb7bdf1006909b1a2b59bc8">00828</a>   __I uint32_t  <a class="code" href="struct_s_d_i_o___type_def.html#a4273e2b5aeb7bdf1006909b1a2b59bc8">DCOUNT</a>;         
<a name="l00829"></a><a class="code" href="struct_s_d_i_o___type_def.html#a7520cdf6f3df68c2f147bdd87fb8a96f">00829</a>   __I uint32_t  <a class="code" href="struct_s_d_i_o___type_def.html#a7520cdf6f3df68c2f147bdd87fb8a96f">STA</a>;            
<a name="l00830"></a><a class="code" href="struct_s_d_i_o___type_def.html#a0a8c8230846fd8ff154b9fde8dfa0399">00830</a>   __IO uint32_t <a class="code" href="struct_s_d_i_o___type_def.html#a0a8c8230846fd8ff154b9fde8dfa0399">ICR</a>;            
<a name="l00831"></a><a class="code" href="struct_s_d_i_o___type_def.html#a5c955643593b4aedbe9f84f054d26522">00831</a>   __IO uint32_t <a class="code" href="struct_s_d_i_o___type_def.html#a5c955643593b4aedbe9f84f054d26522">MASK</a>;           
<a name="l00832"></a><a class="code" href="struct_s_d_i_o___type_def.html#a8be676577db129a84a9a2689519a8502">00832</a>   uint32_t      RESERVED0[2];   
<a name="l00833"></a><a class="code" href="struct_s_d_i_o___type_def.html#ab27b78e19f487c845437c29812eecca7">00833</a>   __I uint32_t  <a class="code" href="struct_s_d_i_o___type_def.html#ab27b78e19f487c845437c29812eecca7">FIFOCNT</a>;        
<a name="l00834"></a><a class="code" href="struct_s_d_i_o___type_def.html#a2d531df35272b1f3d787e5726ed5c52c">00834</a>   uint32_t      RESERVED1[13];  
<a name="l00835"></a><a class="code" href="struct_s_d_i_o___type_def.html#a68bef1da5fd164cf0f884b4209670dc8">00835</a>   __IO uint32_t <a class="code" href="struct_s_d_i_o___type_def.html#a68bef1da5fd164cf0f884b4209670dc8">FIFO</a>;           
<a name="l00836"></a>00836 } <a class="code" href="struct_s_d_i_o___type_def.html" title="SD host Interface.">SDIO_TypeDef</a>;
<a name="l00837"></a>00837 
<a name="l00842"></a><a class="code" href="struct_s_p_i___type_def.html">00842</a> <span class="keyword">typedef</span> <span class="keyword">struct</span>
<a name="l00843"></a>00843 {
<a name="l00844"></a><a class="code" href="struct_s_p_i___type_def.html#a61400ce239355b62aa25c95fcc18a5e1">00844</a>   __IO uint16_t <a class="code" href="struct_s_p_i___type_def.html#a61400ce239355b62aa25c95fcc18a5e1">CR1</a>;        
<a name="l00845"></a><a class="code" href="struct_s_p_i___type_def.html#a149feba01f9c4a49570c6d88619f504f">00845</a>   uint16_t      <a class="code" href="struct_s_p_i___type_def.html#a149feba01f9c4a49570c6d88619f504f">RESERVED0</a>;  
<a name="l00846"></a><a class="code" href="struct_s_p_i___type_def.html#a2a3e81bd118d1bc52d24a0b0772e6a0c">00846</a>   __IO uint16_t <a class="code" href="struct_s_p_i___type_def.html#a2a3e81bd118d1bc52d24a0b0772e6a0c">CR2</a>;        
<a name="l00847"></a><a class="code" href="struct_s_p_i___type_def.html#a8249a3955aace28d92109b391311eb30">00847</a>   uint16_t      <a class="code" href="struct_s_p_i___type_def.html#a8249a3955aace28d92109b391311eb30">RESERVED1</a>;  
<a name="l00848"></a><a class="code" href="struct_s_p_i___type_def.html#a44962ea5442d203bf4954035d1bfeb9d">00848</a>   __IO uint16_t <a class="code" href="struct_s_p_i___type_def.html#a44962ea5442d203bf4954035d1bfeb9d">SR</a>;         
<a name="l00849"></a><a class="code" href="struct_s_p_i___type_def.html#a5573848497a716a9947fd87487709feb">00849</a>   uint16_t      <a class="code" href="struct_s_p_i___type_def.html#a5573848497a716a9947fd87487709feb">RESERVED2</a>;  
<a name="l00850"></a><a class="code" href="struct_s_p_i___type_def.html#a0a1acc0425516ff7969709d118b96a3b">00850</a>   __IO uint16_t <a class="code" href="struct_s_p_i___type_def.html#a0a1acc0425516ff7969709d118b96a3b">DR</a>;         
<a name="l00851"></a><a class="code" href="struct_s_p_i___type_def.html#a6c3b31022e6f59b800e9f5cc2a89d54c">00851</a>   uint16_t      <a class="code" href="struct_s_p_i___type_def.html#a6c3b31022e6f59b800e9f5cc2a89d54c">RESERVED3</a>;  
<a name="l00852"></a><a class="code" href="struct_s_p_i___type_def.html#a942ae09a7662bad70ef336f2bed43a19">00852</a>   __IO uint16_t <a class="code" href="struct_s_p_i___type_def.html#a942ae09a7662bad70ef336f2bed43a19">CRCPR</a>;      
<a name="l00853"></a><a class="code" href="struct_s_p_i___type_def.html#aa0223808025f5bf9c056185038c9d545">00853</a>   uint16_t      <a class="code" href="struct_s_p_i___type_def.html#aa0223808025f5bf9c056185038c9d545">RESERVED4</a>;  
<a name="l00854"></a><a class="code" href="struct_s_p_i___type_def.html#a7ad53aa3735ccdd785e3eec02faf5eb9">00854</a>   __IO uint16_t <a class="code" href="struct_s_p_i___type_def.html#a7ad53aa3735ccdd785e3eec02faf5eb9">RXCRCR</a>;     
<a name="l00855"></a><a class="code" href="struct_s_p_i___type_def.html#abd36010ac282682d1f3c641b183b1b6f">00855</a>   uint16_t      <a class="code" href="struct_s_p_i___type_def.html#abd36010ac282682d1f3c641b183b1b6f">RESERVED5</a>;  
<a name="l00856"></a><a class="code" href="struct_s_p_i___type_def.html#a0238d40f977d03709c97033b8379f98f">00856</a>   __IO uint16_t <a class="code" href="struct_s_p_i___type_def.html#a0238d40f977d03709c97033b8379f98f">TXCRCR</a>;     
<a name="l00857"></a><a class="code" href="struct_s_p_i___type_def.html#aab502dde158ab7da8e7823d1f8a06edb">00857</a>   uint16_t      <a class="code" href="struct_s_p_i___type_def.html#aab502dde158ab7da8e7823d1f8a06edb">RESERVED6</a>;  
<a name="l00858"></a><a class="code" href="struct_s_p_i___type_def.html#acb40abca5ca4cd2b2855adf2186effe8">00858</a>   __IO uint16_t <a class="code" href="struct_s_p_i___type_def.html#acb40abca5ca4cd2b2855adf2186effe8">I2SCFGR</a>;    
<a name="l00859"></a><a class="code" href="struct_s_p_i___type_def.html#ab1820c97e368d349f5f4121f015d9fab">00859</a>   uint16_t      <a class="code" href="struct_s_p_i___type_def.html#ab1820c97e368d349f5f4121f015d9fab">RESERVED7</a>;  
<a name="l00860"></a><a class="code" href="struct_s_p_i___type_def.html#a02ce1ece243cc4ce1d66ebeca247fee1">00860</a>   __IO uint16_t <a class="code" href="struct_s_p_i___type_def.html#a02ce1ece243cc4ce1d66ebeca247fee1">I2SPR</a>;      
<a name="l00861"></a><a class="code" href="struct_s_p_i___type_def.html#afc22764fbf9ee7ce28174d65d0260f18">00861</a>   uint16_t      <a class="code" href="struct_s_p_i___type_def.html#afc22764fbf9ee7ce28174d65d0260f18">RESERVED8</a>;  
<a name="l00862"></a>00862 } <a class="code" href="struct_s_p_i___type_def.html" title="Serial Peripheral Interface.">SPI_TypeDef</a>;
<a name="l00863"></a>00863 
<a name="l00868"></a><a class="code" href="struct_t_i_m___type_def.html">00868</a> <span class="keyword">typedef</span> <span class="keyword">struct</span>
<a name="l00869"></a>00869 {
<a name="l00870"></a><a class="code" href="struct_t_i_m___type_def.html#a61400ce239355b62aa25c95fcc18a5e1">00870</a>   __IO uint16_t <a class="code" href="struct_t_i_m___type_def.html#a61400ce239355b62aa25c95fcc18a5e1">CR1</a>;         
<a name="l00871"></a><a class="code" href="struct_t_i_m___type_def.html#a149feba01f9c4a49570c6d88619f504f">00871</a>   uint16_t      <a class="code" href="struct_t_i_m___type_def.html#a149feba01f9c4a49570c6d88619f504f">RESERVED0</a>;   
<a name="l00872"></a><a class="code" href="struct_t_i_m___type_def.html#a2a3e81bd118d1bc52d24a0b0772e6a0c">00872</a>   __IO uint16_t <a class="code" href="struct_t_i_m___type_def.html#a2a3e81bd118d1bc52d24a0b0772e6a0c">CR2</a>;         
<a name="l00873"></a><a class="code" href="struct_t_i_m___type_def.html#a8249a3955aace28d92109b391311eb30">00873</a>   uint16_t      <a class="code" href="struct_t_i_m___type_def.html#a8249a3955aace28d92109b391311eb30">RESERVED1</a>;   
<a name="l00874"></a><a class="code" href="struct_t_i_m___type_def.html#a02758713abfe580460dd5bcd8762702a">00874</a>   __IO uint16_t <a class="code" href="struct_t_i_m___type_def.html#a02758713abfe580460dd5bcd8762702a">SMCR</a>;        
<a name="l00875"></a><a class="code" href="struct_t_i_m___type_def.html#a5573848497a716a9947fd87487709feb">00875</a>   uint16_t      <a class="code" href="struct_t_i_m___type_def.html#a5573848497a716a9947fd87487709feb">RESERVED2</a>;   
<a name="l00876"></a><a class="code" href="struct_t_i_m___type_def.html#a1481b34cc41018c17e4ab592a1c8cb55">00876</a>   __IO uint16_t <a class="code" href="struct_t_i_m___type_def.html#a1481b34cc41018c17e4ab592a1c8cb55">DIER</a>;        
<a name="l00877"></a><a class="code" href="struct_t_i_m___type_def.html#a6c3b31022e6f59b800e9f5cc2a89d54c">00877</a>   uint16_t      <a class="code" href="struct_t_i_m___type_def.html#a6c3b31022e6f59b800e9f5cc2a89d54c">RESERVED3</a>;   
<a name="l00878"></a><a class="code" href="struct_t_i_m___type_def.html#a44962ea5442d203bf4954035d1bfeb9d">00878</a>   __IO uint16_t <a class="code" href="struct_t_i_m___type_def.html#a44962ea5442d203bf4954035d1bfeb9d">SR</a>;          
<a name="l00879"></a><a class="code" href="struct_t_i_m___type_def.html#aa0223808025f5bf9c056185038c9d545">00879</a>   uint16_t      <a class="code" href="struct_t_i_m___type_def.html#aa0223808025f5bf9c056185038c9d545">RESERVED4</a>;   
<a name="l00880"></a><a class="code" href="struct_t_i_m___type_def.html#a980df1a5752e36604de4d71ce14fbfa3">00880</a>   __IO uint16_t <a class="code" href="struct_t_i_m___type_def.html#a980df1a5752e36604de4d71ce14fbfa3">EGR</a>;         
<a name="l00881"></a><a class="code" href="struct_t_i_m___type_def.html#abd36010ac282682d1f3c641b183b1b6f">00881</a>   uint16_t      <a class="code" href="struct_t_i_m___type_def.html#abd36010ac282682d1f3c641b183b1b6f">RESERVED5</a>;   
<a name="l00882"></a><a class="code" href="struct_t_i_m___type_def.html#a90d89aec51d8012b8a565ef48333b24b">00882</a>   __IO uint16_t <a class="code" href="struct_t_i_m___type_def.html#a90d89aec51d8012b8a565ef48333b24b">CCMR1</a>;       
<a name="l00883"></a><a class="code" href="struct_t_i_m___type_def.html#aab502dde158ab7da8e7823d1f8a06edb">00883</a>   uint16_t      <a class="code" href="struct_t_i_m___type_def.html#aab502dde158ab7da8e7823d1f8a06edb">RESERVED6</a>;   
<a name="l00884"></a><a class="code" href="struct_t_i_m___type_def.html#a977b3cf310388b5ad02440d64d03810a">00884</a>   __IO uint16_t <a class="code" href="struct_t_i_m___type_def.html#a977b3cf310388b5ad02440d64d03810a">CCMR2</a>;       
<a name="l00885"></a><a class="code" href="struct_t_i_m___type_def.html#ab1820c97e368d349f5f4121f015d9fab">00885</a>   uint16_t      <a class="code" href="struct_t_i_m___type_def.html#ab1820c97e368d349f5f4121f015d9fab">RESERVED7</a>;   
<a name="l00886"></a><a class="code" href="struct_t_i_m___type_def.html#ab1da3e84848ed66e0577c87c199bfb6d">00886</a>   __IO uint16_t <a class="code" href="struct_t_i_m___type_def.html#ab1da3e84848ed66e0577c87c199bfb6d">CCER</a>;        
<a name="l00887"></a><a class="code" href="struct_t_i_m___type_def.html#afc22764fbf9ee7ce28174d65d0260f18">00887</a>   uint16_t      <a class="code" href="struct_t_i_m___type_def.html#afc22764fbf9ee7ce28174d65d0260f18">RESERVED8</a>;   
<a name="l00888"></a><a class="code" href="struct_t_i_m___type_def.html#a6095a27d764d06750fc0d642e08f8b2a">00888</a>   __IO uint32_t <a class="code" href="struct_t_i_m___type_def.html#a6095a27d764d06750fc0d642e08f8b2a">CNT</a>;         
<a name="l00889"></a><a class="code" href="struct_t_i_m___type_def.html#aba5df4ecbb3ecb97b966b188c3681600">00889</a>   __IO uint16_t <a class="code" href="struct_t_i_m___type_def.html#aba5df4ecbb3ecb97b966b188c3681600">PSC</a>;         
<a name="l00890"></a><a class="code" href="struct_t_i_m___type_def.html#ad8b1fadb520f7a200ee0046e110edc79">00890</a>   uint16_t      <a class="code" href="struct_t_i_m___type_def.html#ad8b1fadb520f7a200ee0046e110edc79">RESERVED9</a>;   
<a name="l00891"></a><a class="code" href="struct_t_i_m___type_def.html#af17f19bb4aeea3cc14fa73dfa7772cb8">00891</a>   __IO uint32_t <a class="code" href="struct_t_i_m___type_def.html#af17f19bb4aeea3cc14fa73dfa7772cb8">ARR</a>;         
<a name="l00892"></a><a class="code" href="struct_t_i_m___type_def.html#aa0663aab6ed640b7594c8c6d32f6c1cd">00892</a>   __IO uint16_t <a class="code" href="struct_t_i_m___type_def.html#aa0663aab6ed640b7594c8c6d32f6c1cd">RCR</a>;         
<a name="l00893"></a><a class="code" href="struct_t_i_m___type_def.html#ad68efe7a323ac2fcb823a26c0c51445b">00893</a>   uint16_t      <a class="code" href="struct_t_i_m___type_def.html#ad68efe7a323ac2fcb823a26c0c51445b">RESERVED10</a>;  
<a name="l00894"></a><a class="code" href="struct_t_i_m___type_def.html#adab1e24ef769bbcb3e3769feae192ffb">00894</a>   __IO uint32_t <a class="code" href="struct_t_i_m___type_def.html#adab1e24ef769bbcb3e3769feae192ffb">CCR1</a>;        
<a name="l00895"></a><a class="code" href="struct_t_i_m___type_def.html#ab90aa584f07eeeac364a67f5e05faa93">00895</a>   __IO uint32_t <a class="code" href="struct_t_i_m___type_def.html#ab90aa584f07eeeac364a67f5e05faa93">CCR2</a>;        
<a name="l00896"></a><a class="code" href="struct_t_i_m___type_def.html#a27a478cc47a3dff478555ccb985b06a2">00896</a>   __IO uint32_t <a class="code" href="struct_t_i_m___type_def.html#a27a478cc47a3dff478555ccb985b06a2">CCR3</a>;        
<a name="l00897"></a><a class="code" href="struct_t_i_m___type_def.html#a85fdb75569bd7ea26fa48544786535be">00897</a>   __IO uint32_t <a class="code" href="struct_t_i_m___type_def.html#a85fdb75569bd7ea26fa48544786535be">CCR4</a>;        
<a name="l00898"></a><a class="code" href="struct_t_i_m___type_def.html#a112c0403ac38905a70cf5aaa9c8cc38a">00898</a>   __IO uint16_t <a class="code" href="struct_t_i_m___type_def.html#a112c0403ac38905a70cf5aaa9c8cc38a">BDTR</a>;        
<a name="l00899"></a><a class="code" href="struct_t_i_m___type_def.html#a11e504ee49142f46dcc67740ae9235e5">00899</a>   uint16_t      <a class="code" href="struct_t_i_m___type_def.html#a11e504ee49142f46dcc67740ae9235e5">RESERVED11</a>;  
<a name="l00900"></a><a class="code" href="struct_t_i_m___type_def.html#a0afd527a4ec64faf878f9957096102bf">00900</a>   __IO uint16_t <a class="code" href="struct_t_i_m___type_def.html#a0afd527a4ec64faf878f9957096102bf">DCR</a>;         
<a name="l00901"></a><a class="code" href="struct_t_i_m___type_def.html#a2f133f27cf624e76a2ac1092ab5789f7">00901</a>   uint16_t      <a class="code" href="struct_t_i_m___type_def.html#a2f133f27cf624e76a2ac1092ab5789f7">RESERVED12</a>;  
<a name="l00902"></a><a class="code" href="struct_t_i_m___type_def.html#a30c2d8aa9c76dfba0b9a378b64700bda">00902</a>   __IO uint16_t <a class="code" href="struct_t_i_m___type_def.html#a30c2d8aa9c76dfba0b9a378b64700bda">DMAR</a>;        
<a name="l00903"></a><a class="code" href="struct_t_i_m___type_def.html#a85b970173fe49d3959c0c7f7528dacf0">00903</a>   uint16_t      <a class="code" href="struct_t_i_m___type_def.html#a85b970173fe49d3959c0c7f7528dacf0">RESERVED13</a>;  
<a name="l00904"></a><a class="code" href="struct_t_i_m___type_def.html#a47766f433b160258ec05dbb6498fd271">00904</a>   __IO uint16_t <a class="code" href="struct_t_i_m___type_def.html#a47766f433b160258ec05dbb6498fd271">OR</a>;          
<a name="l00905"></a><a class="code" href="struct_t_i_m___type_def.html#a1841fa0366924d522d6ac880fb14d766">00905</a>   uint16_t      <a class="code" href="struct_t_i_m___type_def.html#a1841fa0366924d522d6ac880fb14d766">RESERVED14</a>;  
<a name="l00906"></a>00906 } <a class="code" href="struct_t_i_m___type_def.html" title="TIM.">TIM_TypeDef</a>;
<a name="l00907"></a>00907 
<a name="l00912"></a><a class="code" href="struct_u_s_a_r_t___type_def.html">00912</a> <span class="keyword">typedef</span> <span class="keyword">struct</span>
<a name="l00913"></a>00913 {
<a name="l00914"></a><a class="code" href="struct_u_s_a_r_t___type_def.html#a44962ea5442d203bf4954035d1bfeb9d">00914</a>   __IO uint16_t <a class="code" href="struct_u_s_a_r_t___type_def.html#a44962ea5442d203bf4954035d1bfeb9d">SR</a>;         
<a name="l00915"></a><a class="code" href="struct_u_s_a_r_t___type_def.html#a149feba01f9c4a49570c6d88619f504f">00915</a>   uint16_t      <a class="code" href="struct_u_s_a_r_t___type_def.html#a149feba01f9c4a49570c6d88619f504f">RESERVED0</a>;  
<a name="l00916"></a><a class="code" href="struct_u_s_a_r_t___type_def.html#a0a1acc0425516ff7969709d118b96a3b">00916</a>   __IO uint16_t <a class="code" href="struct_u_s_a_r_t___type_def.html#a0a1acc0425516ff7969709d118b96a3b">DR</a>;         
<a name="l00917"></a><a class="code" href="struct_u_s_a_r_t___type_def.html#a8249a3955aace28d92109b391311eb30">00917</a>   uint16_t      <a class="code" href="struct_u_s_a_r_t___type_def.html#a8249a3955aace28d92109b391311eb30">RESERVED1</a>;  
<a name="l00918"></a><a class="code" href="struct_u_s_a_r_t___type_def.html#af0ba3d82d524fddbe0fb3309788e2954">00918</a>   __IO uint16_t <a class="code" href="struct_u_s_a_r_t___type_def.html#af0ba3d82d524fddbe0fb3309788e2954">BRR</a>;        
<a name="l00919"></a><a class="code" href="struct_u_s_a_r_t___type_def.html#a5573848497a716a9947fd87487709feb">00919</a>   uint16_t      <a class="code" href="struct_u_s_a_r_t___type_def.html#a5573848497a716a9947fd87487709feb">RESERVED2</a>;  
<a name="l00920"></a><a class="code" href="struct_u_s_a_r_t___type_def.html#a61400ce239355b62aa25c95fcc18a5e1">00920</a>   __IO uint16_t <a class="code" href="struct_u_s_a_r_t___type_def.html#a61400ce239355b62aa25c95fcc18a5e1">CR1</a>;        
<a name="l00921"></a><a class="code" href="struct_u_s_a_r_t___type_def.html#a6c3b31022e6f59b800e9f5cc2a89d54c">00921</a>   uint16_t      <a class="code" href="struct_u_s_a_r_t___type_def.html#a6c3b31022e6f59b800e9f5cc2a89d54c">RESERVED3</a>;  
<a name="l00922"></a><a class="code" href="struct_u_s_a_r_t___type_def.html#a2a3e81bd118d1bc52d24a0b0772e6a0c">00922</a>   __IO uint16_t <a class="code" href="struct_u_s_a_r_t___type_def.html#a2a3e81bd118d1bc52d24a0b0772e6a0c">CR2</a>;        
<a name="l00923"></a><a class="code" href="struct_u_s_a_r_t___type_def.html#aa0223808025f5bf9c056185038c9d545">00923</a>   uint16_t      <a class="code" href="struct_u_s_a_r_t___type_def.html#aa0223808025f5bf9c056185038c9d545">RESERVED4</a>;  
<a name="l00924"></a><a class="code" href="struct_u_s_a_r_t___type_def.html#a9651ce2df8eec57b9cab2f27f6dbf3e1">00924</a>   __IO uint16_t <a class="code" href="struct_u_s_a_r_t___type_def.html#a9651ce2df8eec57b9cab2f27f6dbf3e1">CR3</a>;        
<a name="l00925"></a><a class="code" href="struct_u_s_a_r_t___type_def.html#abd36010ac282682d1f3c641b183b1b6f">00925</a>   uint16_t      <a class="code" href="struct_u_s_a_r_t___type_def.html#abd36010ac282682d1f3c641b183b1b6f">RESERVED5</a>;  
<a name="l00926"></a><a class="code" href="struct_u_s_a_r_t___type_def.html#a26f8b74978e03c8a4c99c9395a6a524d">00926</a>   __IO uint16_t <a class="code" href="struct_u_s_a_r_t___type_def.html#a26f8b74978e03c8a4c99c9395a6a524d">GTPR</a>;       
<a name="l00927"></a><a class="code" href="struct_u_s_a_r_t___type_def.html#aab502dde158ab7da8e7823d1f8a06edb">00927</a>   uint16_t      <a class="code" href="struct_u_s_a_r_t___type_def.html#aab502dde158ab7da8e7823d1f8a06edb">RESERVED6</a>;  
<a name="l00928"></a>00928 } <a class="code" href="struct_u_s_a_r_t___type_def.html" title="Universal Synchronous Asynchronous Receiver Transmitter.">USART_TypeDef</a>;
<a name="l00929"></a>00929 
<a name="l00934"></a><a class="code" href="struct_w_w_d_g___type_def.html">00934</a> <span class="keyword">typedef</span> <span class="keyword">struct</span>
<a name="l00935"></a>00935 {
<a name="l00936"></a><a class="code" href="struct_w_w_d_g___type_def.html#ab40c89c59391aaa9d9a8ec011dd0907a">00936</a>   __IO uint32_t <a class="code" href="struct_w_w_d_g___type_def.html#ab40c89c59391aaa9d9a8ec011dd0907a">CR</a>;   
<a name="l00937"></a><a class="code" href="struct_w_w_d_g___type_def.html#ac011ddcfe531f8e16787ea851c1f3667">00937</a>   __IO uint32_t <a class="code" href="struct_w_w_d_g___type_def.html#ac011ddcfe531f8e16787ea851c1f3667">CFR</a>;  
<a name="l00938"></a><a class="code" href="struct_w_w_d_g___type_def.html#af6aca2bbd40c0fb6df7c3aebe224a360">00938</a>   __IO uint32_t <a class="code" href="struct_w_w_d_g___type_def.html#af6aca2bbd40c0fb6df7c3aebe224a360">SR</a>;   
<a name="l00939"></a>00939 } <a class="code" href="struct_w_w_d_g___type_def.html" title="Window WATCHDOG.">WWDG_TypeDef</a>;
<a name="l00940"></a>00940 
<a name="l00945"></a><a class="code" href="struct_c_r_y_p___type_def.html">00945</a> <span class="keyword">typedef</span> <span class="keyword">struct</span>
<a name="l00946"></a>00946 {
<a name="l00947"></a><a class="code" href="struct_c_r_y_p___type_def.html#ab40c89c59391aaa9d9a8ec011dd0907a">00947</a>   __IO uint32_t <a class="code" href="struct_c_r_y_p___type_def.html#ab40c89c59391aaa9d9a8ec011dd0907a">CR</a>;     
<a name="l00948"></a><a class="code" href="struct_c_r_y_p___type_def.html#af6aca2bbd40c0fb6df7c3aebe224a360">00948</a>   __IO uint32_t <a class="code" href="struct_c_r_y_p___type_def.html#af6aca2bbd40c0fb6df7c3aebe224a360">SR</a>;     
<a name="l00949"></a><a class="code" href="struct_c_r_y_p___type_def.html#a3df0d8dfcd1ec958659ffe21eb64fa94">00949</a>   __IO uint32_t <a class="code" href="struct_c_r_y_p___type_def.html#a3df0d8dfcd1ec958659ffe21eb64fa94">DR</a>;     
<a name="l00950"></a><a class="code" href="struct_c_r_y_p___type_def.html#ab8ba768d1dac54a845084bd07f4ef2b9">00950</a>   __IO uint32_t <a class="code" href="struct_c_r_y_p___type_def.html#ab8ba768d1dac54a845084bd07f4ef2b9">DOUT</a>;   
<a name="l00951"></a><a class="code" href="struct_c_r_y_p___type_def.html#a082219a924d748e9c6092582aec06226">00951</a>   __IO uint32_t <a class="code" href="struct_c_r_y_p___type_def.html#a082219a924d748e9c6092582aec06226">DMACR</a>;  
<a name="l00952"></a><a class="code" href="struct_c_r_y_p___type_def.html#adcdd7c23a99f81c21dae2e9f989632e1">00952</a>   __IO uint32_t <a class="code" href="struct_c_r_y_p___type_def.html#adcdd7c23a99f81c21dae2e9f989632e1">IMSCR</a>;  
<a name="l00953"></a><a class="code" href="struct_c_r_y_p___type_def.html#aa196fddf0ba7d6e3ce29bdb04eb38b94">00953</a>   __IO uint32_t <a class="code" href="struct_c_r_y_p___type_def.html#aa196fddf0ba7d6e3ce29bdb04eb38b94">RISR</a>;   
<a name="l00954"></a><a class="code" href="struct_c_r_y_p___type_def.html#a524e134cec519206cb41d0545e382978">00954</a>   __IO uint32_t <a class="code" href="struct_c_r_y_p___type_def.html#a524e134cec519206cb41d0545e382978">MISR</a>;   
<a name="l00955"></a><a class="code" href="struct_c_r_y_p___type_def.html#a3ca109e86323625e5f56f92f999c3b05">00955</a>   __IO uint32_t <a class="code" href="struct_c_r_y_p___type_def.html#a3ca109e86323625e5f56f92f999c3b05">K0LR</a>;   
<a name="l00956"></a><a class="code" href="struct_c_r_y_p___type_def.html#ae6d97d339f0091d4a105001ea59086ae">00956</a>   __IO uint32_t <a class="code" href="struct_c_r_y_p___type_def.html#ae6d97d339f0091d4a105001ea59086ae">K0RR</a>;   
<a name="l00957"></a><a class="code" href="struct_c_r_y_p___type_def.html#a948ff2e2e97978287411fe725dd70a7f">00957</a>   __IO uint32_t <a class="code" href="struct_c_r_y_p___type_def.html#a948ff2e2e97978287411fe725dd70a7f">K1LR</a>;   
<a name="l00958"></a><a class="code" href="struct_c_r_y_p___type_def.html#a7554383cff84540eb260a3fdf55cb934">00958</a>   __IO uint32_t <a class="code" href="struct_c_r_y_p___type_def.html#a7554383cff84540eb260a3fdf55cb934">K1RR</a>;   
<a name="l00959"></a><a class="code" href="struct_c_r_y_p___type_def.html#a32210fb9ecbb0b4bd127e688f3f79802">00959</a>   __IO uint32_t <a class="code" href="struct_c_r_y_p___type_def.html#a32210fb9ecbb0b4bd127e688f3f79802">K2LR</a>;   
<a name="l00960"></a><a class="code" href="struct_c_r_y_p___type_def.html#a41a0448734e8ccbdd6fba98284815c6f">00960</a>   __IO uint32_t <a class="code" href="struct_c_r_y_p___type_def.html#a41a0448734e8ccbdd6fba98284815c6f">K2RR</a>;   
<a name="l00961"></a><a class="code" href="struct_c_r_y_p___type_def.html#a516c328fcb53ec754384e584caf890f5">00961</a>   __IO uint32_t <a class="code" href="struct_c_r_y_p___type_def.html#a516c328fcb53ec754384e584caf890f5">K3LR</a>;   
<a name="l00962"></a><a class="code" href="struct_c_r_y_p___type_def.html#a8fe249258f1733ec155c3893375c7a21">00962</a>   __IO uint32_t <a class="code" href="struct_c_r_y_p___type_def.html#a8fe249258f1733ec155c3893375c7a21">K3RR</a>;   
<a name="l00963"></a><a class="code" href="struct_c_r_y_p___type_def.html#ab1efba4cdf22c525fce804375961d567">00963</a>   __IO uint32_t <a class="code" href="struct_c_r_y_p___type_def.html#ab1efba4cdf22c525fce804375961d567">IV0LR</a>;  
<a name="l00964"></a><a class="code" href="struct_c_r_y_p___type_def.html#aeb1990f7c28e815a4962db3a861937bb">00964</a>   __IO uint32_t <a class="code" href="struct_c_r_y_p___type_def.html#aeb1990f7c28e815a4962db3a861937bb">IV0RR</a>;  
<a name="l00965"></a><a class="code" href="struct_c_r_y_p___type_def.html#aad2f43335b25a0065f3d327364610cbd">00965</a>   __IO uint32_t <a class="code" href="struct_c_r_y_p___type_def.html#aad2f43335b25a0065f3d327364610cbd">IV1LR</a>;  
<a name="l00966"></a><a class="code" href="struct_c_r_y_p___type_def.html#a38a9f05c03174023fc6ac951c04eaeff">00966</a>   __IO uint32_t <a class="code" href="struct_c_r_y_p___type_def.html#a38a9f05c03174023fc6ac951c04eaeff">IV1RR</a>;  
<a name="l00967"></a>00967 } <a class="code" href="struct_c_r_y_p___type_def.html" title="Crypto Processor.">CRYP_TypeDef</a>;
<a name="l00968"></a>00968 
<a name="l00973"></a><a class="code" href="struct_h_a_s_h___type_def.html">00973</a> <span class="keyword">typedef</span> <span class="keyword">struct </span>
<a name="l00974"></a>00974 {
<a name="l00975"></a><a class="code" href="struct_h_a_s_h___type_def.html#ab40c89c59391aaa9d9a8ec011dd0907a">00975</a>   __IO uint32_t <a class="code" href="struct_h_a_s_h___type_def.html#ab40c89c59391aaa9d9a8ec011dd0907a">CR</a>;        
<a name="l00976"></a><a class="code" href="struct_h_a_s_h___type_def.html#a445dd5529e7dc6a4fa2fec4f78da2692">00976</a>   __IO uint32_t <a class="code" href="struct_h_a_s_h___type_def.html#a445dd5529e7dc6a4fa2fec4f78da2692">DIN</a>;       
<a name="l00977"></a><a class="code" href="struct_h_a_s_h___type_def.html#a7060ac1ed928ee931d7664650f2dcf75">00977</a>   __IO uint32_t <a class="code" href="struct_h_a_s_h___type_def.html#a7060ac1ed928ee931d7664650f2dcf75">STR</a>;       
<a name="l00978"></a><a class="code" href="struct_h_a_s_h___type_def.html#a02cdb629fbb2bfa63db818ac846847a1">00978</a>   __IO uint32_t HR[5];     
<a name="l00979"></a><a class="code" href="struct_h_a_s_h___type_def.html#ae845b86e973b4bf8a33c447c261633f6">00979</a>   __IO uint32_t <a class="code" href="struct_h_a_s_h___type_def.html#ae845b86e973b4bf8a33c447c261633f6">IMR</a>;       
<a name="l00980"></a><a class="code" href="struct_h_a_s_h___type_def.html#af6aca2bbd40c0fb6df7c3aebe224a360">00980</a>   __IO uint32_t <a class="code" href="struct_h_a_s_h___type_def.html#af6aca2bbd40c0fb6df7c3aebe224a360">SR</a>;        
<a name="l00981"></a><a class="code" href="struct_h_a_s_h___type_def.html#a31675cbea6dc1b5f7de162884a4bb6eb">00981</a>   uint32_t  RESERVED[52];  
<a name="l00982"></a><a class="code" href="struct_h_a_s_h___type_def.html#a5a72a62805d5497f2b44448edd18f20f">00982</a>   __IO uint32_t CSR[51];   
<a name="l00983"></a>00983 } <a class="code" href="struct_h_a_s_h___type_def.html" title="HASH.">HASH_TypeDef</a>;
<a name="l00984"></a>00984 
<a name="l00989"></a><a class="code" href="struct_r_n_g___type_def.html">00989</a> <span class="keyword">typedef</span> <span class="keyword">struct </span>
<a name="l00990"></a>00990 {
<a name="l00991"></a><a class="code" href="struct_r_n_g___type_def.html#ab40c89c59391aaa9d9a8ec011dd0907a">00991</a>   __IO uint32_t <a class="code" href="struct_r_n_g___type_def.html#ab40c89c59391aaa9d9a8ec011dd0907a">CR</a>;  
<a name="l00992"></a><a class="code" href="struct_r_n_g___type_def.html#af6aca2bbd40c0fb6df7c3aebe224a360">00992</a>   __IO uint32_t <a class="code" href="struct_r_n_g___type_def.html#af6aca2bbd40c0fb6df7c3aebe224a360">SR</a>;  
<a name="l00993"></a><a class="code" href="struct_r_n_g___type_def.html#a3df0d8dfcd1ec958659ffe21eb64fa94">00993</a>   __IO uint32_t <a class="code" href="struct_r_n_g___type_def.html#a3df0d8dfcd1ec958659ffe21eb64fa94">DR</a>;  
<a name="l00994"></a>00994 } <a class="code" href="struct_r_n_g___type_def.html" title="HASH.">RNG_TypeDef</a>;
<a name="l00995"></a>00995 
<a name="l01003"></a><a class="code" href="group___peripheral__memory__map.html#ga23a9099a5f8fc9c6e253c0eecb2be8db">01003</a> <span class="preprocessor">#define FLASH_BASE            ((uint32_t)0x08000000) </span>
<a name="l01004"></a><a class="code" href="group___peripheral__memory__map.html#gabea1f1810ebeac402164b42ab54bcdf9">01004</a> <span class="preprocessor">#define CCMDATARAM_BASE       ((uint32_t)0x10000000) </span>
<a name="l01005"></a><a class="code" href="group___peripheral__memory__map.html#ga7d0fbfb8894012dbbb96754b95e562cd">01005</a> <span class="preprocessor">#define SRAM1_BASE            ((uint32_t)0x20000000) </span>
<a name="l01006"></a><a class="code" href="group___peripheral__memory__map.html#gadbb42a3d0a8a90a79d2146e4014241b1">01006</a> <span class="preprocessor">#define SRAM2_BASE            ((uint32_t)0x2001C000) </span>
<a name="l01007"></a><a class="code" href="group___peripheral__memory__map.html#ga9171f49478fa86d932f89e78e73b88b0">01007</a> <span class="preprocessor">#define PERIPH_BASE           ((uint32_t)0x40000000) </span>
<a name="l01008"></a><a class="code" href="group___peripheral__memory__map.html#ga52e57051bdf8909222b36e5408a48f32">01008</a> <span class="preprocessor">#define BKPSRAM_BASE          ((uint32_t)0x40024000) </span>
<a name="l01009"></a><a class="code" href="group___peripheral__memory__map.html#gaddf0e199dccba83272b20c9fb4d3aaed">01009</a> <span class="preprocessor">#define FSMC_R_BASE           ((uint32_t)0xA0000000) </span>
<a name="l01011"></a><a class="code" href="group___peripheral__memory__map.html#gaf98d1f99ecd952ee59e80b345d835bb0">01011</a> <span class="preprocessor">#define CCMDATARAM_BB_BASE    ((uint32_t)0x12000000) </span>
<a name="l01012"></a><a class="code" href="group___peripheral__memory__map.html#gac4c4f61082e4b168f29d9cf97dc3ca5c">01012</a> <span class="preprocessor">#define SRAM1_BB_BASE         ((uint32_t)0x22000000) </span>
<a name="l01013"></a><a class="code" href="group___peripheral__memory__map.html#gac33cb6edadf184ab9860d77089503922">01013</a> <span class="preprocessor">#define SRAM2_BB_BASE         ((uint32_t)0x2201C000) </span>
<a name="l01014"></a><a class="code" href="group___peripheral__memory__map.html#gaed7efc100877000845c236ccdc9e144a">01014</a> <span class="preprocessor">#define PERIPH_BB_BASE        ((uint32_t)0x42000000) </span>
<a name="l01015"></a><a class="code" href="group___peripheral__memory__map.html#gaee19a30c9fa326bb10b547e4eaf4e250">01015</a> <span class="preprocessor">#define BKPSRAM_BB_BASE       ((uint32_t)0x42024000) </span>
<a name="l01017"></a>01017 <span class="preprocessor"></span><span class="comment">/* Legacy defines */</span>
<a name="l01018"></a>01018 <span class="preprocessor">#define SRAM_BASE             SRAM1_BASE</span>
<a name="l01019"></a><a class="code" href="group___peripheral__memory__map.html#gad3548b6e2f017f39d399358f3ac98454">01019</a> <span class="preprocessor"></span><span class="preprocessor">#define SRAM_BB_BASE          SRAM1_BB_BASE</span>
<a name="l01020"></a>01020 <span class="preprocessor"></span>
<a name="l01021"></a>01021 
<a name="l01023"></a>01023 <span class="preprocessor">#define APB1PERIPH_BASE       PERIPH_BASE</span>
<a name="l01024"></a>01024 <span class="preprocessor"></span><span class="preprocessor">#define APB2PERIPH_BASE       (PERIPH_BASE + 0x00010000)</span>
<a name="l01025"></a>01025 <span class="preprocessor"></span><span class="preprocessor">#define AHB1PERIPH_BASE       (PERIPH_BASE + 0x00020000)</span>
<a name="l01026"></a><a class="code" href="group___peripheral__memory__map.html#gaeedaa71d22a1948492365e2cd26cfd46">01026</a> <span class="preprocessor"></span><span class="preprocessor">#define AHB2PERIPH_BASE       (PERIPH_BASE + 0x10000000)</span>
<a name="l01027"></a>01027 <span class="preprocessor"></span>
<a name="l01029"></a>01029 <span class="preprocessor">#define TIM2_BASE             (APB1PERIPH_BASE + 0x0000)</span>
<a name="l01030"></a>01030 <span class="preprocessor"></span><span class="preprocessor">#define TIM3_BASE             (APB1PERIPH_BASE + 0x0400)</span>
<a name="l01031"></a>01031 <span class="preprocessor"></span><span class="preprocessor">#define TIM4_BASE             (APB1PERIPH_BASE + 0x0800)</span>
<a name="l01032"></a>01032 <span class="preprocessor"></span><span class="preprocessor">#define TIM5_BASE             (APB1PERIPH_BASE + 0x0C00)</span>
<a name="l01033"></a>01033 <span class="preprocessor"></span><span class="preprocessor">#define TIM6_BASE             (APB1PERIPH_BASE + 0x1000)</span>
<a name="l01034"></a>01034 <span class="preprocessor"></span><span class="preprocessor">#define TIM7_BASE             (APB1PERIPH_BASE + 0x1400)</span>
<a name="l01035"></a>01035 <span class="preprocessor"></span><span class="preprocessor">#define TIM12_BASE            (APB1PERIPH_BASE + 0x1800)</span>
<a name="l01036"></a>01036 <span class="preprocessor"></span><span class="preprocessor">#define TIM13_BASE            (APB1PERIPH_BASE + 0x1C00)</span>
<a name="l01037"></a>01037 <span class="preprocessor"></span><span class="preprocessor">#define TIM14_BASE            (APB1PERIPH_BASE + 0x2000)</span>
<a name="l01038"></a>01038 <span class="preprocessor"></span><span class="preprocessor">#define RTC_BASE              (APB1PERIPH_BASE + 0x2800)</span>
<a name="l01039"></a>01039 <span class="preprocessor"></span><span class="preprocessor">#define WWDG_BASE             (APB1PERIPH_BASE + 0x2C00)</span>
<a name="l01040"></a>01040 <span class="preprocessor"></span><span class="preprocessor">#define IWDG_BASE             (APB1PERIPH_BASE + 0x3000)</span>
<a name="l01041"></a>01041 <span class="preprocessor"></span><span class="preprocessor">#define I2S2ext_BASE          (APB1PERIPH_BASE + 0x3400)</span>
<a name="l01042"></a>01042 <span class="preprocessor"></span><span class="preprocessor">#define SPI2_BASE             (APB1PERIPH_BASE + 0x3800)</span>
<a name="l01043"></a>01043 <span class="preprocessor"></span><span class="preprocessor">#define SPI3_BASE             (APB1PERIPH_BASE + 0x3C00)</span>
<a name="l01044"></a>01044 <span class="preprocessor"></span><span class="preprocessor">#define I2S3ext_BASE          (APB1PERIPH_BASE + 0x4000)</span>
<a name="l01045"></a>01045 <span class="preprocessor"></span><span class="preprocessor">#define USART2_BASE           (APB1PERIPH_BASE + 0x4400)</span>
<a name="l01046"></a>01046 <span class="preprocessor"></span><span class="preprocessor">#define USART3_BASE           (APB1PERIPH_BASE + 0x4800)</span>
<a name="l01047"></a>01047 <span class="preprocessor"></span><span class="preprocessor">#define UART4_BASE            (APB1PERIPH_BASE + 0x4C00)</span>
<a name="l01048"></a>01048 <span class="preprocessor"></span><span class="preprocessor">#define UART5_BASE            (APB1PERIPH_BASE + 0x5000)</span>
<a name="l01049"></a>01049 <span class="preprocessor"></span><span class="preprocessor">#define I2C1_BASE             (APB1PERIPH_BASE + 0x5400)</span>
<a name="l01050"></a>01050 <span class="preprocessor"></span><span class="preprocessor">#define I2C2_BASE             (APB1PERIPH_BASE + 0x5800)</span>
<a name="l01051"></a>01051 <span class="preprocessor"></span><span class="preprocessor">#define I2C3_BASE             (APB1PERIPH_BASE + 0x5C00)</span>
<a name="l01052"></a>01052 <span class="preprocessor"></span><span class="preprocessor">#define CAN1_BASE             (APB1PERIPH_BASE + 0x6400)</span>
<a name="l01053"></a>01053 <span class="preprocessor"></span><span class="preprocessor">#define CAN2_BASE             (APB1PERIPH_BASE + 0x6800)</span>
<a name="l01054"></a>01054 <span class="preprocessor"></span><span class="preprocessor">#define PWR_BASE              (APB1PERIPH_BASE + 0x7000)</span>
<a name="l01055"></a><a class="code" href="group___peripheral__memory__map.html#gad18d0b914c7f68cecbee1a2d23a67d38">01055</a> <span class="preprocessor"></span><span class="preprocessor">#define DAC_BASE              (APB1PERIPH_BASE + 0x7400)</span>
<a name="l01056"></a>01056 <span class="preprocessor"></span>
<a name="l01058"></a>01058 <span class="preprocessor">#define TIM1_BASE             (APB2PERIPH_BASE + 0x0000)</span>
<a name="l01059"></a>01059 <span class="preprocessor"></span><span class="preprocessor">#define TIM8_BASE             (APB2PERIPH_BASE + 0x0400)</span>
<a name="l01060"></a>01060 <span class="preprocessor"></span><span class="preprocessor">#define USART1_BASE           (APB2PERIPH_BASE + 0x1000)</span>
<a name="l01061"></a>01061 <span class="preprocessor"></span><span class="preprocessor">#define USART6_BASE           (APB2PERIPH_BASE + 0x1400)</span>
<a name="l01062"></a>01062 <span class="preprocessor"></span><span class="preprocessor">#define ADC1_BASE             (APB2PERIPH_BASE + 0x2000)</span>
<a name="l01063"></a>01063 <span class="preprocessor"></span><span class="preprocessor">#define ADC2_BASE             (APB2PERIPH_BASE + 0x2100)</span>
<a name="l01064"></a>01064 <span class="preprocessor"></span><span class="preprocessor">#define ADC3_BASE             (APB2PERIPH_BASE + 0x2200)</span>
<a name="l01065"></a>01065 <span class="preprocessor"></span><span class="preprocessor">#define ADC_BASE              (APB2PERIPH_BASE + 0x2300)</span>
<a name="l01066"></a>01066 <span class="preprocessor"></span><span class="preprocessor">#define SDIO_BASE             (APB2PERIPH_BASE + 0x2C00)</span>
<a name="l01067"></a>01067 <span class="preprocessor"></span><span class="preprocessor">#define SPI1_BASE             (APB2PERIPH_BASE + 0x3000)</span>
<a name="l01068"></a>01068 <span class="preprocessor"></span><span class="preprocessor">#define SYSCFG_BASE           (APB2PERIPH_BASE + 0x3800)</span>
<a name="l01069"></a>01069 <span class="preprocessor"></span><span class="preprocessor">#define EXTI_BASE             (APB2PERIPH_BASE + 0x3C00)</span>
<a name="l01070"></a>01070 <span class="preprocessor"></span><span class="preprocessor">#define TIM9_BASE             (APB2PERIPH_BASE + 0x4000)</span>
<a name="l01071"></a>01071 <span class="preprocessor"></span><span class="preprocessor">#define TIM10_BASE            (APB2PERIPH_BASE + 0x4400)</span>
<a name="l01072"></a><a class="code" href="group___peripheral__memory__map.html#ga3a4a06bb84c703084f0509e105ffaf1d">01072</a> <span class="preprocessor"></span><span class="preprocessor">#define TIM11_BASE            (APB2PERIPH_BASE + 0x4800)</span>
<a name="l01073"></a>01073 <span class="preprocessor"></span>
<a name="l01075"></a>01075 <span class="preprocessor">#define GPIOA_BASE            (AHB1PERIPH_BASE + 0x0000)</span>
<a name="l01076"></a>01076 <span class="preprocessor"></span><span class="preprocessor">#define GPIOB_BASE            (AHB1PERIPH_BASE + 0x0400)</span>
<a name="l01077"></a>01077 <span class="preprocessor"></span><span class="preprocessor">#define GPIOC_BASE            (AHB1PERIPH_BASE + 0x0800)</span>
<a name="l01078"></a>01078 <span class="preprocessor"></span><span class="preprocessor">#define GPIOD_BASE            (AHB1PERIPH_BASE + 0x0C00)</span>
<a name="l01079"></a>01079 <span class="preprocessor"></span><span class="preprocessor">#define GPIOE_BASE            (AHB1PERIPH_BASE + 0x1000)</span>
<a name="l01080"></a>01080 <span class="preprocessor"></span><span class="preprocessor">#define GPIOF_BASE            (AHB1PERIPH_BASE + 0x1400)</span>
<a name="l01081"></a>01081 <span class="preprocessor"></span><span class="preprocessor">#define GPIOG_BASE            (AHB1PERIPH_BASE + 0x1800)</span>
<a name="l01082"></a>01082 <span class="preprocessor"></span><span class="preprocessor">#define GPIOH_BASE            (AHB1PERIPH_BASE + 0x1C00)</span>
<a name="l01083"></a>01083 <span class="preprocessor"></span><span class="preprocessor">#define GPIOI_BASE            (AHB1PERIPH_BASE + 0x2000)</span>
<a name="l01084"></a>01084 <span class="preprocessor"></span><span class="preprocessor">#define CRC_BASE              (AHB1PERIPH_BASE + 0x3000)</span>
<a name="l01085"></a>01085 <span class="preprocessor"></span><span class="preprocessor">#define RCC_BASE              (AHB1PERIPH_BASE + 0x3800)</span>
<a name="l01086"></a>01086 <span class="preprocessor"></span><span class="preprocessor">#define FLASH_R_BASE          (AHB1PERIPH_BASE + 0x3C00)</span>
<a name="l01087"></a>01087 <span class="preprocessor"></span><span class="preprocessor">#define DMA1_BASE             (AHB1PERIPH_BASE + 0x6000)</span>
<a name="l01088"></a>01088 <span class="preprocessor"></span><span class="preprocessor">#define DMA1_Stream0_BASE     (DMA1_BASE + 0x010)</span>
<a name="l01089"></a>01089 <span class="preprocessor"></span><span class="preprocessor">#define DMA1_Stream1_BASE     (DMA1_BASE + 0x028)</span>
<a name="l01090"></a>01090 <span class="preprocessor"></span><span class="preprocessor">#define DMA1_Stream2_BASE     (DMA1_BASE + 0x040)</span>
<a name="l01091"></a>01091 <span class="preprocessor"></span><span class="preprocessor">#define DMA1_Stream3_BASE     (DMA1_BASE + 0x058)</span>
<a name="l01092"></a>01092 <span class="preprocessor"></span><span class="preprocessor">#define DMA1_Stream4_BASE     (DMA1_BASE + 0x070)</span>
<a name="l01093"></a>01093 <span class="preprocessor"></span><span class="preprocessor">#define DMA1_Stream5_BASE     (DMA1_BASE + 0x088)</span>
<a name="l01094"></a>01094 <span class="preprocessor"></span><span class="preprocessor">#define DMA1_Stream6_BASE     (DMA1_BASE + 0x0A0)</span>
<a name="l01095"></a>01095 <span class="preprocessor"></span><span class="preprocessor">#define DMA1_Stream7_BASE     (DMA1_BASE + 0x0B8)</span>
<a name="l01096"></a>01096 <span class="preprocessor"></span><span class="preprocessor">#define DMA2_BASE             (AHB1PERIPH_BASE + 0x6400)</span>
<a name="l01097"></a>01097 <span class="preprocessor"></span><span class="preprocessor">#define DMA2_Stream0_BASE     (DMA2_BASE + 0x010)</span>
<a name="l01098"></a>01098 <span class="preprocessor"></span><span class="preprocessor">#define DMA2_Stream1_BASE     (DMA2_BASE + 0x028)</span>
<a name="l01099"></a>01099 <span class="preprocessor"></span><span class="preprocessor">#define DMA2_Stream2_BASE     (DMA2_BASE + 0x040)</span>
<a name="l01100"></a>01100 <span class="preprocessor"></span><span class="preprocessor">#define DMA2_Stream3_BASE     (DMA2_BASE + 0x058)</span>
<a name="l01101"></a>01101 <span class="preprocessor"></span><span class="preprocessor">#define DMA2_Stream4_BASE     (DMA2_BASE + 0x070)</span>
<a name="l01102"></a>01102 <span class="preprocessor"></span><span class="preprocessor">#define DMA2_Stream5_BASE     (DMA2_BASE + 0x088)</span>
<a name="l01103"></a>01103 <span class="preprocessor"></span><span class="preprocessor">#define DMA2_Stream6_BASE     (DMA2_BASE + 0x0A0)</span>
<a name="l01104"></a>01104 <span class="preprocessor"></span><span class="preprocessor">#define DMA2_Stream7_BASE     (DMA2_BASE + 0x0B8)</span>
<a name="l01105"></a>01105 <span class="preprocessor"></span><span class="preprocessor">#define ETH_BASE              (AHB1PERIPH_BASE + 0x8000)</span>
<a name="l01106"></a>01106 <span class="preprocessor"></span><span class="preprocessor">#define ETH_MAC_BASE          (ETH_BASE)</span>
<a name="l01107"></a>01107 <span class="preprocessor"></span><span class="preprocessor">#define ETH_MMC_BASE          (ETH_BASE + 0x0100)</span>
<a name="l01108"></a>01108 <span class="preprocessor"></span><span class="preprocessor">#define ETH_PTP_BASE          (ETH_BASE + 0x0700)</span>
<a name="l01109"></a><a class="code" href="group___peripheral__memory__map.html#gace2114e1b37c1ba88d60f3e831b67e93">01109</a> <span class="preprocessor"></span><span class="preprocessor">#define ETH_DMA_BASE          (ETH_BASE + 0x1000)</span>
<a name="l01110"></a>01110 <span class="preprocessor"></span>
<a name="l01112"></a>01112 <span class="preprocessor">#define DCMI_BASE             (AHB2PERIPH_BASE + 0x50000)</span>
<a name="l01113"></a>01113 <span class="preprocessor"></span><span class="preprocessor">#define CRYP_BASE             (AHB2PERIPH_BASE + 0x60000)</span>
<a name="l01114"></a>01114 <span class="preprocessor"></span><span class="preprocessor">#define HASH_BASE             (AHB2PERIPH_BASE + 0x60400)</span>
<a name="l01115"></a><a class="code" href="group___peripheral__memory__map.html#gab92662976cfe62457141e5b4f83d541c">01115</a> <span class="preprocessor"></span><span class="preprocessor">#define RNG_BASE              (AHB2PERIPH_BASE + 0x60800)</span>
<a name="l01116"></a>01116 <span class="preprocessor"></span>
<a name="l01118"></a>01118 <span class="preprocessor">#define FSMC_Bank1_R_BASE     (FSMC_R_BASE + 0x0000)</span>
<a name="l01119"></a>01119 <span class="preprocessor"></span><span class="preprocessor">#define FSMC_Bank1E_R_BASE    (FSMC_R_BASE + 0x0104)</span>
<a name="l01120"></a>01120 <span class="preprocessor"></span><span class="preprocessor">#define FSMC_Bank2_R_BASE     (FSMC_R_BASE + 0x0060)</span>
<a name="l01121"></a>01121 <span class="preprocessor"></span><span class="preprocessor">#define FSMC_Bank3_R_BASE     (FSMC_R_BASE + 0x0080)</span>
<a name="l01122"></a>01122 <span class="preprocessor"></span><span class="preprocessor">#define FSMC_Bank4_R_BASE     (FSMC_R_BASE + 0x00A0)</span>
<a name="l01123"></a>01123 <span class="preprocessor"></span>
<a name="l01124"></a>01124 <span class="comment">/* Debug MCU registers base address */</span>
<a name="l01125"></a>01125 <span class="preprocessor">#define DBGMCU_BASE           ((uint32_t )0xE0042000)</span>
<a name="l01126"></a>01126 <span class="preprocessor"></span>
<a name="l01134"></a>01134 <span class="preprocessor">#define TIM2                ((TIM_TypeDef *) TIM2_BASE)</span>
<a name="l01135"></a>01135 <span class="preprocessor"></span><span class="preprocessor">#define TIM3                ((TIM_TypeDef *) TIM3_BASE)</span>
<a name="l01136"></a>01136 <span class="preprocessor"></span><span class="preprocessor">#define TIM4                ((TIM_TypeDef *) TIM4_BASE)</span>
<a name="l01137"></a>01137 <span class="preprocessor"></span><span class="preprocessor">#define TIM5                ((TIM_TypeDef *) TIM5_BASE)</span>
<a name="l01138"></a>01138 <span class="preprocessor"></span><span class="preprocessor">#define TIM6                ((TIM_TypeDef *) TIM6_BASE)</span>
<a name="l01139"></a>01139 <span class="preprocessor"></span><span class="preprocessor">#define TIM7                ((TIM_TypeDef *) TIM7_BASE)</span>
<a name="l01140"></a>01140 <span class="preprocessor"></span><span class="preprocessor">#define TIM12               ((TIM_TypeDef *) TIM12_BASE)</span>
<a name="l01141"></a>01141 <span class="preprocessor"></span><span class="preprocessor">#define TIM13               ((TIM_TypeDef *) TIM13_BASE)</span>
<a name="l01142"></a>01142 <span class="preprocessor"></span><span class="preprocessor">#define TIM14               ((TIM_TypeDef *) TIM14_BASE)</span>
<a name="l01143"></a>01143 <span class="preprocessor"></span><span class="preprocessor">#define RTC                 ((RTC_TypeDef *) RTC_BASE)</span>
<a name="l01144"></a>01144 <span class="preprocessor"></span><span class="preprocessor">#define WWDG                ((WWDG_TypeDef *) WWDG_BASE)</span>
<a name="l01145"></a>01145 <span class="preprocessor"></span><span class="preprocessor">#define IWDG                ((IWDG_TypeDef *) IWDG_BASE)</span>
<a name="l01146"></a>01146 <span class="preprocessor"></span><span class="preprocessor">#define I2S2ext             ((SPI_TypeDef *) I2S2ext_BASE)</span>
<a name="l01147"></a>01147 <span class="preprocessor"></span><span class="preprocessor">#define SPI2                ((SPI_TypeDef *) SPI2_BASE)</span>
<a name="l01148"></a>01148 <span class="preprocessor"></span><span class="preprocessor">#define SPI3                ((SPI_TypeDef *) SPI3_BASE)</span>
<a name="l01149"></a>01149 <span class="preprocessor"></span><span class="preprocessor">#define I2S3ext             ((SPI_TypeDef *) I2S3ext_BASE)</span>
<a name="l01150"></a>01150 <span class="preprocessor"></span><span class="preprocessor">#define USART2              ((USART_TypeDef *) USART2_BASE)</span>
<a name="l01151"></a>01151 <span class="preprocessor"></span><span class="preprocessor">#define USART3              ((USART_TypeDef *) USART3_BASE)</span>
<a name="l01152"></a>01152 <span class="preprocessor"></span><span class="preprocessor">#define UART4               ((USART_TypeDef *) UART4_BASE)</span>
<a name="l01153"></a>01153 <span class="preprocessor"></span><span class="preprocessor">#define UART5               ((USART_TypeDef *) UART5_BASE)</span>
<a name="l01154"></a>01154 <span class="preprocessor"></span><span class="preprocessor">#define I2C1                ((I2C_TypeDef *) I2C1_BASE)</span>
<a name="l01155"></a>01155 <span class="preprocessor"></span><span class="preprocessor">#define I2C2                ((I2C_TypeDef *) I2C2_BASE)</span>
<a name="l01156"></a>01156 <span class="preprocessor"></span><span class="preprocessor">#define I2C3                ((I2C_TypeDef *) I2C3_BASE)</span>
<a name="l01157"></a>01157 <span class="preprocessor"></span><span class="preprocessor">#define CAN1                ((CAN_TypeDef *) CAN1_BASE)</span>
<a name="l01158"></a>01158 <span class="preprocessor"></span><span class="preprocessor">#define CAN2                ((CAN_TypeDef *) CAN2_BASE)</span>
<a name="l01159"></a>01159 <span class="preprocessor"></span><span class="preprocessor">#define PWR                 ((PWR_TypeDef *) PWR_BASE)</span>
<a name="l01160"></a>01160 <span class="preprocessor"></span><span class="preprocessor">#define DAC                 ((DAC_TypeDef *) DAC_BASE)</span>
<a name="l01161"></a>01161 <span class="preprocessor"></span><span class="preprocessor">#define TIM1                ((TIM_TypeDef *) TIM1_BASE)</span>
<a name="l01162"></a>01162 <span class="preprocessor"></span><span class="preprocessor">#define TIM8                ((TIM_TypeDef *) TIM8_BASE)</span>
<a name="l01163"></a>01163 <span class="preprocessor"></span><span class="preprocessor">#define USART1              ((USART_TypeDef *) USART1_BASE)</span>
<a name="l01164"></a>01164 <span class="preprocessor"></span><span class="preprocessor">#define USART6              ((USART_TypeDef *) USART6_BASE)</span>
<a name="l01165"></a>01165 <span class="preprocessor"></span><span class="preprocessor">#define ADC                 ((ADC_Common_TypeDef *) ADC_BASE)</span>
<a name="l01166"></a>01166 <span class="preprocessor"></span><span class="preprocessor">#define ADC1                ((ADC_TypeDef *) ADC1_BASE)</span>
<a name="l01167"></a>01167 <span class="preprocessor"></span><span class="preprocessor">#define ADC2                ((ADC_TypeDef *) ADC2_BASE)</span>
<a name="l01168"></a>01168 <span class="preprocessor"></span><span class="preprocessor">#define ADC3                ((ADC_TypeDef *) ADC3_BASE)</span>
<a name="l01169"></a>01169 <span class="preprocessor"></span><span class="preprocessor">#define SDIO                ((SDIO_TypeDef *) SDIO_BASE)</span>
<a name="l01170"></a>01170 <span class="preprocessor"></span><span class="preprocessor">#define SPI1                ((SPI_TypeDef *) SPI1_BASE)</span>
<a name="l01171"></a>01171 <span class="preprocessor"></span><span class="preprocessor">#define SYSCFG              ((SYSCFG_TypeDef *) SYSCFG_BASE)</span>
<a name="l01172"></a>01172 <span class="preprocessor"></span><span class="preprocessor">#define EXTI                ((EXTI_TypeDef *) EXTI_BASE)</span>
<a name="l01173"></a>01173 <span class="preprocessor"></span><span class="preprocessor">#define TIM9                ((TIM_TypeDef *) TIM9_BASE)</span>
<a name="l01174"></a>01174 <span class="preprocessor"></span><span class="preprocessor">#define TIM10               ((TIM_TypeDef *) TIM10_BASE)</span>
<a name="l01175"></a>01175 <span class="preprocessor"></span><span class="preprocessor">#define TIM11               ((TIM_TypeDef *) TIM11_BASE)</span>
<a name="l01176"></a>01176 <span class="preprocessor"></span><span class="preprocessor">#define GPIOA               ((GPIO_TypeDef *) GPIOA_BASE)</span>
<a name="l01177"></a>01177 <span class="preprocessor"></span><span class="preprocessor">#define GPIOB               ((GPIO_TypeDef *) GPIOB_BASE)</span>
<a name="l01178"></a>01178 <span class="preprocessor"></span><span class="preprocessor">#define GPIOC               ((GPIO_TypeDef *) GPIOC_BASE)</span>
<a name="l01179"></a>01179 <span class="preprocessor"></span><span class="preprocessor">#define GPIOD               ((GPIO_TypeDef *) GPIOD_BASE)</span>
<a name="l01180"></a>01180 <span class="preprocessor"></span><span class="preprocessor">#define GPIOE               ((GPIO_TypeDef *) GPIOE_BASE)</span>
<a name="l01181"></a>01181 <span class="preprocessor"></span><span class="preprocessor">#define GPIOF               ((GPIO_TypeDef *) GPIOF_BASE)</span>
<a name="l01182"></a>01182 <span class="preprocessor"></span><span class="preprocessor">#define GPIOG               ((GPIO_TypeDef *) GPIOG_BASE)</span>
<a name="l01183"></a>01183 <span class="preprocessor"></span><span class="preprocessor">#define GPIOH               ((GPIO_TypeDef *) GPIOH_BASE)</span>
<a name="l01184"></a>01184 <span class="preprocessor"></span><span class="preprocessor">#define GPIOI               ((GPIO_TypeDef *) GPIOI_BASE)</span>
<a name="l01185"></a>01185 <span class="preprocessor"></span><span class="preprocessor">#define CRC                 ((CRC_TypeDef *) CRC_BASE)</span>
<a name="l01186"></a>01186 <span class="preprocessor"></span><span class="preprocessor">#define RCC                 ((RCC_TypeDef *) RCC_BASE)</span>
<a name="l01187"></a>01187 <span class="preprocessor"></span><span class="preprocessor">#define FLASH               ((FLASH_TypeDef *) FLASH_R_BASE)</span>
<a name="l01188"></a>01188 <span class="preprocessor"></span><span class="preprocessor">#define DMA1                ((DMA_TypeDef *) DMA1_BASE)</span>
<a name="l01189"></a>01189 <span class="preprocessor"></span><span class="preprocessor">#define DMA1_Stream0        ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE)</span>
<a name="l01190"></a>01190 <span class="preprocessor"></span><span class="preprocessor">#define DMA1_Stream1        ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE)</span>
<a name="l01191"></a>01191 <span class="preprocessor"></span><span class="preprocessor">#define DMA1_Stream2        ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE)</span>
<a name="l01192"></a>01192 <span class="preprocessor"></span><span class="preprocessor">#define DMA1_Stream3        ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE)</span>
<a name="l01193"></a>01193 <span class="preprocessor"></span><span class="preprocessor">#define DMA1_Stream4        ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE)</span>
<a name="l01194"></a>01194 <span class="preprocessor"></span><span class="preprocessor">#define DMA1_Stream5        ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE)</span>
<a name="l01195"></a>01195 <span class="preprocessor"></span><span class="preprocessor">#define DMA1_Stream6        ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE)</span>
<a name="l01196"></a>01196 <span class="preprocessor"></span><span class="preprocessor">#define DMA1_Stream7        ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE)</span>
<a name="l01197"></a>01197 <span class="preprocessor"></span><span class="preprocessor">#define DMA2                ((DMA_TypeDef *) DMA2_BASE)</span>
<a name="l01198"></a>01198 <span class="preprocessor"></span><span class="preprocessor">#define DMA2_Stream0        ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE)</span>
<a name="l01199"></a>01199 <span class="preprocessor"></span><span class="preprocessor">#define DMA2_Stream1        ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE)</span>
<a name="l01200"></a>01200 <span class="preprocessor"></span><span class="preprocessor">#define DMA2_Stream2        ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE)</span>
<a name="l01201"></a>01201 <span class="preprocessor"></span><span class="preprocessor">#define DMA2_Stream3        ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE)</span>
<a name="l01202"></a>01202 <span class="preprocessor"></span><span class="preprocessor">#define DMA2_Stream4        ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE)</span>
<a name="l01203"></a>01203 <span class="preprocessor"></span><span class="preprocessor">#define DMA2_Stream5        ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE)</span>
<a name="l01204"></a>01204 <span class="preprocessor"></span><span class="preprocessor">#define DMA2_Stream6        ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE)</span>
<a name="l01205"></a>01205 <span class="preprocessor"></span><span class="preprocessor">#define DMA2_Stream7        ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE)</span>
<a name="l01206"></a>01206 <span class="preprocessor"></span><span class="preprocessor">#define ETH                 ((ETH_TypeDef *) ETH_BASE)  </span>
<a name="l01207"></a>01207 <span class="preprocessor"></span><span class="preprocessor">#define DCMI                ((DCMI_TypeDef *) DCMI_BASE)</span>
<a name="l01208"></a>01208 <span class="preprocessor"></span><span class="preprocessor">#define CRYP                ((CRYP_TypeDef *) CRYP_BASE)</span>
<a name="l01209"></a>01209 <span class="preprocessor"></span><span class="preprocessor">#define HASH                ((HASH_TypeDef *) HASH_BASE)</span>
<a name="l01210"></a>01210 <span class="preprocessor"></span><span class="preprocessor">#define RNG                 ((RNG_TypeDef *) RNG_BASE)</span>
<a name="l01211"></a>01211 <span class="preprocessor"></span><span class="preprocessor">#define FSMC_Bank1          ((FSMC_Bank1_TypeDef *) FSMC_Bank1_R_BASE)</span>
<a name="l01212"></a>01212 <span class="preprocessor"></span><span class="preprocessor">#define FSMC_Bank1E         ((FSMC_Bank1E_TypeDef *) FSMC_Bank1E_R_BASE)</span>
<a name="l01213"></a>01213 <span class="preprocessor"></span><span class="preprocessor">#define FSMC_Bank2          ((FSMC_Bank2_TypeDef *) FSMC_Bank2_R_BASE)</span>
<a name="l01214"></a>01214 <span class="preprocessor"></span><span class="preprocessor">#define FSMC_Bank3          ((FSMC_Bank3_TypeDef *) FSMC_Bank3_R_BASE)</span>
<a name="l01215"></a>01215 <span class="preprocessor"></span><span class="preprocessor">#define FSMC_Bank4          ((FSMC_Bank4_TypeDef *) FSMC_Bank4_R_BASE)</span>
<a name="l01216"></a>01216 <span class="preprocessor"></span><span class="preprocessor">#define DBGMCU              ((DBGMCU_TypeDef *) DBGMCU_BASE)</span>
<a name="l01217"></a>01217 <span class="preprocessor"></span>
<a name="l01230"></a>01230 <span class="comment">/******************************************************************************/</span>
<a name="l01231"></a>01231 <span class="comment">/*                         Peripheral Registers_Bits_Definition               */</span>
<a name="l01232"></a>01232 <span class="comment">/******************************************************************************/</span>
<a name="l01233"></a>01233 
<a name="l01234"></a>01234 <span class="comment">/******************************************************************************/</span>
<a name="l01235"></a>01235 <span class="comment">/*                                                                            */</span>
<a name="l01236"></a>01236 <span class="comment">/*                        Analog to Digital Converter                         */</span>
<a name="l01237"></a>01237 <span class="comment">/*                                                                            */</span>
<a name="l01238"></a>01238 <span class="comment">/******************************************************************************/</span>
<a name="l01239"></a>01239 <span class="comment">/********************  Bit definition for ADC_SR register  ********************/</span>
<a name="l01240"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga8b7f27694281e4cad956da567e5583b2">01240</a> <span class="preprocessor">#define  ADC_SR_AWD                          ((uint8_t)0x01)               </span>
<a name="l01241"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga3dc295c5253743aeb2cda582953b7b53">01241</a> <span class="preprocessor">#define  ADC_SR_EOC                          ((uint8_t)0x02)               </span>
<a name="l01242"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gabc9f07589bb1a4e398781df372389b56">01242</a> <span class="preprocessor">#define  ADC_SR_JEOC                         ((uint8_t)0x04)               </span>
<a name="l01243"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga7340a01ffec051c06e80a037eee58a14">01243</a> <span class="preprocessor">#define  ADC_SR_JSTRT                        ((uint8_t)0x08)               </span>
<a name="l01244"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga45eb11ad986d8220cde9fa47a91ed222">01244</a> <span class="preprocessor">#define  ADC_SR_STRT                         ((uint8_t)0x10)               </span>
<a name="l01245"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga1e5211d5e3e53cdedf4d9d6fe4ce2a45">01245</a> <span class="preprocessor">#define  ADC_SR_OVR                          ((uint8_t)0x20)               </span>
<a name="l01247"></a>01247 <span class="preprocessor"></span><span class="comment">/*******************  Bit definition for ADC_CR1 register  ********************/</span>
<a name="l01248"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gad8bb755c7059bb2d4f5e2e999d2a2677">01248</a> <span class="preprocessor">#define  ADC_CR1_AWDCH                       ((uint32_t)0x0000001F)        </span>
<a name="l01249"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga18725d77c35c173cdb5bdab658d9dace">01249</a> <span class="preprocessor">#define  ADC_CR1_AWDCH_0                     ((uint32_t)0x00000001)        </span>
<a name="l01250"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gafcd37244d74db7c9a34a4f08b94301ae">01250</a> <span class="preprocessor">#define  ADC_CR1_AWDCH_1                     ((uint32_t)0x00000002)        </span>
<a name="l01251"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga625eebdc95937325cad90a151853f5a0">01251</a> <span class="preprocessor">#define  ADC_CR1_AWDCH_2                     ((uint32_t)0x00000004)        </span>
<a name="l01252"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gafb768d4aafbabc114d4650cf962392ec">01252</a> <span class="preprocessor">#define  ADC_CR1_AWDCH_3                     ((uint32_t)0x00000008)        </span>
<a name="l01253"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaf37f3c0d7c72192803d0772e076cf8ee">01253</a> <span class="preprocessor">#define  ADC_CR1_AWDCH_4                     ((uint32_t)0x00000010)        </span>
<a name="l01254"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaa39fee2e812a7ca45998cccf32e90aea">01254</a> <span class="preprocessor">#define  ADC_CR1_EOCIE                       ((uint32_t)0x00000020)        </span>
<a name="l01255"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gacd44f86b189696d5a3780342516de722">01255</a> <span class="preprocessor">#define  ADC_CR1_AWDIE                       ((uint32_t)0x00000040)        </span>
<a name="l01256"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga5c46fc1dc6c63acf88821f46a8f6d5e7">01256</a> <span class="preprocessor">#define  ADC_CR1_JEOCIE                      ((uint32_t)0x00000080)        </span>
<a name="l01257"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaaeab75ece0c73dd97e8f21911ed22d06">01257</a> <span class="preprocessor">#define  ADC_CR1_SCAN                        ((uint32_t)0x00000100)        </span>
<a name="l01258"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga5c9fc31f19c04033dfa98e982519c451">01258</a> <span class="preprocessor">#define  ADC_CR1_AWDSGL                      ((uint32_t)0x00000200)        </span>
<a name="l01259"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga6353cb0d564410358b3a086dd0241f8c">01259</a> <span class="preprocessor">#define  ADC_CR1_JAUTO                       ((uint32_t)0x00000400)        </span>
<a name="l01260"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gabd690297fc73fca40d797f4c90800b9a">01260</a> <span class="preprocessor">#define  ADC_CR1_DISCEN                      ((uint32_t)0x00000800)        </span>
<a name="l01261"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gacd06a2840346bf45ff335707db0b6e30">01261</a> <span class="preprocessor">#define  ADC_CR1_JDISCEN                     ((uint32_t)0x00001000)        </span>
<a name="l01262"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaeaa416a291023449ae82e7ef39844075">01262</a> <span class="preprocessor">#define  ADC_CR1_DISCNUM                     ((uint32_t)0x0000E000)        </span>
<a name="l01263"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga59ff81db7def261f0e84d5dbb6cca1ce">01263</a> <span class="preprocessor">#define  ADC_CR1_DISCNUM_0                   ((uint32_t)0x00002000)        </span>
<a name="l01264"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga39940d3611126052f4f748934c629ebf">01264</a> <span class="preprocessor">#define  ADC_CR1_DISCNUM_1                   ((uint32_t)0x00004000)        </span>
<a name="l01265"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gab73d5fdf276f5ef3965afdda78ac9e1e">01265</a> <span class="preprocessor">#define  ADC_CR1_DISCNUM_2                   ((uint32_t)0x00008000)        </span>
<a name="l01266"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga4886de74bcd3a1e545094089f76fd0b3">01266</a> <span class="preprocessor">#define  ADC_CR1_JAWDEN                      ((uint32_t)0x00400000)        </span>
<a name="l01267"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga6e006d43fcb9fe1306745c95a1bdd651">01267</a> <span class="preprocessor">#define  ADC_CR1_AWDEN                       ((uint32_t)0x00800000)        </span>
<a name="l01268"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga71e4a4c233895a2e7b6dd3ca6ca849e5">01268</a> <span class="preprocessor">#define  ADC_CR1_RES                         ((uint32_t)0x03000000)        </span>
<a name="l01269"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gacfc432ddbd2140a92d877f6d9dc52417">01269</a> <span class="preprocessor">#define  ADC_CR1_RES_0                       ((uint32_t)0x01000000)        </span>
<a name="l01270"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga674904864f540043692a5b5ead9fae10">01270</a> <span class="preprocessor">#define  ADC_CR1_RES_1                       ((uint32_t)0x02000000)        </span>
<a name="l01271"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaa892fda7c204bf18a33a059f28be0fba">01271</a> <span class="preprocessor">#define  ADC_CR1_OVRIE                       ((uint32_t)0x04000000)         </span>
<a name="l01273"></a>01273 <span class="preprocessor"></span><span class="comment">/*******************  Bit definition for ADC_CR2 register  ********************/</span>
<a name="l01274"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga89b646f092b052d8488d2016f6290f0e">01274</a> <span class="preprocessor">#define  ADC_CR2_ADON                        ((uint32_t)0x00000001)        </span>
<a name="l01275"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga49bb71a868c9d88a0f7bbe48918b2140">01275</a> <span class="preprocessor">#define  ADC_CR2_CONT                        ((uint32_t)0x00000002)        </span>
<a name="l01276"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga017309ac4b532bc8c607388f4e2cbbec">01276</a> <span class="preprocessor">#define  ADC_CR2_DMA                         ((uint32_t)0x00000100)        </span>
<a name="l01277"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga0d7d75f0c4c8fa190fbf9f86fbe6dfc8">01277</a> <span class="preprocessor">#define  ADC_CR2_DDS                         ((uint32_t)0x00000200)        </span>
<a name="l01278"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaf9dac2004ab20295e04012060ab24aeb">01278</a> <span class="preprocessor">#define  ADC_CR2_EOCS                        ((uint32_t)0x00000400)        </span>
<a name="l01279"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaf5950b5a7438a447584f6dd86c343362">01279</a> <span class="preprocessor">#define  ADC_CR2_ALIGN                       ((uint32_t)0x00000800)        </span>
<a name="l01280"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaab3aa5d0e2a4b77960ec8f3b425a3eac">01280</a> <span class="preprocessor">#define  ADC_CR2_JEXTSEL                     ((uint32_t)0x000F0000)        </span>
<a name="l01281"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaa70c1f30e2101e2177ce564440203ba3">01281</a> <span class="preprocessor">#define  ADC_CR2_JEXTSEL_0                   ((uint32_t)0x00010000)        </span>
<a name="l01282"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga99fa4a240d34ce231d6d0543bac7fd9b">01282</a> <span class="preprocessor">#define  ADC_CR2_JEXTSEL_1                   ((uint32_t)0x00020000)        </span>
<a name="l01283"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga571bb97f950181fedbc0d4756482713d">01283</a> <span class="preprocessor">#define  ADC_CR2_JEXTSEL_2                   ((uint32_t)0x00040000)        </span>
<a name="l01284"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gae34f5dda7a153ffd927c9cd38999f822">01284</a> <span class="preprocessor">#define  ADC_CR2_JEXTSEL_3                   ((uint32_t)0x00080000)        </span>
<a name="l01285"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga07330f702208792faca3a563dc4fd9c6">01285</a> <span class="preprocessor">#define  ADC_CR2_JEXTEN                      ((uint32_t)0x00300000)        </span>
<a name="l01286"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga0b3c99510de210ff3137ff8de328889b">01286</a> <span class="preprocessor">#define  ADC_CR2_JEXTEN_0                    ((uint32_t)0x00100000)        </span>
<a name="l01287"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga949c70fdf36a32a6afcbf44fec123832">01287</a> <span class="preprocessor">#define  ADC_CR2_JEXTEN_1                    ((uint32_t)0x00200000)        </span>
<a name="l01288"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gac12fe8a6cc24eef2ed2e1f1525855678">01288</a> <span class="preprocessor">#define  ADC_CR2_JSWSTART                    ((uint32_t)0x00400000)        </span>
<a name="l01289"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga6d1054d6cd017e305cf6e8a864ce96c8">01289</a> <span class="preprocessor">#define  ADC_CR2_EXTSEL                      ((uint32_t)0x0F000000)        </span>
<a name="l01290"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga9410c7fd93f6d0b157ede745ee269d7b">01290</a> <span class="preprocessor">#define  ADC_CR2_EXTSEL_0                    ((uint32_t)0x01000000)        </span>
<a name="l01291"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga5a6725419743a8d01b4a223609952893">01291</a> <span class="preprocessor">#define  ADC_CR2_EXTSEL_1                    ((uint32_t)0x02000000)        </span>
<a name="l01292"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga5c2322988b5fff19d012d9179d412ad0">01292</a> <span class="preprocessor">#define  ADC_CR2_EXTSEL_2                    ((uint32_t)0x04000000)        </span>
<a name="l01293"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga387de6160834197888efa43e164c2db9">01293</a> <span class="preprocessor">#define  ADC_CR2_EXTSEL_3                    ((uint32_t)0x08000000)        </span>
<a name="l01294"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga574b4d8e90655d0432882d620e629234">01294</a> <span class="preprocessor">#define  ADC_CR2_EXTEN                       ((uint32_t)0x30000000)        </span>
<a name="l01295"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga3519da0cc6fbd31444a16244c70232e6">01295</a> <span class="preprocessor">#define  ADC_CR2_EXTEN_0                     ((uint32_t)0x10000000)        </span>
<a name="l01296"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga17e37edddbb6ad791bffb350cca23d4d">01296</a> <span class="preprocessor">#define  ADC_CR2_EXTEN_1                     ((uint32_t)0x20000000)        </span>
<a name="l01297"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga5eae65bad1a6c975e1911eb5ba117468">01297</a> <span class="preprocessor">#define  ADC_CR2_SWSTART                     ((uint32_t)0x40000000)        </span>
<a name="l01299"></a>01299 <span class="preprocessor"></span><span class="comment">/******************  Bit definition for ADC_SMPR1 register  *******************/</span>
<a name="l01300"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga32242a2c2156a012a7343bcb43d490d0">01300</a> <span class="preprocessor">#define  ADC_SMPR1_SMP10                     ((uint32_t)0x00000007)        </span>
<a name="l01301"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga8a8996c53042759f01e966fb00351ebf">01301</a> <span class="preprocessor">#define  ADC_SMPR1_SMP10_0                   ((uint32_t)0x00000001)        </span>
<a name="l01302"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga42b96f058436c8bdcfabe1e08c7edd61">01302</a> <span class="preprocessor">#define  ADC_SMPR1_SMP10_1                   ((uint32_t)0x00000002)        </span>
<a name="l01303"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga289d89b4d92d7f685a8e44aeb9ddcded">01303</a> <span class="preprocessor">#define  ADC_SMPR1_SMP10_2                   ((uint32_t)0x00000004)        </span>
<a name="l01304"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga4c74d559f2a70a2e8c807b7bcaccd800">01304</a> <span class="preprocessor">#define  ADC_SMPR1_SMP11                     ((uint32_t)0x00000038)        </span>
<a name="l01305"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga60780d613953f48a2dfc8debce72fb28">01305</a> <span class="preprocessor">#define  ADC_SMPR1_SMP11_0                   ((uint32_t)0x00000008)        </span>
<a name="l01306"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaa61e1dbafcae3e1c8eae4320a6e5ec5d">01306</a> <span class="preprocessor">#define  ADC_SMPR1_SMP11_1                   ((uint32_t)0x00000010)        </span>
<a name="l01307"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga93a876a9a6d90cd30456433b7e38c3f2">01307</a> <span class="preprocessor">#define  ADC_SMPR1_SMP11_2                   ((uint32_t)0x00000020)        </span>
<a name="l01308"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga433b5a7d944666fb7abed3b107c352fc">01308</a> <span class="preprocessor">#define  ADC_SMPR1_SMP12                     ((uint32_t)0x000001C0)        </span>
<a name="l01309"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaaaac6ae97c00276d7472bc92a9edd6e2">01309</a> <span class="preprocessor">#define  ADC_SMPR1_SMP12_0                   ((uint32_t)0x00000040)        </span>
<a name="l01310"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga6020f9d742e15650ad919aaccaf2ff6c">01310</a> <span class="preprocessor">#define  ADC_SMPR1_SMP12_1                   ((uint32_t)0x00000080)        </span>
<a name="l01311"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gadb59adb544d416e91ea0c12d4f39ccc9">01311</a> <span class="preprocessor">#define  ADC_SMPR1_SMP12_2                   ((uint32_t)0x00000100)        </span>
<a name="l01312"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga2df120cd93a177ea17946a656259129e">01312</a> <span class="preprocessor">#define  ADC_SMPR1_SMP13                     ((uint32_t)0x00000E00)        </span>
<a name="l01313"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga49e7444d6cf630eccfd52fb4155bd553">01313</a> <span class="preprocessor">#define  ADC_SMPR1_SMP13_0                   ((uint32_t)0x00000200)        </span>
<a name="l01314"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gad5d5ad9d8d08feaee18d1f2d8d6787a1">01314</a> <span class="preprocessor">#define  ADC_SMPR1_SMP13_1                   ((uint32_t)0x00000400)        </span>
<a name="l01315"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gac4cd285d46485136deb6223377d0b17c">01315</a> <span class="preprocessor">#define  ADC_SMPR1_SMP13_2                   ((uint32_t)0x00000800)        </span>
<a name="l01316"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gab1574fc02a40f22fc751073e02ebb781">01316</a> <span class="preprocessor">#define  ADC_SMPR1_SMP14                     ((uint32_t)0x00007000)        </span>
<a name="l01317"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga9243898272b1d27018c971eecfa57f78">01317</a> <span class="preprocessor">#define  ADC_SMPR1_SMP14_0                   ((uint32_t)0x00001000)        </span>
<a name="l01318"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga1016b8ca359247491a2a0a5d77aa1c22">01318</a> <span class="preprocessor">#define  ADC_SMPR1_SMP14_1                   ((uint32_t)0x00002000)        </span>
<a name="l01319"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga8e658a8b72bac244bf919a874690e49e">01319</a> <span class="preprocessor">#define  ADC_SMPR1_SMP14_2                   ((uint32_t)0x00004000)        </span>
<a name="l01320"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga5ae0043ad863f7710834217bc82c8ecf">01320</a> <span class="preprocessor">#define  ADC_SMPR1_SMP15                     ((uint32_t)0x00038000)        </span>
<a name="l01321"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gac5f8e555f5ece2ee632dd9d6c60d9584">01321</a> <span class="preprocessor">#define  ADC_SMPR1_SMP15_0                   ((uint32_t)0x00008000)        </span>
<a name="l01322"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gab978e10b7dcfe6c1b88dd4fef50498ac">01322</a> <span class="preprocessor">#define  ADC_SMPR1_SMP15_1                   ((uint32_t)0x00010000)        </span>
<a name="l01323"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga045285e1c5ab9ae570e37fe627b0e117">01323</a> <span class="preprocessor">#define  ADC_SMPR1_SMP15_2                   ((uint32_t)0x00020000)        </span>
<a name="l01324"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga2925d05347e46e9c6a970214fa76bbec">01324</a> <span class="preprocessor">#define  ADC_SMPR1_SMP16                     ((uint32_t)0x001C0000)        </span>
<a name="l01325"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gae1a7d0ef695bd2017bcda3949f0134be">01325</a> <span class="preprocessor">#define  ADC_SMPR1_SMP16_0                   ((uint32_t)0x00040000)        </span>
<a name="l01326"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga793ff2f46f51e1d485a9bd728687bf15">01326</a> <span class="preprocessor">#define  ADC_SMPR1_SMP16_1                   ((uint32_t)0x00080000)        </span>
<a name="l01327"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gade321fdbf74f830e54951ccfca285686">01327</a> <span class="preprocessor">#define  ADC_SMPR1_SMP16_2                   ((uint32_t)0x00100000)        </span>
<a name="l01328"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga9867370ecef7b99c32b8ecb44ad9e581">01328</a> <span class="preprocessor">#define  ADC_SMPR1_SMP17                     ((uint32_t)0x00E00000)        </span>
<a name="l01329"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga42b004d74f288cb191bfc6a327f94480">01329</a> <span class="preprocessor">#define  ADC_SMPR1_SMP17_0                   ((uint32_t)0x00200000)        </span>
<a name="l01330"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga3ac4c21586d6a353c208a5175906ecc1">01330</a> <span class="preprocessor">#define  ADC_SMPR1_SMP17_1                   ((uint32_t)0x00400000)        </span>
<a name="l01331"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gac81ceec799a7da2def4f33339bd5e273">01331</a> <span class="preprocessor">#define  ADC_SMPR1_SMP17_2                   ((uint32_t)0x00800000)        </span>
<a name="l01332"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gac3c7d84a92899d950de236fe9d14df2c">01332</a> <span class="preprocessor">#define  ADC_SMPR1_SMP18                     ((uint32_t)0x07000000)        </span>
<a name="l01333"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga6862168bb7688638764defc72120716b">01333</a> <span class="preprocessor">#define  ADC_SMPR1_SMP18_0                   ((uint32_t)0x01000000)        </span>
<a name="l01334"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga72a01c59a0a785b18235641b36735090">01334</a> <span class="preprocessor">#define  ADC_SMPR1_SMP18_1                   ((uint32_t)0x02000000)        </span>
<a name="l01335"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaec1addc9c417b4b7693768817b058059">01335</a> <span class="preprocessor">#define  ADC_SMPR1_SMP18_2                   ((uint32_t)0x04000000)        </span>
<a name="l01337"></a>01337 <span class="preprocessor"></span><span class="comment">/******************  Bit definition for ADC_SMPR2 register  *******************/</span>
<a name="l01338"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga5a13b3c652e5759e2d8bc7e38889bc5e">01338</a> <span class="preprocessor">#define  ADC_SMPR2_SMP0                      ((uint32_t)0x00000007)        </span>
<a name="l01339"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga1bde59fce56980a59a3dfdb0da7ebe0c">01339</a> <span class="preprocessor">#define  ADC_SMPR2_SMP0_0                    ((uint32_t)0x00000001)        </span>
<a name="l01340"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga1d5b6e025d8e70767914c144793b93e6">01340</a> <span class="preprocessor">#define  ADC_SMPR2_SMP0_1                    ((uint32_t)0x00000002)        </span>
<a name="l01341"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga361de56c56c45834fc837df349f155dc">01341</a> <span class="preprocessor">#define  ADC_SMPR2_SMP0_2                    ((uint32_t)0x00000004)        </span>
<a name="l01342"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga5b85dd0b1708cdf1bf403b07ad51da36">01342</a> <span class="preprocessor">#define  ADC_SMPR2_SMP1                      ((uint32_t)0x00000038)        </span>
<a name="l01343"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaaa99de1a2d2bbe8921353114d03cb7f6">01343</a> <span class="preprocessor">#define  ADC_SMPR2_SMP1_0                    ((uint32_t)0x00000008)        </span>
<a name="l01344"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaf6ceb41e5e3cb6ae7da28070bc0b07d2">01344</a> <span class="preprocessor">#define  ADC_SMPR2_SMP1_1                    ((uint32_t)0x00000010)        </span>
<a name="l01345"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga8b9efc8f9488d389301c4a6f9ef4427a">01345</a> <span class="preprocessor">#define  ADC_SMPR2_SMP1_2                    ((uint32_t)0x00000020)        </span>
<a name="l01346"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaea6e1e298372596bcdcdf93e763b3683">01346</a> <span class="preprocessor">#define  ADC_SMPR2_SMP2                      ((uint32_t)0x000001C0)        </span>
<a name="l01347"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga97e2ac0d4d8afb3aa0b4c09c8fa1d018">01347</a> <span class="preprocessor">#define  ADC_SMPR2_SMP2_0                    ((uint32_t)0x00000040)        </span>
<a name="l01348"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga83fe79e3e10b689a209dc5a724f89199">01348</a> <span class="preprocessor">#define  ADC_SMPR2_SMP2_1                    ((uint32_t)0x00000080)        </span>
<a name="l01349"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gad580d376e0a0bcb34183a6d6735b3122">01349</a> <span class="preprocessor">#define  ADC_SMPR2_SMP2_2                    ((uint32_t)0x00000100)        </span>
<a name="l01350"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga081c3d61e5311a11cb046d56630e1fd0">01350</a> <span class="preprocessor">#define  ADC_SMPR2_SMP3                      ((uint32_t)0x00000E00)        </span>
<a name="l01351"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaa1679a42f67ca4b9b9496dd6000fec01">01351</a> <span class="preprocessor">#define  ADC_SMPR2_SMP3_0                    ((uint32_t)0x00000200)        </span>
<a name="l01352"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga1bf92b0a67dcec9b3c325d58e7e517b0">01352</a> <span class="preprocessor">#define  ADC_SMPR2_SMP3_1                    ((uint32_t)0x00000400)        </span>
<a name="l01353"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga40682268fa8534bd369eb64a329bdf46">01353</a> <span class="preprocessor">#define  ADC_SMPR2_SMP3_2                    ((uint32_t)0x00000800)        </span>
<a name="l01354"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaeab838fcf0aace87b2163b96d208bb64">01354</a> <span class="preprocessor">#define  ADC_SMPR2_SMP4                      ((uint32_t)0x00007000)        </span>
<a name="l01355"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gae4123bce64dc4f1831f992b09d6db4f2">01355</a> <span class="preprocessor">#define  ADC_SMPR2_SMP4_0                    ((uint32_t)0x00001000)        </span>
<a name="l01356"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gad3edf57b459804d17d5a588dd446c763">01356</a> <span class="preprocessor">#define  ADC_SMPR2_SMP4_1                    ((uint32_t)0x00002000)        </span>
<a name="l01357"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gac2a2fd74311c4ffcaed4a8d1a3be2245">01357</a> <span class="preprocessor">#define  ADC_SMPR2_SMP4_2                    ((uint32_t)0x00004000)        </span>
<a name="l01358"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga9500281fa740994b9cfa6a7df8227849">01358</a> <span class="preprocessor">#define  ADC_SMPR2_SMP5                      ((uint32_t)0x00038000)        </span>
<a name="l01359"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga22dd2b1695a4e7a4b1d4ec2b8e244ffc">01359</a> <span class="preprocessor">#define  ADC_SMPR2_SMP5_0                    ((uint32_t)0x00008000)        </span>
<a name="l01360"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gab4de4f6c62646be62d0710dc46eb5e88">01360</a> <span class="preprocessor">#define  ADC_SMPR2_SMP5_1                    ((uint32_t)0x00010000)        </span>
<a name="l01361"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga6c19081d82f2c6478c6aefc207778e1e">01361</a> <span class="preprocessor">#define  ADC_SMPR2_SMP5_2                    ((uint32_t)0x00020000)        </span>
<a name="l01362"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga64cd99c27d07298913541dbdc31aa8ae">01362</a> <span class="preprocessor">#define  ADC_SMPR2_SMP6                      ((uint32_t)0x001C0000)        </span>
<a name="l01363"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gadbebc0a7f368e5846408d768603d9b44">01363</a> <span class="preprocessor">#define  ADC_SMPR2_SMP6_0                    ((uint32_t)0x00040000)        </span>
<a name="l01364"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga27f59166864f7cd0a5e8e6b4450e72d3">01364</a> <span class="preprocessor">#define  ADC_SMPR2_SMP6_1                    ((uint32_t)0x00080000)        </span>
<a name="l01365"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga4139fac7e8ba3e604e35ba906880f909">01365</a> <span class="preprocessor">#define  ADC_SMPR2_SMP6_2                    ((uint32_t)0x00100000)        </span>
<a name="l01366"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga6ec6ee971fc8b2d1890858df94a5c500">01366</a> <span class="preprocessor">#define  ADC_SMPR2_SMP7                      ((uint32_t)0x00E00000)        </span>
<a name="l01367"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga6f30003c59ab6c232d73aa446c77651a">01367</a> <span class="preprocessor">#define  ADC_SMPR2_SMP7_0                    ((uint32_t)0x00200000)        </span>
<a name="l01368"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga0c8708fc97082257b43fa4534c721068">01368</a> <span class="preprocessor">#define  ADC_SMPR2_SMP7_1                    ((uint32_t)0x00400000)        </span>
<a name="l01369"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga2e42897bdc25951a73bac060a7a065ca">01369</a> <span class="preprocessor">#define  ADC_SMPR2_SMP7_2                    ((uint32_t)0x00800000)        </span>
<a name="l01370"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga0695c289e658b772070a7f29797e9cc3">01370</a> <span class="preprocessor">#define  ADC_SMPR2_SMP8                      ((uint32_t)0x07000000)        </span>
<a name="l01371"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gab5f1d2290107eda2dfee33810779b0f6">01371</a> <span class="preprocessor">#define  ADC_SMPR2_SMP8_0                    ((uint32_t)0x01000000)        </span>
<a name="l01372"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gabb9ce9d71f989bad0ed686caf4dd5250">01372</a> <span class="preprocessor">#define  ADC_SMPR2_SMP8_1                    ((uint32_t)0x02000000)        </span>
<a name="l01373"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga3756c6141f55c60da0bcd4d599e7d60d">01373</a> <span class="preprocessor">#define  ADC_SMPR2_SMP8_2                    ((uint32_t)0x04000000)        </span>
<a name="l01374"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga5348f83daaa38060702d7b9cfe2e4005">01374</a> <span class="preprocessor">#define  ADC_SMPR2_SMP9                      ((uint32_t)0x38000000)        </span>
<a name="l01375"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga892f18c89fbaafc74b7d67db74b41423">01375</a> <span class="preprocessor">#define  ADC_SMPR2_SMP9_0                    ((uint32_t)0x08000000)        </span>
<a name="l01376"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga3a6949e61c5845a7ff2331b64cb579bc">01376</a> <span class="preprocessor">#define  ADC_SMPR2_SMP9_1                    ((uint32_t)0x10000000)        </span>
<a name="l01377"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga070135017850599b1e19766c6aa31cd1">01377</a> <span class="preprocessor">#define  ADC_SMPR2_SMP9_2                    ((uint32_t)0x20000000)        </span>
<a name="l01379"></a>01379 <span class="preprocessor"></span><span class="comment">/******************  Bit definition for ADC_JOFR1 register  *******************/</span>
<a name="l01380"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gad76f97130b391455094605a6c803026c">01380</a> <span class="preprocessor">#define  ADC_JOFR1_JOFFSET1                  ((uint16_t)0x0FFF)            </span>
<a name="l01382"></a>01382 <span class="preprocessor"></span><span class="comment">/******************  Bit definition for ADC_JOFR2 register  *******************/</span>
<a name="l01383"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga1b15a9e9ce10303e233059c1de6d956c">01383</a> <span class="preprocessor">#define  ADC_JOFR2_JOFFSET2                  ((uint16_t)0x0FFF)            </span>
<a name="l01385"></a>01385 <span class="preprocessor"></span><span class="comment">/******************  Bit definition for ADC_JOFR3 register  *******************/</span>
<a name="l01386"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga743e4c3a7cefc1a193146e77791c3985">01386</a> <span class="preprocessor">#define  ADC_JOFR3_JOFFSET3                  ((uint16_t)0x0FFF)            </span>
<a name="l01388"></a>01388 <span class="preprocessor"></span><span class="comment">/******************  Bit definition for ADC_JOFR4 register  *******************/</span>
<a name="l01389"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gada0937f2f6a64bd6b7531ad553471b8d">01389</a> <span class="preprocessor">#define  ADC_JOFR4_JOFFSET4                  ((uint16_t)0x0FFF)            </span>
<a name="l01391"></a>01391 <span class="preprocessor"></span><span class="comment">/*******************  Bit definition for ADC_HTR register  ********************/</span>
<a name="l01392"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gad685f031174465e636ef75a5bd7b637d">01392</a> <span class="preprocessor">#define  ADC_HTR_HT                          ((uint16_t)0x0FFF)            </span>
<a name="l01394"></a>01394 <span class="preprocessor"></span><span class="comment">/*******************  Bit definition for ADC_LTR register  ********************/</span>
<a name="l01395"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gac7ac18b970378acf726f04ae68232c24">01395</a> <span class="preprocessor">#define  ADC_LTR_LT                          ((uint16_t)0x0FFF)            </span>
<a name="l01397"></a>01397 <span class="preprocessor"></span><span class="comment">/*******************  Bit definition for ADC_SQR1 register  *******************/</span>
<a name="l01398"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga1ae1998c0dd11275958e7347a92852fc">01398</a> <span class="preprocessor">#define  ADC_SQR1_SQ13                       ((uint32_t)0x0000001F)        </span>
<a name="l01399"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga40d24ddd458198e7731d5abf9d15fc08">01399</a> <span class="preprocessor">#define  ADC_SQR1_SQ13_0                     ((uint32_t)0x00000001)        </span>
<a name="l01400"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaccdca8b0f3cab9f62ae2ffbb9c30546f">01400</a> <span class="preprocessor">#define  ADC_SQR1_SQ13_1                     ((uint32_t)0x00000002)        </span>
<a name="l01401"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga37e8723bfdc43da0b86e40a49b78c9ad">01401</a> <span class="preprocessor">#define  ADC_SQR1_SQ13_2                     ((uint32_t)0x00000004)        </span>
<a name="l01402"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga412374f7ce1f62ee187c819391898778">01402</a> <span class="preprocessor">#define  ADC_SQR1_SQ13_3                     ((uint32_t)0x00000008)        </span>
<a name="l01403"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga05ca5e303f844f512c9a9cb5df9a1028">01403</a> <span class="preprocessor">#define  ADC_SQR1_SQ13_4                     ((uint32_t)0x00000010)        </span>
<a name="l01404"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gab0251199146cb3d0d2c1c0608fbca585">01404</a> <span class="preprocessor">#define  ADC_SQR1_SQ14                       ((uint32_t)0x000003E0)        </span>
<a name="l01405"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gacde3a6d9e94aa1c2399e335911fd6212">01405</a> <span class="preprocessor">#define  ADC_SQR1_SQ14_0                     ((uint32_t)0x00000020)        </span>
<a name="l01406"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga1bc61e4d3ea200e1fc3e9d621ebbd2b4">01406</a> <span class="preprocessor">#define  ADC_SQR1_SQ14_1                     ((uint32_t)0x00000040)        </span>
<a name="l01407"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaeea616e444521cd58c5d8d574c47ccf0">01407</a> <span class="preprocessor">#define  ADC_SQR1_SQ14_2                     ((uint32_t)0x00000080)        </span>
<a name="l01408"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga0e0c9439633fb5c67c8f2138c9d2efae">01408</a> <span class="preprocessor">#define  ADC_SQR1_SQ14_3                     ((uint32_t)0x00000100)        </span>
<a name="l01409"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaea22b4dd0fbb26d2a0babbc483778b0e">01409</a> <span class="preprocessor">#define  ADC_SQR1_SQ14_4                     ((uint32_t)0x00000200)        </span>
<a name="l01410"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga23222c591c6d926f7a741bc9346f1d8f">01410</a> <span class="preprocessor">#define  ADC_SQR1_SQ15                       ((uint32_t)0x00007C00)        </span>
<a name="l01411"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gacbfbc70f67ce1d8f227e17a7f19c123b">01411</a> <span class="preprocessor">#define  ADC_SQR1_SQ15_0                     ((uint32_t)0x00000400)        </span>
<a name="l01412"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gac00e343ff0dd8f1f29e897148e3e070a">01412</a> <span class="preprocessor">#define  ADC_SQR1_SQ15_1                     ((uint32_t)0x00000800)        </span>
<a name="l01413"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gab63443b0c5a2eca60a8c9714f6f31c03">01413</a> <span class="preprocessor">#define  ADC_SQR1_SQ15_2                     ((uint32_t)0x00001000)        </span>
<a name="l01414"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gadf676d45ba227a2dc641b2afadfa7852">01414</a> <span class="preprocessor">#define  ADC_SQR1_SQ15_3                     ((uint32_t)0x00002000)        </span>
<a name="l01415"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga7dbc07d0904f60abcc15827ccab1a8c2">01415</a> <span class="preprocessor">#define  ADC_SQR1_SQ15_4                     ((uint32_t)0x00004000)        </span>
<a name="l01416"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gafecb33099669a080cede6ce0236389e7">01416</a> <span class="preprocessor">#define  ADC_SQR1_SQ16                       ((uint32_t)0x000F8000)        </span>
<a name="l01417"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga3404d0bf04b8561bf93455d968b77ea9">01417</a> <span class="preprocessor">#define  ADC_SQR1_SQ16_0                     ((uint32_t)0x00008000)        </span>
<a name="l01418"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga7ea6af777051f14be5cf166dd4ae69d1">01418</a> <span class="preprocessor">#define  ADC_SQR1_SQ16_1                     ((uint32_t)0x00010000)        </span>
<a name="l01419"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaf59e4a113346ac3daf6829c3321444f5">01419</a> <span class="preprocessor">#define  ADC_SQR1_SQ16_2                     ((uint32_t)0x00020000)        </span>
<a name="l01420"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga6052517e5fcab3f58c42b59fb3ffee55">01420</a> <span class="preprocessor">#define  ADC_SQR1_SQ16_3                     ((uint32_t)0x00040000)        </span>
<a name="l01421"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga7af851b5898b4421958e7a100602c8cd">01421</a> <span class="preprocessor">#define  ADC_SQR1_SQ16_4                     ((uint32_t)0x00080000)        </span>
<a name="l01422"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gae68a19a18d72f6d87c6f2b8cc8bfc6dc">01422</a> <span class="preprocessor">#define  ADC_SQR1_L                          ((uint32_t)0x00F00000)        </span>
<a name="l01423"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga00ec56fbf232492ec12c954e27d03c6c">01423</a> <span class="preprocessor">#define  ADC_SQR1_L_0                        ((uint32_t)0x00100000)        </span>
<a name="l01424"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga52708c6570da08c295603e5b52461ecd">01424</a> <span class="preprocessor">#define  ADC_SQR1_L_1                        ((uint32_t)0x00200000)        </span>
<a name="l01425"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga8b914eeb128157c4acf6f6b9a4be5558">01425</a> <span class="preprocessor">#define  ADC_SQR1_L_2                        ((uint32_t)0x00400000)        </span>
<a name="l01426"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaffdd34daa55da53d18055417ae895c47">01426</a> <span class="preprocessor">#define  ADC_SQR1_L_3                        ((uint32_t)0x00800000)        </span>
<a name="l01428"></a>01428 <span class="preprocessor"></span><span class="comment">/*******************  Bit definition for ADC_SQR2 register  *******************/</span>
<a name="l01429"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaa9f66f702fc124040956117f20ef8df4">01429</a> <span class="preprocessor">#define  ADC_SQR2_SQ7                        ((uint32_t)0x0000001F)        </span>
<a name="l01430"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga12bbc822c10582a80f7e20a11038ce96">01430</a> <span class="preprocessor">#define  ADC_SQR2_SQ7_0                      ((uint32_t)0x00000001)        </span>
<a name="l01431"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga3d0d7daf3b6db6ff4fa382495f6127c6">01431</a> <span class="preprocessor">#define  ADC_SQR2_SQ7_1                      ((uint32_t)0x00000002)        </span>
<a name="l01432"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga74bda24f18a95261661a944cecf45a52">01432</a> <span class="preprocessor">#define  ADC_SQR2_SQ7_2                      ((uint32_t)0x00000004)        </span>
<a name="l01433"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga2697675d008dda4e6a4905fc0f8d22af">01433</a> <span class="preprocessor">#define  ADC_SQR2_SQ7_3                      ((uint32_t)0x00000008)        </span>
<a name="l01434"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga2c46dd0f30ef85094ca0cde2e8c00dac">01434</a> <span class="preprocessor">#define  ADC_SQR2_SQ7_4                      ((uint32_t)0x00000010)        </span>
<a name="l01435"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga308ec58a8d20dcb3a348c30c332a0a8e">01435</a> <span class="preprocessor">#define  ADC_SQR2_SQ8                        ((uint32_t)0x000003E0)        </span>
<a name="l01436"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga858717a28d6c26612ad4ced46863ba13">01436</a> <span class="preprocessor">#define  ADC_SQR2_SQ8_0                      ((uint32_t)0x00000020)        </span>
<a name="l01437"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga2d06168a43b4845409f2fb9193ee474a">01437</a> <span class="preprocessor">#define  ADC_SQR2_SQ8_1                      ((uint32_t)0x00000040)        </span>
<a name="l01438"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaa5eaea65d6719a8199639ec30bb8a07b">01438</a> <span class="preprocessor">#define  ADC_SQR2_SQ8_2                      ((uint32_t)0x00000080)        </span>
<a name="l01439"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga23e22da18926dd107adc69282a445412">01439</a> <span class="preprocessor">#define  ADC_SQR2_SQ8_3                      ((uint32_t)0x00000100)        </span>
<a name="l01440"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gacadd092f31f37bb129065be175673c63">01440</a> <span class="preprocessor">#define  ADC_SQR2_SQ8_4                      ((uint32_t)0x00000200)        </span>
<a name="l01441"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaf5d91ecfc3d40cc6b1960544e526eb91">01441</a> <span class="preprocessor">#define  ADC_SQR2_SQ9                        ((uint32_t)0x00007C00)        </span>
<a name="l01442"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gace032949b436d9af8a20ea10a349d55b">01442</a> <span class="preprocessor">#define  ADC_SQR2_SQ9_0                      ((uint32_t)0x00000400)        </span>
<a name="l01443"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga5cf43f1c5de0e73d6159fabc3681b891">01443</a> <span class="preprocessor">#define  ADC_SQR2_SQ9_1                      ((uint32_t)0x00000800)        </span>
<a name="l01444"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga3389c07a9de242151ffa434908fee39d">01444</a> <span class="preprocessor">#define  ADC_SQR2_SQ9_2                      ((uint32_t)0x00001000)        </span>
<a name="l01445"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga13f30540b9f2d33640ea7d9652dc3c71">01445</a> <span class="preprocessor">#define  ADC_SQR2_SQ9_3                      ((uint32_t)0x00002000)        </span>
<a name="l01446"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga910e5bda9852d49117b76b0d9f420ef2">01446</a> <span class="preprocessor">#define  ADC_SQR2_SQ9_4                      ((uint32_t)0x00004000)        </span>
<a name="l01447"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga22e474b65f217ac21137b1d3f3cbb6bb">01447</a> <span class="preprocessor">#define  ADC_SQR2_SQ10                       ((uint32_t)0x000F8000)        </span>
<a name="l01448"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gab5a36056dbfce703d22387432ac12262">01448</a> <span class="preprocessor">#define  ADC_SQR2_SQ10_0                     ((uint32_t)0x00008000)        </span>
<a name="l01449"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga09a1de734fe67156af26edf3b8a61044">01449</a> <span class="preprocessor">#define  ADC_SQR2_SQ10_1                     ((uint32_t)0x00010000)        </span>
<a name="l01450"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga3b1d6ad0a40e7171d40a964b361d1eb9">01450</a> <span class="preprocessor">#define  ADC_SQR2_SQ10_2                     ((uint32_t)0x00020000)        </span>
<a name="l01451"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga24d63e60eabad897aa9b19dbe56da71e">01451</a> <span class="preprocessor">#define  ADC_SQR2_SQ10_3                     ((uint32_t)0x00040000)        </span>
<a name="l01452"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga7df899f74116e6cb3205af2767840cfb">01452</a> <span class="preprocessor">#define  ADC_SQR2_SQ10_4                     ((uint32_t)0x00080000)        </span>
<a name="l01453"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga7bf491b9c1542fb0d0b83fc96166362e">01453</a> <span class="preprocessor">#define  ADC_SQR2_SQ11                       ((uint32_t)0x01F00000)        </span>
<a name="l01454"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga5bc91fec2ef468c5d39d19beda9ecd3e">01454</a> <span class="preprocessor">#define  ADC_SQR2_SQ11_0                     ((uint32_t)0x00100000)        </span>
<a name="l01455"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga3e142789d2bd0584480e923754544ff5">01455</a> <span class="preprocessor">#define  ADC_SQR2_SQ11_1                     ((uint32_t)0x00200000)        </span>
<a name="l01456"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gad6b844fe698c16437e91c9e05a367a4c">01456</a> <span class="preprocessor">#define  ADC_SQR2_SQ11_2                     ((uint32_t)0x00400000)        </span>
<a name="l01457"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga1a8127191e3c48f4e0952bdb5e196225">01457</a> <span class="preprocessor">#define  ADC_SQR2_SQ11_3                     ((uint32_t)0x00800000)        </span>
<a name="l01458"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga5e8a39f645505ef84cb94bbc8d21b8e0">01458</a> <span class="preprocessor">#define  ADC_SQR2_SQ11_4                     ((uint32_t)0x01000000)        </span>
<a name="l01459"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga8731660b1710e63d5423cd31c11be184">01459</a> <span class="preprocessor">#define  ADC_SQR2_SQ12                       ((uint32_t)0x3E000000)        </span>
<a name="l01460"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga5b2da909e54f8f6f61bf2bd2cd3e93e0">01460</a> <span class="preprocessor">#define  ADC_SQR2_SQ12_0                     ((uint32_t)0x02000000)        </span>
<a name="l01461"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gab5930c4a07d594aa23bc868526b42601">01461</a> <span class="preprocessor">#define  ADC_SQR2_SQ12_1                     ((uint32_t)0x04000000)        </span>
<a name="l01462"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga377805a21e7da2a66a3913a77bcc1e66">01462</a> <span class="preprocessor">#define  ADC_SQR2_SQ12_2                     ((uint32_t)0x08000000)        </span>
<a name="l01463"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga2e3b45cac9aeb68d33b31a0914692857">01463</a> <span class="preprocessor">#define  ADC_SQR2_SQ12_3                     ((uint32_t)0x10000000)        </span>
<a name="l01464"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga6043d31a6cb9bd7c1542c3d41eb296c7">01464</a> <span class="preprocessor">#define  ADC_SQR2_SQ12_4                     ((uint32_t)0x20000000)        </span>
<a name="l01466"></a>01466 <span class="preprocessor"></span><span class="comment">/*******************  Bit definition for ADC_SQR3 register  *******************/</span>
<a name="l01467"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga52491114e8394648559004f3bae718d9">01467</a> <span class="preprocessor">#define  ADC_SQR3_SQ1                        ((uint32_t)0x0000001F)        </span>
<a name="l01468"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga53d3bb1c8bb48c7bcb0f7409db69f7b4">01468</a> <span class="preprocessor">#define  ADC_SQR3_SQ1_0                      ((uint32_t)0x00000001)        </span>
<a name="l01469"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaddb9af3a3b23a103fbc34c4f422fd2af">01469</a> <span class="preprocessor">#define  ADC_SQR3_SQ1_1                      ((uint32_t)0x00000002)        </span>
<a name="l01470"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gadf591f43a15c0c2c5afae2598b8f2afc">01470</a> <span class="preprocessor">#define  ADC_SQR3_SQ1_2                      ((uint32_t)0x00000004)        </span>
<a name="l01471"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga05cfde0ef0e6a8dd6311f5cd7a806556">01471</a> <span class="preprocessor">#define  ADC_SQR3_SQ1_3                      ((uint32_t)0x00000008)        </span>
<a name="l01472"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga9981512f99a6c41ce107a9428d9cfdd0">01472</a> <span class="preprocessor">#define  ADC_SQR3_SQ1_4                      ((uint32_t)0x00000010)        </span>
<a name="l01473"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga60637fb25c099f8da72a8a36211f7a8c">01473</a> <span class="preprocessor">#define  ADC_SQR3_SQ2                        ((uint32_t)0x000003E0)        </span>
<a name="l01474"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaede0302eb64f023913c7a9e588d77937">01474</a> <span class="preprocessor">#define  ADC_SQR3_SQ2_0                      ((uint32_t)0x00000020)        </span>
<a name="l01475"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga158ab7429a864634a46c81fdb51d7508">01475</a> <span class="preprocessor">#define  ADC_SQR3_SQ2_1                      ((uint32_t)0x00000040)        </span>
<a name="l01476"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gae729e21d590271c59c0d653300d5581c">01476</a> <span class="preprocessor">#define  ADC_SQR3_SQ2_2                      ((uint32_t)0x00000080)        </span>
<a name="l01477"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaf65c33275178a8777fa8fed8a01f7389">01477</a> <span class="preprocessor">#define  ADC_SQR3_SQ2_3                      ((uint32_t)0x00000100)        </span>
<a name="l01478"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga990aeb689b7cc8f0bebb3dd6af7b27a6">01478</a> <span class="preprocessor">#define  ADC_SQR3_SQ2_4                      ((uint32_t)0x00000200)        </span>
<a name="l01479"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga601f21b7c1e571fb8c5ff310aca021e1">01479</a> <span class="preprocessor">#define  ADC_SQR3_SQ3                        ((uint32_t)0x00007C00)        </span>
<a name="l01480"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga7fd2c154b5852cb08ce60b4adfa36313">01480</a> <span class="preprocessor">#define  ADC_SQR3_SQ3_0                      ((uint32_t)0x00000400)        </span>
<a name="l01481"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga214580377dd3a424ad819f14f6b025d4">01481</a> <span class="preprocessor">#define  ADC_SQR3_SQ3_1                      ((uint32_t)0x00000800)        </span>
<a name="l01482"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gabae2353b109c9cda2a176ea1f44db4fe">01482</a> <span class="preprocessor">#define  ADC_SQR3_SQ3_2                      ((uint32_t)0x00001000)        </span>
<a name="l01483"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga7d2f00d3372bd1d64bf4eb2271277ab0">01483</a> <span class="preprocessor">#define  ADC_SQR3_SQ3_3                      ((uint32_t)0x00002000)        </span>
<a name="l01484"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga5279e505b1a59b223f30e5be139d5042">01484</a> <span class="preprocessor">#define  ADC_SQR3_SQ3_4                      ((uint32_t)0x00004000)        </span>
<a name="l01485"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga3fc43f70bb3c67c639678b91d852390b">01485</a> <span class="preprocessor">#define  ADC_SQR3_SQ4                        ((uint32_t)0x000F8000)        </span>
<a name="l01486"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gab2a501b20cf758a7353efcb3f95a3a93">01486</a> <span class="preprocessor">#define  ADC_SQR3_SQ4_0                      ((uint32_t)0x00008000)        </span>
<a name="l01487"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaffafa27fd561e4c7d419e3f665d80f2c">01487</a> <span class="preprocessor">#define  ADC_SQR3_SQ4_1                      ((uint32_t)0x00010000)        </span>
<a name="l01488"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gad0251fa70e400ee74f442d8fba2b1afb">01488</a> <span class="preprocessor">#define  ADC_SQR3_SQ4_2                      ((uint32_t)0x00020000)        </span>
<a name="l01489"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga3dc48c3c6b304517261486d8a63637ae">01489</a> <span class="preprocessor">#define  ADC_SQR3_SQ4_3                      ((uint32_t)0x00040000)        </span>
<a name="l01490"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gafe23b9e640df96ca84eab4b6b4f44083">01490</a> <span class="preprocessor">#define  ADC_SQR3_SQ4_4                      ((uint32_t)0x00080000)        </span>
<a name="l01491"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaae841d68049442e4568b86322ed4be6f">01491</a> <span class="preprocessor">#define  ADC_SQR3_SQ5                        ((uint32_t)0x01F00000)        </span>
<a name="l01492"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaa1de9fc24755b715c700c6442f4a396b">01492</a> <span class="preprocessor">#define  ADC_SQR3_SQ5_0                      ((uint32_t)0x00100000)        </span>
<a name="l01493"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga3f704feb58eecb39bc7f199577064172">01493</a> <span class="preprocessor">#define  ADC_SQR3_SQ5_1                      ((uint32_t)0x00200000)        </span>
<a name="l01494"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga88a7994f637a75d105cc5975b154c373">01494</a> <span class="preprocessor">#define  ADC_SQR3_SQ5_2                      ((uint32_t)0x00400000)        </span>
<a name="l01495"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga31c6fce8f01e75c68124124061f67f0e">01495</a> <span class="preprocessor">#define  ADC_SQR3_SQ5_3                      ((uint32_t)0x00800000)        </span>
<a name="l01496"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga6b0cad694c068ea8874b6504bd6ae885">01496</a> <span class="preprocessor">#define  ADC_SQR3_SQ5_4                      ((uint32_t)0x01000000)        </span>
<a name="l01497"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga723792274b16b342d16d6a02fce74ba6">01497</a> <span class="preprocessor">#define  ADC_SQR3_SQ6                        ((uint32_t)0x3E000000)        </span>
<a name="l01498"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga91b8b5293abd0601c543c13a0b53b335">01498</a> <span class="preprocessor">#define  ADC_SQR3_SQ6_0                      ((uint32_t)0x02000000)        </span>
<a name="l01499"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gab29847362a613b43eeeda6db758d781e">01499</a> <span class="preprocessor">#define  ADC_SQR3_SQ6_1                      ((uint32_t)0x04000000)        </span>
<a name="l01500"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaa92c8ea1bfb42ed80622770ae2dc41ab">01500</a> <span class="preprocessor">#define  ADC_SQR3_SQ6_2                      ((uint32_t)0x08000000)        </span>
<a name="l01501"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaed2d7edb11fb84b02c175acff305a922">01501</a> <span class="preprocessor">#define  ADC_SQR3_SQ6_3                      ((uint32_t)0x10000000)        </span>
<a name="l01502"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga78f9e51811549a6797ecfe1468def4ff">01502</a> <span class="preprocessor">#define  ADC_SQR3_SQ6_4                      ((uint32_t)0x20000000)        </span>
<a name="l01504"></a>01504 <span class="preprocessor"></span><span class="comment">/*******************  Bit definition for ADC_JSQR register  *******************/</span>
<a name="l01505"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gad7fa15dfe51b084b36cb5df2fbf44bb2">01505</a> <span class="preprocessor">#define  ADC_JSQR_JSQ1                       ((uint32_t)0x0000001F)        </span>
<a name="l01506"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaf3ea38b080462c4571524b5fcbfed292">01506</a> <span class="preprocessor">#define  ADC_JSQR_JSQ1_0                     ((uint32_t)0x00000001)        </span>
<a name="l01507"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gabae36d7655fb1dce11e60ffa8e57b509">01507</a> <span class="preprocessor">#define  ADC_JSQR_JSQ1_1                     ((uint32_t)0x00000002)        </span>
<a name="l01508"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gad3e7a96d33f640444b40b70e9ee28671">01508</a> <span class="preprocessor">#define  ADC_JSQR_JSQ1_2                     ((uint32_t)0x00000004)        </span>
<a name="l01509"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga6066a6aef47f317a5df0c9bbf59121fb">01509</a> <span class="preprocessor">#define  ADC_JSQR_JSQ1_3                     ((uint32_t)0x00000008)        </span>
<a name="l01510"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaf2c4baf98380a477cebb01be3e8f0594">01510</a> <span class="preprocessor">#define  ADC_JSQR_JSQ1_4                     ((uint32_t)0x00000010)        </span>
<a name="l01511"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga3e8446a5857e5379cff8cadf822e15d4">01511</a> <span class="preprocessor">#define  ADC_JSQR_JSQ2                       ((uint32_t)0x000003E0)        </span>
<a name="l01512"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaabf0889d056b56e4a113142b3694166d">01512</a> <span class="preprocessor">#define  ADC_JSQR_JSQ2_0                     ((uint32_t)0x00000020)        </span>
<a name="l01513"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga048f97e9e332adb21eca27b647af1378">01513</a> <span class="preprocessor">#define  ADC_JSQR_JSQ2_1                     ((uint32_t)0x00000040)        </span>
<a name="l01514"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga18bee187ed94e73b16eeea7501394581">01514</a> <span class="preprocessor">#define  ADC_JSQR_JSQ2_2                     ((uint32_t)0x00000080)        </span>
<a name="l01515"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga78b031d11b56e49b2c28c1a79136b48a">01515</a> <span class="preprocessor">#define  ADC_JSQR_JSQ2_3                     ((uint32_t)0x00000100)        </span>
<a name="l01516"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga064d6ccde30a22430c658b8efc431e59">01516</a> <span class="preprocessor">#define  ADC_JSQR_JSQ2_4                     ((uint32_t)0x00000200)        </span>
<a name="l01517"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gae2fbdc1b854a54c4288402c2d3a7fca9">01517</a> <span class="preprocessor">#define  ADC_JSQR_JSQ3                       ((uint32_t)0x00007C00)        </span>
<a name="l01518"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga12fbc27c3543f23125f632dfa60fdc98">01518</a> <span class="preprocessor">#define  ADC_JSQR_JSQ3_0                     ((uint32_t)0x00000400)        </span>
<a name="l01519"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga169ec7d371e3ee897b73c3ad84b6ed32">01519</a> <span class="preprocessor">#define  ADC_JSQR_JSQ3_1                     ((uint32_t)0x00000800)        </span>
<a name="l01520"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga693542d5a536304f364476589ba0bec9">01520</a> <span class="preprocessor">#define  ADC_JSQR_JSQ3_2                     ((uint32_t)0x00001000)        </span>
<a name="l01521"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga139ddd01c0faf219dca844477453149e">01521</a> <span class="preprocessor">#define  ADC_JSQR_JSQ3_3                     ((uint32_t)0x00002000)        </span>
<a name="l01522"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gac1452b8cf4acc90fb522d90751043aac">01522</a> <span class="preprocessor">#define  ADC_JSQR_JSQ3_4                     ((uint32_t)0x00004000)        </span>
<a name="l01523"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga39a279051ef198ee34cad73743b996f4">01523</a> <span class="preprocessor">#define  ADC_JSQR_JSQ4                       ((uint32_t)0x000F8000)        </span>
<a name="l01524"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga13e250d329673c02f7a0d24d25e83649">01524</a> <span class="preprocessor">#define  ADC_JSQR_JSQ4_0                     ((uint32_t)0x00008000)        </span>
<a name="l01525"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga30dad81d708c35136e2da4e96cfe07b7">01525</a> <span class="preprocessor">#define  ADC_JSQR_JSQ4_1                     ((uint32_t)0x00010000)        </span>
<a name="l01526"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga6ceab97acb95b31cb7448c9da38fc11a">01526</a> <span class="preprocessor">#define  ADC_JSQR_JSQ4_2                     ((uint32_t)0x00020000)        </span>
<a name="l01527"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga52f6571e7efed6a0f72df19c66d3c917">01527</a> <span class="preprocessor">#define  ADC_JSQR_JSQ4_3                     ((uint32_t)0x00040000)        </span>
<a name="l01528"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaede3a17ef541039943d9dcd85df223ca">01528</a> <span class="preprocessor">#define  ADC_JSQR_JSQ4_4                     ((uint32_t)0x00080000)        </span>
<a name="l01529"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaa624d1fe34014b88873e2dfa91f79232">01529</a> <span class="preprocessor">#define  ADC_JSQR_JL                         ((uint32_t)0x00300000)        </span>
<a name="l01530"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga117a6719241f20dbd765bc34f9ffcd58">01530</a> <span class="preprocessor">#define  ADC_JSQR_JL_0                       ((uint32_t)0x00100000)        </span>
<a name="l01531"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga1f82ef3b6e6350b9e52e622daeaa3e6e">01531</a> <span class="preprocessor">#define  ADC_JSQR_JL_1                       ((uint32_t)0x00200000)        </span>
<a name="l01533"></a>01533 <span class="preprocessor"></span><span class="comment">/*******************  Bit definition for ADC_JDR1 register  *******************/</span>
<a name="l01534"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gad02fcd8fd97b2f7d70a5a04fed60b558">01534</a> <span class="preprocessor">#define  ADC_JDR1_JDATA                      ((uint16_t)0xFFFF)            </span>
<a name="l01536"></a>01536 <span class="preprocessor"></span><span class="comment">/*******************  Bit definition for ADC_JDR2 register  *******************/</span>
<a name="l01537"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga9fbd8801b9c60269ca477062985a08e8">01537</a> <span class="preprocessor">#define  ADC_JDR2_JDATA                      ((uint16_t)0xFFFF)            </span>
<a name="l01539"></a>01539 <span class="preprocessor"></span><span class="comment">/*******************  Bit definition for ADC_JDR3 register  *******************/</span>
<a name="l01540"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaae84e9e5928bb9ed1aef6c83089fb5ef">01540</a> <span class="preprocessor">#define  ADC_JDR3_JDATA                      ((uint16_t)0xFFFF)            </span>
<a name="l01542"></a>01542 <span class="preprocessor"></span><span class="comment">/*******************  Bit definition for ADC_JDR4 register  *******************/</span>
<a name="l01543"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga48d8fafdad1fb1bb0f761fd833e7b0c1">01543</a> <span class="preprocessor">#define  ADC_JDR4_JDATA                      ((uint16_t)0xFFFF)            </span>
<a name="l01545"></a>01545 <span class="preprocessor"></span><span class="comment">/********************  Bit definition for ADC_DR register  ********************/</span>
<a name="l01546"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gada596183c4087696c486546e88176038">01546</a> <span class="preprocessor">#define  ADC_DR_DATA                         ((uint32_t)0x0000FFFF)        </span>
<a name="l01547"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga67c396288ac97bfab2d37017bd536b98">01547</a> <span class="preprocessor">#define  ADC_DR_ADC2DATA                     ((uint32_t)0xFFFF0000)        </span>
<a name="l01549"></a>01549 <span class="preprocessor"></span><span class="comment">/*******************  Bit definition for ADC_CSR register  ********************/</span>
<a name="l01550"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga3e640f7443f14d01a37e29cff004223f">01550</a> <span class="preprocessor">#define  ADC_CSR_AWD1                        ((uint32_t)0x00000001)        </span>
<a name="l01551"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga715bcb019d713187aacd46f4482fa5f9">01551</a> <span class="preprocessor">#define  ADC_CSR_EOC1                        ((uint32_t)0x00000002)        </span>
<a name="l01552"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga1a8a134d8b946f3549390294ef94b8d6">01552</a> <span class="preprocessor">#define  ADC_CSR_JEOC1                       ((uint32_t)0x00000004)        </span>
<a name="l01553"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga3f1e6578b14d71c6d972c6d6f6d48eaa">01553</a> <span class="preprocessor">#define  ADC_CSR_JSTRT1                      ((uint32_t)0x00000008)        </span>
<a name="l01554"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga78ff468cfaa299ef62ab7b8b9910e142">01554</a> <span class="preprocessor">#define  ADC_CSR_STRT1                       ((uint32_t)0x00000010)        </span>
<a name="l01555"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga321ed2ccdf98d3a3307947056a8c401a">01555</a> <span class="preprocessor">#define  ADC_CSR_DOVR1                       ((uint32_t)0x00000020)        </span>
<a name="l01556"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga80d8090a99ec65807ed831fea0d5524c">01556</a> <span class="preprocessor">#define  ADC_CSR_AWD2                        ((uint32_t)0x00000100)        </span>
<a name="l01557"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga411d79254769bbb4eeb14964abad497a">01557</a> <span class="preprocessor">#define  ADC_CSR_EOC2                        ((uint32_t)0x00000200)        </span>
<a name="l01558"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaf24dbb77fadc6f928b8e38199a08abc7">01558</a> <span class="preprocessor">#define  ADC_CSR_JEOC2                       ((uint32_t)0x00000400)        </span>
<a name="l01559"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga0ca65d6d580299518fb7491e1cebac1d">01559</a> <span class="preprocessor">#define  ADC_CSR_JSTRT2                      ((uint32_t)0x00000800)        </span>
<a name="l01560"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gac9e79005049b17d08c28aeca86677655">01560</a> <span class="preprocessor">#define  ADC_CSR_STRT2                       ((uint32_t)0x00001000)        </span>
<a name="l01561"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga00e2a30df5568b5663e9f016743b3a35">01561</a> <span class="preprocessor">#define  ADC_CSR_DOVR2                       ((uint32_t)0x00002000)        </span>
<a name="l01562"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gad8883de33c5a7b30c611db11340fec6d">01562</a> <span class="preprocessor">#define  ADC_CSR_AWD3                        ((uint32_t)0x00010000)        </span>
<a name="l01563"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga4a94c410343ba459146b2bb17833a795">01563</a> <span class="preprocessor">#define  ADC_CSR_EOC3                        ((uint32_t)0x00020000)        </span>
<a name="l01564"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gae7d3c36f449ef1ee9ee20c5686b4e974">01564</a> <span class="preprocessor">#define  ADC_CSR_JEOC3                       ((uint32_t)0x00040000)        </span>
<a name="l01565"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga94140d21b4c83d9f401cc459a7ec6060">01565</a> <span class="preprocessor">#define  ADC_CSR_JSTRT3                      ((uint32_t)0x00080000)        </span>
<a name="l01566"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga13ca665cc575b64588475723f5289d4a">01566</a> <span class="preprocessor">#define  ADC_CSR_STRT3                       ((uint32_t)0x00100000)        </span>
<a name="l01567"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga396513974cf26f2a4aa0f36e755e227c">01567</a> <span class="preprocessor">#define  ADC_CSR_DOVR3                       ((uint32_t)0x00200000)        </span>
<a name="l01569"></a>01569 <span class="preprocessor"></span><span class="comment">/*******************  Bit definition for ADC_CCR register  ********************/</span>
<a name="l01570"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaf70ab04667c7c7da0f29c0e5a6c48e68">01570</a> <span class="preprocessor">#define  ADC_CCR_MULTI                       ((uint32_t)0x0000001F)        </span>
<a name="l01571"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gae4e7104ce01e3a79b8f6138d87dc3684">01571</a> <span class="preprocessor">#define  ADC_CCR_MULTI_0                     ((uint32_t)0x00000001)        </span>
<a name="l01572"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga8781dec7f076b475b85f8470aee94d06">01572</a> <span class="preprocessor">#define  ADC_CCR_MULTI_1                     ((uint32_t)0x00000002)        </span>
<a name="l01573"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gae6a5be6cff1227431b8d54dffcc1ce88">01573</a> <span class="preprocessor">#define  ADC_CCR_MULTI_2                     ((uint32_t)0x00000004)        </span>
<a name="l01574"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gae55be7b911b4c0272543f98a0dba5f20">01574</a> <span class="preprocessor">#define  ADC_CCR_MULTI_3                     ((uint32_t)0x00000008)        </span>
<a name="l01575"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga5087b3cb0d4570b80b3138c277bcbf6c">01575</a> <span class="preprocessor">#define  ADC_CCR_MULTI_4                     ((uint32_t)0x00000010)        </span>
<a name="l01576"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga9c13aa04949ed520cf92613d3a619198">01576</a> <span class="preprocessor">#define  ADC_CCR_DELAY                       ((uint32_t)0x00000F00)        </span>
<a name="l01577"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga22b71e9df8b1fca93802ad602341eb0b">01577</a> <span class="preprocessor">#define  ADC_CCR_DELAY_0                     ((uint32_t)0x00000100)        </span>
<a name="l01578"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga6d0d5785cb6c75e700517e88af188573">01578</a> <span class="preprocessor">#define  ADC_CCR_DELAY_1                     ((uint32_t)0x00000200)        </span>
<a name="l01579"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga17f85cbda5dcf9a392a29befb73c6ceb">01579</a> <span class="preprocessor">#define  ADC_CCR_DELAY_2                     ((uint32_t)0x00000400)        </span>
<a name="l01580"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gae0216de7d6fcfa507c9aa1400972d862">01580</a> <span class="preprocessor">#define  ADC_CCR_DELAY_3                     ((uint32_t)0x00000800)        </span>
<a name="l01581"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga7e745513bbc2e5e5a76ae999d5d535af">01581</a> <span class="preprocessor">#define  ADC_CCR_DDS                         ((uint32_t)0x00002000)        </span>
<a name="l01582"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga9e346b21afcaeced784e6c80b3aa1fb4">01582</a> <span class="preprocessor">#define  ADC_CCR_DMA                         ((uint32_t)0x0000C000)        </span>
<a name="l01583"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga3a42ee6ec5115244aef8f60d35abcc47">01583</a> <span class="preprocessor">#define  ADC_CCR_DMA_0                       ((uint32_t)0x00004000)        </span>
<a name="l01584"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gacdc9d29cafdd54e5c0dd752c358e1bc8">01584</a> <span class="preprocessor">#define  ADC_CCR_DMA_1                       ((uint32_t)0x00008000)        </span>
<a name="l01585"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga3a2ee019aef4c64fffc72141f7aaab2c">01585</a> <span class="preprocessor">#define  ADC_CCR_ADCPRE                      ((uint32_t)0x00030000)        </span>
<a name="l01586"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaf3108cc8fb81f6efd1e93fa5f82ac313">01586</a> <span class="preprocessor">#define  ADC_CCR_ADCPRE_0                    ((uint32_t)0x00010000)        </span>
<a name="l01587"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gafa090830d2d359db04f365d46c6644d5">01587</a> <span class="preprocessor">#define  ADC_CCR_ADCPRE_1                    ((uint32_t)0x00020000)        </span>
<a name="l01588"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga519645e42dcf6b19af9c05dc40300abb">01588</a> <span class="preprocessor">#define  ADC_CCR_VBATE                       ((uint32_t)0x00400000)        </span>
<a name="l01589"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gafc020d85a8740491ce3f218a0706f1dc">01589</a> <span class="preprocessor">#define  ADC_CCR_TSVREFE                     ((uint32_t)0x00800000)        </span>
<a name="l01591"></a>01591 <span class="preprocessor"></span><span class="comment">/*******************  Bit definition for ADC_CDR register  ********************/</span>
<a name="l01592"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga6d7a0a18c77816c45c5682c3884e3d56">01592</a> <span class="preprocessor">#define  ADC_CDR_DATA1                      ((uint32_t)0x0000FFFF)         </span>
<a name="l01593"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga55f0776b9bf2612c194c1ab478d8a371">01593</a> <span class="preprocessor">#define  ADC_CDR_DATA2                      ((uint32_t)0xFFFF0000)         </span>
<a name="l01595"></a>01595 <span class="preprocessor"></span><span class="comment">/******************************************************************************/</span>
<a name="l01596"></a>01596 <span class="comment">/*                                                                            */</span>
<a name="l01597"></a>01597 <span class="comment">/*                         Controller Area Network                            */</span>
<a name="l01598"></a>01598 <span class="comment">/*                                                                            */</span>
<a name="l01599"></a>01599 <span class="comment">/******************************************************************************/</span>
<a name="l01601"></a>01601 <span class="comment">/*******************  Bit definition for CAN_MCR register  ********************/</span>
<a name="l01602"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga0cf12be5661908dbe38aa14cd4c3a356">01602</a> <span class="preprocessor">#define  CAN_MCR_INRQ                        ((uint16_t)0x0001)            </span>
<a name="l01603"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gadf9602dfb2f95b481b6e642b95991176">01603</a> <span class="preprocessor">#define  CAN_MCR_SLEEP                       ((uint16_t)0x0002)            </span>
<a name="l01604"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga35e7e66f9cd8cb6efa6a80367d2294a9">01604</a> <span class="preprocessor">#define  CAN_MCR_TXFP                        ((uint16_t)0x0004)            </span>
<a name="l01605"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga501125ff257a7d02c35a0d6dcbaa2ba8">01605</a> <span class="preprocessor">#define  CAN_MCR_RFLM                        ((uint16_t)0x0008)            </span>
<a name="l01606"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga2774f04e286942d36a5b6135c8028049">01606</a> <span class="preprocessor">#define  CAN_MCR_NART                        ((uint16_t)0x0010)            </span>
<a name="l01607"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaa2745f1a565c3f2ec5b16612d1fd66e0">01607</a> <span class="preprocessor">#define  CAN_MCR_AWUM                        ((uint16_t)0x0020)            </span>
<a name="l01608"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gad7aff5c0a3ead7f937849ab66eba7490">01608</a> <span class="preprocessor">#define  CAN_MCR_ABOM                        ((uint16_t)0x0040)            </span>
<a name="l01609"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga32b2eda9cad8a969c5d2349bd1d853bb">01609</a> <span class="preprocessor">#define  CAN_MCR_TTCM                        ((uint16_t)0x0080)            </span>
<a name="l01610"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga410fdbad37a9dbda508b8c437277e79f">01610</a> <span class="preprocessor">#define  CAN_MCR_RESET                       ((uint16_t)0x8000)            </span>
<a name="l01612"></a>01612 <span class="preprocessor"></span><span class="comment">/*******************  Bit definition for CAN_MSR register  ********************/</span>
<a name="l01613"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga2871cee90ebecb760bab16e9c039b682">01613</a> <span class="preprocessor">#define  CAN_MSR_INAK                        ((uint16_t)0x0001)            </span>
<a name="l01614"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaf1611badb362f0fd9047af965509f074">01614</a> <span class="preprocessor">#define  CAN_MSR_SLAK                        ((uint16_t)0x0002)            </span>
<a name="l01615"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga9c424768e9e963402f37cb95ae87a1ae">01615</a> <span class="preprocessor">#define  CAN_MSR_ERRI                        ((uint16_t)0x0004)            </span>
<a name="l01616"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga0f4c753b96d21c5001b39ad5b08519fc">01616</a> <span class="preprocessor">#define  CAN_MSR_WKUI                        ((uint16_t)0x0008)            </span>
<a name="l01617"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga47ab62ae123c791de27ad05dde5bee91">01617</a> <span class="preprocessor">#define  CAN_MSR_SLAKI                       ((uint16_t)0x0010)            </span>
<a name="l01618"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga651580d35b658e90ea831cb13b8a8988">01618</a> <span class="preprocessor">#define  CAN_MSR_TXM                         ((uint16_t)0x0100)            </span>
<a name="l01619"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga67f8e1140b0304930d5b4f2a041a7884">01619</a> <span class="preprocessor">#define  CAN_MSR_RXM                         ((uint16_t)0x0200)            </span>
<a name="l01620"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaf68038824bb78c4a5c4dee1730848f69">01620</a> <span class="preprocessor">#define  CAN_MSR_SAMP                        ((uint16_t)0x0400)            </span>
<a name="l01621"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga6564a1d2f23f246053188a454264eb4b">01621</a> <span class="preprocessor">#define  CAN_MSR_RX                          ((uint16_t)0x0800)            </span>
<a name="l01623"></a>01623 <span class="preprocessor"></span><span class="comment">/*******************  Bit definition for CAN_TSR register  ********************/</span>
<a name="l01624"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga4a4809b8908618df57e6393cc7fe0f52">01624</a> <span class="preprocessor">#define  CAN_TSR_RQCP0                       ((uint32_t)0x00000001)        </span>
<a name="l01625"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaacedb237b31d29aef7f38475e9a6b297">01625</a> <span class="preprocessor">#define  CAN_TSR_TXOK0                       ((uint32_t)0x00000002)        </span>
<a name="l01626"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga9b94ea5001d70a26ec32d9dc6ff76e47">01626</a> <span class="preprocessor">#define  CAN_TSR_ALST0                       ((uint32_t)0x00000004)        </span>
<a name="l01627"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga805d2dab5b1d4618492b1cf2a3f5e1e0">01627</a> <span class="preprocessor">#define  CAN_TSR_TERR0                       ((uint32_t)0x00000008)        </span>
<a name="l01628"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gafdac6b87a303b0d0ec9b0d94a54ae31f">01628</a> <span class="preprocessor">#define  CAN_TSR_ABRQ0                       ((uint32_t)0x00000080)        </span>
<a name="l01629"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gabd3118dec59c3a45d2f262b090699538">01629</a> <span class="preprocessor">#define  CAN_TSR_RQCP1                       ((uint32_t)0x00000100)        </span>
<a name="l01630"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaea918e510c5471b1ac797350b7950151">01630</a> <span class="preprocessor">#define  CAN_TSR_TXOK1                       ((uint32_t)0x00000200)        </span>
<a name="l01631"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga7a34d996177f23148c9b4cd6b0a80529">01631</a> <span class="preprocessor">#define  CAN_TSR_ALST1                       ((uint32_t)0x00000400)        </span>
<a name="l01632"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga9b01eca562bdb60e5416840fca47fff6">01632</a> <span class="preprocessor">#define  CAN_TSR_TERR1                       ((uint32_t)0x00000800)        </span>
<a name="l01633"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga4c44a4e585b3ab1c37a6c2c28c90d6cd">01633</a> <span class="preprocessor">#define  CAN_TSR_ABRQ1                       ((uint32_t)0x00008000)        </span>
<a name="l01634"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga3cf9e83cec96164f1dadf4e43411ebf0">01634</a> <span class="preprocessor">#define  CAN_TSR_RQCP2                       ((uint32_t)0x00010000)        </span>
<a name="l01635"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga782c591bb204d751b470dd53a37d240e">01635</a> <span class="preprocessor">#define  CAN_TSR_TXOK2                       ((uint32_t)0x00020000)        </span>
<a name="l01636"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga75db1172038ebd72db1ed2fedc6108ff">01636</a> <span class="preprocessor">#define  CAN_TSR_ALST2                       ((uint32_t)0x00040000)        </span>
<a name="l01637"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga26a85626eb26bf99413ba80c676d0af8">01637</a> <span class="preprocessor">#define  CAN_TSR_TERR2                       ((uint32_t)0x00080000)        </span>
<a name="l01638"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga2a3b7e4be7cebb35ad66cb85b82901bb">01638</a> <span class="preprocessor">#define  CAN_TSR_ABRQ2                       ((uint32_t)0x00800000)        </span>
<a name="l01639"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gac00145ea43822f362f3d473bba62fa13">01639</a> <span class="preprocessor">#define  CAN_TSR_CODE                        ((uint32_t)0x03000000)        </span>
<a name="l01641"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga61ab11e97b42c5210109516e30af9b05">01641</a> <span class="preprocessor">#define  CAN_TSR_TME                         ((uint32_t)0x1C000000)        </span>
<a name="l01642"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gad7500e491fe82e67ed5d40759e8a50f0">01642</a> <span class="preprocessor">#define  CAN_TSR_TME0                        ((uint32_t)0x04000000)        </span>
<a name="l01643"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga5ba2b51def4b1683fd050e43045306ea">01643</a> <span class="preprocessor">#define  CAN_TSR_TME1                        ((uint32_t)0x08000000)        </span>
<a name="l01644"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaf6523fac51d3aed2e36de4c2f07c2a21">01644</a> <span class="preprocessor">#define  CAN_TSR_TME2                        ((uint32_t)0x10000000)        </span>
<a name="l01646"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga96c6453caa447cc4a9961d6ee5dea74e">01646</a> <span class="preprocessor">#define  CAN_TSR_LOW                         ((uint32_t)0xE0000000)        </span>
<a name="l01647"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga79ff582efea1d7be2d1de7a1fd1a2b65">01647</a> <span class="preprocessor">#define  CAN_TSR_LOW0                        ((uint32_t)0x20000000)        </span>
<a name="l01648"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gac1e550c2e6a5f8425322f9943fd7c7ed">01648</a> <span class="preprocessor">#define  CAN_TSR_LOW1                        ((uint32_t)0x40000000)        </span>
<a name="l01649"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gadd1db2c2ce76b732fdb71df65fb8124f">01649</a> <span class="preprocessor">#define  CAN_TSR_LOW2                        ((uint32_t)0x80000000)        </span>
<a name="l01651"></a>01651 <span class="preprocessor"></span><span class="comment">/*******************  Bit definition for CAN_RF0R register  *******************/</span>
<a name="l01652"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga9e23f3d7947e58531524d77b5c4741cc">01652</a> <span class="preprocessor">#define  CAN_RF0R_FMP0                       ((uint8_t)0x03)               </span>
<a name="l01653"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gae934674f6e22a758e430f32cfc386d70">01653</a> <span class="preprocessor">#define  CAN_RF0R_FULL0                      ((uint8_t)0x08)               </span>
<a name="l01654"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga2a3d15b3abab8199c16e26a3dffdc8b8">01654</a> <span class="preprocessor">#define  CAN_RF0R_FOVR0                      ((uint8_t)0x10)               </span>
<a name="l01655"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga74d2db4b9b7d52712e47557dcc61964d">01655</a> <span class="preprocessor">#define  CAN_RF0R_RFOM0                      ((uint8_t)0x20)               </span>
<a name="l01657"></a>01657 <span class="preprocessor"></span><span class="comment">/*******************  Bit definition for CAN_RF1R register  *******************/</span>
<a name="l01658"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga8f9254d05043df6f21bf96234a03f72f">01658</a> <span class="preprocessor">#define  CAN_RF1R_FMP1                       ((uint8_t)0x03)               </span>
<a name="l01659"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gabdaa12fe4d14254cc4a6a4de749a7d0a">01659</a> <span class="preprocessor">#define  CAN_RF1R_FULL1                      ((uint8_t)0x08)               </span>
<a name="l01660"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gab5eeaabd4db3825bc53d860aca8d7590">01660</a> <span class="preprocessor">#define  CAN_RF1R_FOVR1                      ((uint8_t)0x10)               </span>
<a name="l01661"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga6930f860de4a90e3344e63fbc209b9ab">01661</a> <span class="preprocessor">#define  CAN_RF1R_RFOM1                      ((uint8_t)0x20)               </span>
<a name="l01663"></a>01663 <span class="preprocessor"></span><span class="comment">/********************  Bit definition for CAN_IER register  *******************/</span>
<a name="l01664"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gafe027af7acd051f5a52db78608a36e26">01664</a> <span class="preprocessor">#define  CAN_IER_TMEIE                       ((uint32_t)0x00000001)        </span>
<a name="l01665"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga59eecd1bb7d1d0e17422a26ae89cf39d">01665</a> <span class="preprocessor">#define  CAN_IER_FMPIE0                      ((uint32_t)0x00000002)        </span>
<a name="l01666"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaf926ae29d98a8b72ef48f001fda07fc3">01666</a> <span class="preprocessor">#define  CAN_IER_FFIE0                       ((uint32_t)0x00000004)        </span>
<a name="l01667"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga0c423699fdcd2ddddb3046a368505679">01667</a> <span class="preprocessor">#define  CAN_IER_FOVIE0                      ((uint32_t)0x00000008)        </span>
<a name="l01668"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga4b8492d1b8ce13fead7869a0e4ef39ed">01668</a> <span class="preprocessor">#define  CAN_IER_FMPIE1                      ((uint32_t)0x00000010)        </span>
<a name="l01669"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaf5a7e9d13e8d96bef2ac1972520b1c4f">01669</a> <span class="preprocessor">#define  CAN_IER_FFIE1                       ((uint32_t)0x00000020)        </span>
<a name="l01670"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga3734d9bf5cd08ff219b2d8c2f8300dbf">01670</a> <span class="preprocessor">#define  CAN_IER_FOVIE1                      ((uint32_t)0x00000040)        </span>
<a name="l01671"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaa80103eca53d74a2b047f761336918e3">01671</a> <span class="preprocessor">#define  CAN_IER_EWGIE                       ((uint32_t)0x00000100)        </span>
<a name="l01672"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga9e3307992cabee858287305a64e5031b">01672</a> <span class="preprocessor">#define  CAN_IER_EPVIE                       ((uint32_t)0x00000200)        </span>
<a name="l01673"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga7d953fd5b625af04f95f5414259769ef">01673</a> <span class="preprocessor">#define  CAN_IER_BOFIE                       ((uint32_t)0x00000400)        </span>
<a name="l01674"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga81514ecf1b6596e9930906779c4bdf39">01674</a> <span class="preprocessor">#define  CAN_IER_LECIE                       ((uint32_t)0x00000800)        </span>
<a name="l01675"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga962968c3ee1f70c714a5b12442369d9a">01675</a> <span class="preprocessor">#define  CAN_IER_ERRIE                       ((uint32_t)0x00008000)        </span>
<a name="l01676"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga37f3438e80288c1791de27042df9838e">01676</a> <span class="preprocessor">#define  CAN_IER_WKUIE                       ((uint32_t)0x00010000)        </span>
<a name="l01677"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga82389b79f21410f5d5f6bef38d192812">01677</a> <span class="preprocessor">#define  CAN_IER_SLKIE                       ((uint32_t)0x00020000)        </span>
<a name="l01679"></a>01679 <span class="preprocessor"></span><span class="comment">/********************  Bit definition for CAN_ESR register  *******************/</span>
<a name="l01680"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga2c0c02829fb41ac2a1b1852c19931de8">01680</a> <span class="preprocessor">#define  CAN_ESR_EWGF                        ((uint32_t)0x00000001)        </span>
<a name="l01681"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga633c961d528cbf8093b0e05e92225ff0">01681</a> <span class="preprocessor">#define  CAN_ESR_EPVF                        ((uint32_t)0x00000002)        </span>
<a name="l01682"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga619d49f67f1835a7efc457205fea1225">01682</a> <span class="preprocessor">#define  CAN_ESR_BOFF                        ((uint32_t)0x00000004)        </span>
<a name="l01684"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gab9f86741dd89034900e300499ae2272e">01684</a> <span class="preprocessor">#define  CAN_ESR_LEC                         ((uint32_t)0x00000070)        </span>
<a name="l01685"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga054ebb41578d890d4d9dffb4828f02e7">01685</a> <span class="preprocessor">#define  CAN_ESR_LEC_0                       ((uint32_t)0x00000010)        </span>
<a name="l01686"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gae570e9ba39dbe11808db929392250cf4">01686</a> <span class="preprocessor">#define  CAN_ESR_LEC_1                       ((uint32_t)0x00000020)        </span>
<a name="l01687"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga4998e7bfd002999413c68107911c6e8c">01687</a> <span class="preprocessor">#define  CAN_ESR_LEC_2                       ((uint32_t)0x00000040)        </span>
<a name="l01689"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gae3de2080f48cc851c20d920acfd1737d">01689</a> <span class="preprocessor">#define  CAN_ESR_TEC                         ((uint32_t)0x00FF0000)        </span>
<a name="l01690"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga0df5b2ea3f419182e9bd885f55ee5dc9">01690</a> <span class="preprocessor">#define  CAN_ESR_REC                         ((uint32_t)0xFF000000)        </span>
<a name="l01692"></a>01692 <span class="preprocessor"></span><span class="comment">/*******************  Bit definition for CAN_BTR register  ********************/</span>
<a name="l01693"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga96a5522b4c06551856f7185bdd448b02">01693</a> <span class="preprocessor">#define  CAN_BTR_BRP                         ((uint32_t)0x000003FF)        </span>
<a name="l01694"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga4d7ae8f06f8fbbf5dcfbbbb887057be9">01694</a> <span class="preprocessor">#define  CAN_BTR_TS1                         ((uint32_t)0x000F0000)        </span>
<a name="l01695"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gac006aa2ab26c50227ccaa18e0a79bff3">01695</a> <span class="preprocessor">#define  CAN_BTR_TS2                         ((uint32_t)0x00700000)        </span>
<a name="l01696"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga04c8b91ddacdcbb779bae42398c94cf2">01696</a> <span class="preprocessor">#define  CAN_BTR_SJW                         ((uint32_t)0x03000000)        </span>
<a name="l01697"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gac6c0a81d8dcde61a1f2772232f5343b8">01697</a> <span class="preprocessor">#define  CAN_BTR_LBKM                        ((uint32_t)0x40000000)        </span>
<a name="l01698"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaa36bc23e833190cbee9b8cf5cf49159d">01698</a> <span class="preprocessor">#define  CAN_BTR_SILM                        ((uint32_t)0x80000000)        </span>
<a name="l01701"></a>01701 <span class="preprocessor"></span><span class="comment">/******************  Bit definition for CAN_TI0R register  ********************/</span>
<a name="l01702"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga7b79cbb7ebb7f3419aa6ac04bd76899a">01702</a> <span class="preprocessor">#define  CAN_TI0R_TXRQ                       ((uint32_t)0x00000001)        </span>
<a name="l01703"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gad5556f2ceb5b71b8afa76a18a31cbb6a">01703</a> <span class="preprocessor">#define  CAN_TI0R_RTR                        ((uint32_t)0x00000002)        </span>
<a name="l01704"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga06f761a877f8ad39f878284f69119c0b">01704</a> <span class="preprocessor">#define  CAN_TI0R_IDE                        ((uint32_t)0x00000004)        </span>
<a name="l01705"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga894df6ad0d2976fe643dcb77052672f5">01705</a> <span class="preprocessor">#define  CAN_TI0R_EXID                       ((uint32_t)0x001FFFF8)        </span>
<a name="l01706"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga4d3b5882e1f9f76f5cfebffb5bc2f717">01706</a> <span class="preprocessor">#define  CAN_TI0R_STID                       ((uint32_t)0xFFE00000)        </span>
<a name="l01708"></a>01708 <span class="preprocessor"></span><span class="comment">/******************  Bit definition for CAN_TDT0R register  *******************/</span>
<a name="l01709"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gacf812eaee11f12863773b3f8e95ae6e2">01709</a> <span class="preprocessor">#define  CAN_TDT0R_DLC                       ((uint32_t)0x0000000F)        </span>
<a name="l01710"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gad2d329960b527a62fab099a084bfa906">01710</a> <span class="preprocessor">#define  CAN_TDT0R_TGT                       ((uint32_t)0x00000100)        </span>
<a name="l01711"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga104ba91151bf88edd44593b1690b879a">01711</a> <span class="preprocessor">#define  CAN_TDT0R_TIME                      ((uint32_t)0xFFFF0000)        </span>
<a name="l01713"></a>01713 <span class="preprocessor"></span><span class="comment">/******************  Bit definition for CAN_TDL0R register  *******************/</span>
<a name="l01714"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gadec3350607b41410ddb6e00a71a4384e">01714</a> <span class="preprocessor">#define  CAN_TDL0R_DATA0                     ((uint32_t)0x000000FF)        </span>
<a name="l01715"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga1cd20d218027e7432178c67414475830">01715</a> <span class="preprocessor">#define  CAN_TDL0R_DATA1                     ((uint32_t)0x0000FF00)        </span>
<a name="l01716"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaa04384f0a7c5026c91a33a005c755d68">01716</a> <span class="preprocessor">#define  CAN_TDL0R_DATA2                     ((uint32_t)0x00FF0000)        </span>
<a name="l01717"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga283a1bfa52851ea4ee45f45817985752">01717</a> <span class="preprocessor">#define  CAN_TDL0R_DATA3                     ((uint32_t)0xFF000000)        </span>
<a name="l01719"></a>01719 <span class="preprocessor"></span><span class="comment">/******************  Bit definition for CAN_TDH0R register  *******************/</span>
<a name="l01720"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga0114ae75b33f978ca7825f7bcd836982">01720</a> <span class="preprocessor">#define  CAN_TDH0R_DATA4                     ((uint32_t)0x000000FF)        </span>
<a name="l01721"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaf5b6a0742ac1bcd5ef0408cb0f92ef75">01721</a> <span class="preprocessor">#define  CAN_TDH0R_DATA5                     ((uint32_t)0x0000FF00)        </span>
<a name="l01722"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gac8ea7090da55c7cc9993235efa1c4a02">01722</a> <span class="preprocessor">#define  CAN_TDH0R_DATA6                     ((uint32_t)0x00FF0000)        </span>
<a name="l01723"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga6021a4045fbfd71817bf9aec6cbc731c">01723</a> <span class="preprocessor">#define  CAN_TDH0R_DATA7                     ((uint32_t)0xFF000000)        </span>
<a name="l01725"></a>01725 <span class="preprocessor"></span><span class="comment">/*******************  Bit definition for CAN_TI1R register  *******************/</span>
<a name="l01726"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga0adf4a08415673753fafedf463f93bee">01726</a> <span class="preprocessor">#define  CAN_TI1R_TXRQ                       ((uint32_t)0x00000001)        </span>
<a name="l01727"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga476cde56b1a2a13cde8477d5178ba34b">01727</a> <span class="preprocessor">#define  CAN_TI1R_RTR                        ((uint32_t)0x00000002)        </span>
<a name="l01728"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga8f338f3e295b7b512ed865b3f9a8d6de">01728</a> <span class="preprocessor">#define  CAN_TI1R_IDE                        ((uint32_t)0x00000004)        </span>
<a name="l01729"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga6c660943fa3c70c4974c2dacd3e4ca2e">01729</a> <span class="preprocessor">#define  CAN_TI1R_EXID                       ((uint32_t)0x001FFFF8)        </span>
<a name="l01730"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga842071768c2f8f5eae11a764a77dd0dd">01730</a> <span class="preprocessor">#define  CAN_TI1R_STID                       ((uint32_t)0xFFE00000)        </span>
<a name="l01732"></a>01732 <span class="preprocessor"></span><span class="comment">/*******************  Bit definition for CAN_TDT1R register  ******************/</span>
<a name="l01733"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga68ef8b6cb43a80d29c5fc318a67acd3b">01733</a> <span class="preprocessor">#define  CAN_TDT1R_DLC                       ((uint32_t)0x0000000F)        </span>
<a name="l01734"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga35757787e6481553885fdf4fd2738c4b">01734</a> <span class="preprocessor">#define  CAN_TDT1R_TGT                       ((uint32_t)0x00000100)        </span>
<a name="l01735"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gad28ac334a59a6679c362611d65666910">01735</a> <span class="preprocessor">#define  CAN_TDT1R_TIME                      ((uint32_t)0xFFFF0000)        </span>
<a name="l01737"></a>01737 <span class="preprocessor"></span><span class="comment">/*******************  Bit definition for CAN_TDL1R register  ******************/</span>
<a name="l01738"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga21abc05257bcdfa47fc824b4d806a105">01738</a> <span class="preprocessor">#define  CAN_TDL1R_DATA0                     ((uint32_t)0x000000FF)        </span>
<a name="l01739"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga0bf459dee1be706b38141722be67e4ab">01739</a> <span class="preprocessor">#define  CAN_TDL1R_DATA1                     ((uint32_t)0x0000FF00)        </span>
<a name="l01740"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaeb92a65c225432fab0daa30808d5065c">01740</a> <span class="preprocessor">#define  CAN_TDL1R_DATA2                     ((uint32_t)0x00FF0000)        </span>
<a name="l01741"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga482506faa59360c6a48aa9bc55a024c4">01741</a> <span class="preprocessor">#define  CAN_TDL1R_DATA3                     ((uint32_t)0xFF000000)        </span>
<a name="l01743"></a>01743 <span class="preprocessor"></span><span class="comment">/*******************  Bit definition for CAN_TDH1R register  ******************/</span>
<a name="l01744"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga41c3f19eea0d63211f643833da984c90">01744</a> <span class="preprocessor">#define  CAN_TDH1R_DATA4                     ((uint32_t)0x000000FF)        </span>
<a name="l01745"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga35cbe73d2ce87b6aaf19510818610d16">01745</a> <span class="preprocessor">#define  CAN_TDH1R_DATA5                     ((uint32_t)0x0000FF00)        </span>
<a name="l01746"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga1b731ca095cbad8e56ba4147c14d7128">01746</a> <span class="preprocessor">#define  CAN_TDH1R_DATA6                     ((uint32_t)0x00FF0000)        </span>
<a name="l01747"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaec56ce4aba46e836d44e2c034a9ed817">01747</a> <span class="preprocessor">#define  CAN_TDH1R_DATA7                     ((uint32_t)0xFF000000)        </span>
<a name="l01749"></a>01749 <span class="preprocessor"></span><span class="comment">/*******************  Bit definition for CAN_TI2R register  *******************/</span>
<a name="l01750"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gab4edd8438a684e353c497f80cb37365f">01750</a> <span class="preprocessor">#define  CAN_TI2R_TXRQ                       ((uint32_t)0x00000001)        </span>
<a name="l01751"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga980cfab3daebb05da35b6166a051385d">01751</a> <span class="preprocessor">#define  CAN_TI2R_RTR                        ((uint32_t)0x00000002)        </span>
<a name="l01752"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gac1d888a2225c77452f73bf66fb0e1b78">01752</a> <span class="preprocessor">#define  CAN_TI2R_IDE                        ((uint32_t)0x00000004)        </span>
<a name="l01753"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gae62678bd1dc39aae5a153e9c9b3c3f3b">01753</a> <span class="preprocessor">#define  CAN_TI2R_EXID                       ((uint32_t)0x001FFFF8)        </span>
<a name="l01754"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga41c8bd734dd29caa40d34ced3981443a">01754</a> <span class="preprocessor">#define  CAN_TI2R_STID                       ((uint32_t)0xFFE00000)        </span>
<a name="l01756"></a>01756 <span class="preprocessor"></span><span class="comment">/*******************  Bit definition for CAN_TDT2R register  ******************/</span>  
<a name="l01757"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga52898eb9fa3bcf0b8086220971af49f5">01757</a> <span class="preprocessor">#define  CAN_TDT2R_DLC                       ((uint32_t)0x0000000F)        </span>
<a name="l01758"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga4c51b43d309b56e8a64724ef1517033e">01758</a> <span class="preprocessor">#define  CAN_TDT2R_TGT                       ((uint32_t)0x00000100)        </span>
<a name="l01759"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga508aea584f7c81700b485916a13431fa">01759</a> <span class="preprocessor">#define  CAN_TDT2R_TIME                      ((uint32_t)0xFFFF0000)        </span>
<a name="l01761"></a>01761 <span class="preprocessor"></span><span class="comment">/*******************  Bit definition for CAN_TDL2R register  ******************/</span>
<a name="l01762"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga7a9852d0f6058c19f0e678228ea14a21">01762</a> <span class="preprocessor">#define  CAN_TDL2R_DATA0                     ((uint32_t)0x000000FF)        </span>
<a name="l01763"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gad5be1bcda68f562be669184b30727be1">01763</a> <span class="preprocessor">#define  CAN_TDL2R_DATA1                     ((uint32_t)0x0000FF00)        </span>
<a name="l01764"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga62cd5e7f3e98fe5b247998d39ebdd6fb">01764</a> <span class="preprocessor">#define  CAN_TDL2R_DATA2                     ((uint32_t)0x00FF0000)        </span>
<a name="l01765"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga3d76ed3982f13fb34a54d62f0caa3fa2">01765</a> <span class="preprocessor">#define  CAN_TDL2R_DATA3                     ((uint32_t)0xFF000000)        </span>
<a name="l01767"></a>01767 <span class="preprocessor"></span><span class="comment">/*******************  Bit definition for CAN_TDH2R register  ******************/</span>
<a name="l01768"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga23a93a13da2f302ecd2f0c462065428d">01768</a> <span class="preprocessor">#define  CAN_TDH2R_DATA4                     ((uint32_t)0x000000FF)        </span>
<a name="l01769"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gab9f372328c8d1e4fe2503d45aed50fb6">01769</a> <span class="preprocessor">#define  CAN_TDH2R_DATA5                     ((uint32_t)0x0000FF00)        </span>
<a name="l01770"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gae96248bcf102a3c6f39f72cdcf8e4fe5">01770</a> <span class="preprocessor">#define  CAN_TDH2R_DATA6                     ((uint32_t)0x00FF0000)        </span>
<a name="l01771"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga895341b943e4b01938857b84a0b0dbda">01771</a> <span class="preprocessor">#define  CAN_TDH2R_DATA7                     ((uint32_t)0xFF000000)        </span>
<a name="l01773"></a>01773 <span class="preprocessor"></span><span class="comment">/*******************  Bit definition for CAN_RI0R register  *******************/</span>
<a name="l01774"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga41f4780b822a42834bf1927eb92b4fba">01774</a> <span class="preprocessor">#define  CAN_RI0R_RTR                        ((uint32_t)0x00000002)        </span>
<a name="l01775"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga688074182caafff289c921548bc9afca">01775</a> <span class="preprocessor">#define  CAN_RI0R_IDE                        ((uint32_t)0x00000004)        </span>
<a name="l01776"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga4d81487e8b340810e3193cd8f1386240">01776</a> <span class="preprocessor">#define  CAN_RI0R_EXID                       ((uint32_t)0x001FFFF8)        </span>
<a name="l01777"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga101aa355c83b8c7d068f02b7dcc5b98f">01777</a> <span class="preprocessor">#define  CAN_RI0R_STID                       ((uint32_t)0xFFE00000)        </span>
<a name="l01779"></a>01779 <span class="preprocessor"></span><span class="comment">/*******************  Bit definition for CAN_RDT0R register  ******************/</span>
<a name="l01780"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga17ca0af4afd89e6a1c43ffd1430359b7">01780</a> <span class="preprocessor">#define  CAN_RDT0R_DLC                       ((uint32_t)0x0000000F)        </span>
<a name="l01781"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga5081739b6e21e033b95e68af9331a6d1">01781</a> <span class="preprocessor">#define  CAN_RDT0R_FMI                       ((uint32_t)0x0000FF00)        </span>
<a name="l01782"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gae20b7a72690033591eeda7a511ac4a2e">01782</a> <span class="preprocessor">#define  CAN_RDT0R_TIME                      ((uint32_t)0xFFFF0000)        </span>
<a name="l01784"></a>01784 <span class="preprocessor"></span><span class="comment">/*******************  Bit definition for CAN_RDL0R register  ******************/</span>
<a name="l01785"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga44313106efc3a5a65633168a2ad1928d">01785</a> <span class="preprocessor">#define  CAN_RDL0R_DATA0                     ((uint32_t)0x000000FF)        </span>
<a name="l01786"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga73d4025ce501af78db93761e8b8c3b9e">01786</a> <span class="preprocessor">#define  CAN_RDL0R_DATA1                     ((uint32_t)0x0000FF00)        </span>
<a name="l01787"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga52b3c31ad72881e11a4d3cae073a0df8">01787</a> <span class="preprocessor">#define  CAN_RDL0R_DATA2                     ((uint32_t)0x00FF0000)        </span>
<a name="l01788"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gad637a53ae780998f95f2bb570d5cd05a">01788</a> <span class="preprocessor">#define  CAN_RDL0R_DATA3                     ((uint32_t)0xFF000000)        </span>
<a name="l01790"></a>01790 <span class="preprocessor"></span><span class="comment">/*******************  Bit definition for CAN_RDH0R register  ******************/</span>
<a name="l01791"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga4dc7309c31cda93d05bb1fe1c923646c">01791</a> <span class="preprocessor">#define  CAN_RDH0R_DATA4                     ((uint32_t)0x000000FF)        </span>
<a name="l01792"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga577eba5ab3a66283f5c0837e91f1776a">01792</a> <span class="preprocessor">#define  CAN_RDH0R_DATA5                     ((uint32_t)0x0000FF00)        </span>
<a name="l01793"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga27a0bd49dc24e59b776ad5a00aabb97b">01793</a> <span class="preprocessor">#define  CAN_RDH0R_DATA6                     ((uint32_t)0x00FF0000)        </span>
<a name="l01794"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga243b8a3632812b2f8c7b447ed635ce5f">01794</a> <span class="preprocessor">#define  CAN_RDH0R_DATA7                     ((uint32_t)0xFF000000)        </span>
<a name="l01796"></a>01796 <span class="preprocessor"></span><span class="comment">/*******************  Bit definition for CAN_RI1R register  *******************/</span>
<a name="l01797"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gafbd0ecd9579a339bffb95ea3b7c9f1e8">01797</a> <span class="preprocessor">#define  CAN_RI1R_RTR                        ((uint32_t)0x00000002)        </span>
<a name="l01798"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga8dcedeb4250767a66a4d60c67e367cf8">01798</a> <span class="preprocessor">#define  CAN_RI1R_IDE                        ((uint32_t)0x00000004)        </span>
<a name="l01799"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga2ca45b282f2582c91450d4e1204121cf">01799</a> <span class="preprocessor">#define  CAN_RI1R_EXID                       ((uint32_t)0x001FFFF8)        </span>
<a name="l01800"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga7f3c3aab0f24533821188d14901b3980">01800</a> <span class="preprocessor">#define  CAN_RI1R_STID                       ((uint32_t)0xFFE00000)        </span>
<a name="l01802"></a>01802 <span class="preprocessor"></span><span class="comment">/*******************  Bit definition for CAN_RDT1R register  ******************/</span>
<a name="l01803"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga964b0fa7c70a24a74165c57b3486aae8">01803</a> <span class="preprocessor">#define  CAN_RDT1R_DLC                       ((uint32_t)0x0000000F)        </span>
<a name="l01804"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaf7f72aec91130a20e3a855e78eabb48b">01804</a> <span class="preprocessor">#define  CAN_RDT1R_FMI                       ((uint32_t)0x0000FF00)        </span>
<a name="l01805"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gac112cba5a4cd0b541c1150263132c68a">01805</a> <span class="preprocessor">#define  CAN_RDT1R_TIME                      ((uint32_t)0xFFFF0000)        </span>
<a name="l01807"></a>01807 <span class="preprocessor"></span><span class="comment">/*******************  Bit definition for CAN_RDL1R register  ******************/</span>
<a name="l01808"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga1e399fed282a5aac0b25b059fcf04020">01808</a> <span class="preprocessor">#define  CAN_RDL1R_DATA0                     ((uint32_t)0x000000FF)        </span>
<a name="l01809"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga27ec34e08f87e8836f32bbfed52e860a">01809</a> <span class="preprocessor">#define  CAN_RDL1R_DATA1                     ((uint32_t)0x0000FF00)        </span>
<a name="l01810"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaea34eded40932d364743969643a598c4">01810</a> <span class="preprocessor">#define  CAN_RDL1R_DATA2                     ((uint32_t)0x00FF0000)        </span>
<a name="l01811"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga80bfe3e724b28e8d2a5b7ac4393212cf">01811</a> <span class="preprocessor">#define  CAN_RDL1R_DATA3                     ((uint32_t)0xFF000000)        </span>
<a name="l01813"></a>01813 <span class="preprocessor"></span><span class="comment">/*******************  Bit definition for CAN_RDH1R register  ******************/</span>
<a name="l01814"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gafc2a55c1b5195cf043ef33e79d736255">01814</a> <span class="preprocessor">#define  CAN_RDH1R_DATA4                     ((uint32_t)0x000000FF)        </span>
<a name="l01815"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga81d25a1ea5ad28e7db4a2adbb8a651ad">01815</a> <span class="preprocessor">#define  CAN_RDH1R_DATA5                     ((uint32_t)0x0000FF00)        </span>
<a name="l01816"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga39212ea40388510bde1931f7b3a064ae">01816</a> <span class="preprocessor">#define  CAN_RDH1R_DATA6                     ((uint32_t)0x00FF0000)        </span>
<a name="l01817"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gafdfbb90b5ef2ac1e7f23a5f15c0287eb">01817</a> <span class="preprocessor">#define  CAN_RDH1R_DATA7                     ((uint32_t)0xFF000000)        </span>
<a name="l01820"></a>01820 <span class="preprocessor"></span><span class="comment">/*******************  Bit definition for CAN_FMR register  ********************/</span>
<a name="l01821"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga5eb5b835ee11a78bd391b9d1049f2549">01821</a> <span class="preprocessor">#define  CAN_FMR_FINIT                       ((uint8_t)0x01)               </span>
<a name="l01823"></a>01823 <span class="preprocessor"></span><span class="comment">/*******************  Bit definition for CAN_FM1R register  *******************/</span>
<a name="l01824"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga481099e17a895e92cfbcfca617d52860">01824</a> <span class="preprocessor">#define  CAN_FM1R_FBM                        ((uint16_t)0x3FFF)            </span>
<a name="l01825"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga2d95ff05ed6ef9a38e9af9c0d3db3687">01825</a> <span class="preprocessor">#define  CAN_FM1R_FBM0                       ((uint16_t)0x0001)            </span>
<a name="l01826"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gac2839d73344a7601aa22b5ed3fc0e5d1">01826</a> <span class="preprocessor">#define  CAN_FM1R_FBM1                       ((uint16_t)0x0002)            </span>
<a name="l01827"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga7ba7963ac4eb5b936c444258c13f8940">01827</a> <span class="preprocessor">#define  CAN_FM1R_FBM2                       ((uint16_t)0x0004)            </span>
<a name="l01828"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga2d129b27c2af41ae39e606e802a53386">01828</a> <span class="preprocessor">#define  CAN_FM1R_FBM3                       ((uint16_t)0x0008)            </span>
<a name="l01829"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaf0c94e5f4dcceea510fc72b86128aff3">01829</a> <span class="preprocessor">#define  CAN_FM1R_FBM4                       ((uint16_t)0x0010)            </span>
<a name="l01830"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga2d7fb7c366544a1ef7a85481d3e6325d">01830</a> <span class="preprocessor">#define  CAN_FM1R_FBM5                       ((uint16_t)0x0020)            </span>
<a name="l01831"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga3ff70e74447679a0d1cde1aa69ea2db1">01831</a> <span class="preprocessor">#define  CAN_FM1R_FBM6                       ((uint16_t)0x0040)            </span>
<a name="l01832"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga657fc12fd334bc626b2eb53fb03457b0">01832</a> <span class="preprocessor">#define  CAN_FM1R_FBM7                       ((uint16_t)0x0080)            </span>
<a name="l01833"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gab6bc390ed9a658014fd09fd1073e3037">01833</a> <span class="preprocessor">#define  CAN_FM1R_FBM8                       ((uint16_t)0x0100)            </span>
<a name="l01834"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga375758246b99234dda725b7c64daff32">01834</a> <span class="preprocessor">#define  CAN_FM1R_FBM9                       ((uint16_t)0x0200)            </span>
<a name="l01835"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga0a98c6bde07c570463b6c0e32c0f6805">01835</a> <span class="preprocessor">#define  CAN_FM1R_FBM10                      ((uint16_t)0x0400)            </span>
<a name="l01836"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gab88796333c19954176ef77208cae4964">01836</a> <span class="preprocessor">#define  CAN_FM1R_FBM11                      ((uint16_t)0x0800)            </span>
<a name="l01837"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga858eaac0a8e23c03e13e5c1736bf9842">01837</a> <span class="preprocessor">#define  CAN_FM1R_FBM12                      ((uint16_t)0x1000)            </span>
<a name="l01838"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaf03b553802edd3ae23b70e97228b6dcc">01838</a> <span class="preprocessor">#define  CAN_FM1R_FBM13                      ((uint16_t)0x2000)            </span>
<a name="l01840"></a>01840 <span class="preprocessor"></span><span class="comment">/*******************  Bit definition for CAN_FS1R register  *******************/</span>
<a name="l01841"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gab41471f35878bcdff72d9cd05acf4714">01841</a> <span class="preprocessor">#define  CAN_FS1R_FSC                        ((uint16_t)0x3FFF)            </span>
<a name="l01842"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaab5ea9e0ed17df35894fff7828c89cad">01842</a> <span class="preprocessor">#define  CAN_FS1R_FSC0                       ((uint16_t)0x0001)            </span>
<a name="l01843"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga83304e93d2e75c1cd8bfe7c2ec30c1c8">01843</a> <span class="preprocessor">#define  CAN_FS1R_FSC1                       ((uint16_t)0x0002)            </span>
<a name="l01844"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga0ba1fa61fcf851188a6f16323dda1358">01844</a> <span class="preprocessor">#define  CAN_FS1R_FSC2                       ((uint16_t)0x0004)            </span>
<a name="l01845"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaf2175f52f4308c088458f9e54a1f1354">01845</a> <span class="preprocessor">#define  CAN_FS1R_FSC3                       ((uint16_t)0x0008)            </span>
<a name="l01846"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga791ac090d6a8f2c79cd72f9072aef30f">01846</a> <span class="preprocessor">#define  CAN_FS1R_FSC4                       ((uint16_t)0x0010)            </span>
<a name="l01847"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gadb4ef2030ec70a4635ca4ac38cca76cb">01847</a> <span class="preprocessor">#define  CAN_FS1R_FSC5                       ((uint16_t)0x0020)            </span>
<a name="l01848"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaf015be41f803007b9d0b2f3371e3621b">01848</a> <span class="preprocessor">#define  CAN_FS1R_FSC6                       ((uint16_t)0x0040)            </span>
<a name="l01849"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga206d175417e2c787b44b0734708a5c9a">01849</a> <span class="preprocessor">#define  CAN_FS1R_FSC7                       ((uint16_t)0x0080)            </span>
<a name="l01850"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga7209f008874dadf147cb5357ee46c226">01850</a> <span class="preprocessor">#define  CAN_FS1R_FSC8                       ((uint16_t)0x0100)            </span>
<a name="l01851"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga58b4d8fa56d898ad6bf66ba8a4e098eb">01851</a> <span class="preprocessor">#define  CAN_FS1R_FSC9                       ((uint16_t)0x0200)            </span>
<a name="l01852"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga93162a66091ffd4829ed8265f53fe977">01852</a> <span class="preprocessor">#define  CAN_FS1R_FSC10                      ((uint16_t)0x0400)            </span>
<a name="l01853"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaf2e0bf399ea9175123c95c7010ef527d">01853</a> <span class="preprocessor">#define  CAN_FS1R_FSC11                      ((uint16_t)0x0800)            </span>
<a name="l01854"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga89ea9e9c914052e2aecab16d57f2569d">01854</a> <span class="preprocessor">#define  CAN_FS1R_FSC12                      ((uint16_t)0x1000)            </span>
<a name="l01855"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaf2df1f2a554fc014529da34620739bc4">01855</a> <span class="preprocessor">#define  CAN_FS1R_FSC13                      ((uint16_t)0x2000)            </span>
<a name="l01857"></a>01857 <span class="preprocessor"></span><span class="comment">/******************  Bit definition for CAN_FFA1R register  *******************/</span>
<a name="l01858"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga16fa4bf13579d29b57f7602489d043fe">01858</a> <span class="preprocessor">#define  CAN_FFA1R_FFA                       ((uint16_t)0x3FFF)            </span>
<a name="l01859"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga4b1a0f95bac4fed1a801da0cdbf2a833">01859</a> <span class="preprocessor">#define  CAN_FFA1R_FFA0                      ((uint16_t)0x0001)            </span>
<a name="l01860"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaba35e135e17431de861e57b550421386">01860</a> <span class="preprocessor">#define  CAN_FFA1R_FFA1                      ((uint16_t)0x0002)            </span>
<a name="l01861"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga5b64393197f5cd0bd6e4853828a98065">01861</a> <span class="preprocessor">#define  CAN_FFA1R_FFA2                      ((uint16_t)0x0004)            </span>
<a name="l01862"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga111ce1e4500e2c0f543128dddbe941e9">01862</a> <span class="preprocessor">#define  CAN_FFA1R_FFA3                      ((uint16_t)0x0008)            </span>
<a name="l01863"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga8a824c777e7fea25f580bc313ed2ece6">01863</a> <span class="preprocessor">#define  CAN_FFA1R_FFA4                      ((uint16_t)0x0010)            </span>
<a name="l01864"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gabd571c9c746225e9b856ce3a46c3bb2f">01864</a> <span class="preprocessor">#define  CAN_FFA1R_FFA5                      ((uint16_t)0x0020)            </span>
<a name="l01865"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gab2afec157fe9684f1fa4b4401500f035">01865</a> <span class="preprocessor">#define  CAN_FFA1R_FFA6                      ((uint16_t)0x0040)            </span>
<a name="l01866"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga2d70e150cfd4866ea6b0a264ad45f51b">01866</a> <span class="preprocessor">#define  CAN_FFA1R_FFA7                      ((uint16_t)0x0080)            </span>
<a name="l01867"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gafa802583aa70aadeb46366ff98eccaf1">01867</a> <span class="preprocessor">#define  CAN_FFA1R_FFA8                      ((uint16_t)0x0100)            </span>
<a name="l01868"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga6ee7da4c7e42fa7576d965c4bf94c089">01868</a> <span class="preprocessor">#define  CAN_FFA1R_FFA9                      ((uint16_t)0x0200)            </span>
<a name="l01869"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga8ac0384eab9b0cfdb491a960279fc438">01869</a> <span class="preprocessor">#define  CAN_FFA1R_FFA10                     ((uint16_t)0x0400)            </span>
<a name="l01870"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaacd7e79ab503ec5143b5848edac71817">01870</a> <span class="preprocessor">#define  CAN_FFA1R_FFA11                     ((uint16_t)0x0800)            </span>
<a name="l01871"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga7873f1526050f5e666c22fb6a7e68b65">01871</a> <span class="preprocessor">#define  CAN_FFA1R_FFA12                     ((uint16_t)0x1000)            </span>
<a name="l01872"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gac74339b69a2e6f67df9b6e136089c0ee">01872</a> <span class="preprocessor">#define  CAN_FFA1R_FFA13                     ((uint16_t)0x2000)            </span>
<a name="l01874"></a>01874 <span class="preprocessor"></span><span class="comment">/*******************  Bit definition for CAN_FA1R register  *******************/</span>
<a name="l01875"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaa571445875b08a9514e1d1b410a93ebd">01875</a> <span class="preprocessor">#define  CAN_FA1R_FACT                       ((uint16_t)0x3FFF)            </span>
<a name="l01876"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gab3ec1e2f9b9ccf2b4869cdf7c7328e60">01876</a> <span class="preprocessor">#define  CAN_FA1R_FACT0                      ((uint16_t)0x0001)            </span>
<a name="l01877"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga2457026460aecb52dba7ea17237b4dbe">01877</a> <span class="preprocessor">#define  CAN_FA1R_FACT1                      ((uint16_t)0x0002)            </span>
<a name="l01878"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga66354c26d0252cc86729365b315a69ee">01878</a> <span class="preprocessor">#define  CAN_FA1R_FACT2                      ((uint16_t)0x0004)            </span>
<a name="l01879"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga087dc5f2bdfe084eb98d2a0d06a29f1d">01879</a> <span class="preprocessor">#define  CAN_FA1R_FACT3                      ((uint16_t)0x0008)            </span>
<a name="l01880"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga6c46367b7e5ea831e34ba4cf824a63da">01880</a> <span class="preprocessor">#define  CAN_FA1R_FACT4                      ((uint16_t)0x0010)            </span>
<a name="l01881"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga548238c7babf34116fdb44b4575e2664">01881</a> <span class="preprocessor">#define  CAN_FA1R_FACT5                      ((uint16_t)0x0020)            </span>
<a name="l01882"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gae403370a70f9ea2b6f9b449cafa6a91c">01882</a> <span class="preprocessor">#define  CAN_FA1R_FACT6                      ((uint16_t)0x0040)            </span>
<a name="l01883"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga33e9f4334cf3bf9e7e30d5edf278a02b">01883</a> <span class="preprocessor">#define  CAN_FA1R_FACT7                      ((uint16_t)0x0080)            </span>
<a name="l01884"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga0ccbdd2932828bfa1d68777cb595f12e">01884</a> <span class="preprocessor">#define  CAN_FA1R_FACT8                      ((uint16_t)0x0100)            </span>
<a name="l01885"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaf8e4011791e551feeae33c47ef2b6a6a">01885</a> <span class="preprocessor">#define  CAN_FA1R_FACT9                      ((uint16_t)0x0200)            </span>
<a name="l01886"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga19696d8b702b33eafe7f18aa0c6c1955">01886</a> <span class="preprocessor">#define  CAN_FA1R_FACT10                     ((uint16_t)0x0400)            </span>
<a name="l01887"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga89e5e3ccd4250ad2360b91ef51248a66">01887</a> <span class="preprocessor">#define  CAN_FA1R_FACT11                     ((uint16_t)0x0800)            </span>
<a name="l01888"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gae78ec392640f05b20a7c6877983588ae">01888</a> <span class="preprocessor">#define  CAN_FA1R_FACT12                     ((uint16_t)0x1000)            </span>
<a name="l01889"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaa722eeef87f8a3f58ebfcb531645cc05">01889</a> <span class="preprocessor">#define  CAN_FA1R_FACT13                     ((uint16_t)0x2000)            </span>
<a name="l01891"></a>01891 <span class="preprocessor"></span><span class="comment">/*******************  Bit definition for CAN_F0R1 register  *******************/</span>
<a name="l01892"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga38014ea45b62975627f8e222390f6819">01892</a> <span class="preprocessor">#define  CAN_F0R1_FB0                        ((uint32_t)0x00000001)        </span>
<a name="l01893"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga9e01c05df79304035c7aab1c7295bf3f">01893</a> <span class="preprocessor">#define  CAN_F0R1_FB1                        ((uint32_t)0x00000002)        </span>
<a name="l01894"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga083282146d4db7f757fef86cf302eded">01894</a> <span class="preprocessor">#define  CAN_F0R1_FB2                        ((uint32_t)0x00000004)        </span>
<a name="l01895"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gae4a1adc2e4e550a38649a2bfd3662680">01895</a> <span class="preprocessor">#define  CAN_F0R1_FB3                        ((uint32_t)0x00000008)        </span>
<a name="l01896"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaa0bfa15bf30fefb21f351228cde87981">01896</a> <span class="preprocessor">#define  CAN_F0R1_FB4                        ((uint32_t)0x00000010)        </span>
<a name="l01897"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga5381c154ba89611bf4381657305ecb85">01897</a> <span class="preprocessor">#define  CAN_F0R1_FB5                        ((uint32_t)0x00000020)        </span>
<a name="l01898"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gae224160853946732608f00ad008a6b1a">01898</a> <span class="preprocessor">#define  CAN_F0R1_FB6                        ((uint32_t)0x00000040)        </span>
<a name="l01899"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaa0c44034b5f42fa8250dbb8e46bc83eb">01899</a> <span class="preprocessor">#define  CAN_F0R1_FB7                        ((uint32_t)0x00000080)        </span>
<a name="l01900"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga465e092af3e73882f9eaffad13f36dea">01900</a> <span class="preprocessor">#define  CAN_F0R1_FB8                        ((uint32_t)0x00000100)        </span>
<a name="l01901"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gad1cb7ff6d513fec365eb5a830c3746f0">01901</a> <span class="preprocessor">#define  CAN_F0R1_FB9                        ((uint32_t)0x00000200)        </span>
<a name="l01902"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga6b8a688856ca6b53417948f79932534d">01902</a> <span class="preprocessor">#define  CAN_F0R1_FB10                       ((uint32_t)0x00000400)        </span>
<a name="l01903"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga72b81011a2d626ac398a387c89055935">01903</a> <span class="preprocessor">#define  CAN_F0R1_FB11                       ((uint32_t)0x00000800)        </span>
<a name="l01904"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gac178a6710aeb6c58f725dd7f00af5d5a">01904</a> <span class="preprocessor">#define  CAN_F0R1_FB12                       ((uint32_t)0x00001000)        </span>
<a name="l01905"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga8aee1182bef65da056242c4ed49dd0ef">01905</a> <span class="preprocessor">#define  CAN_F0R1_FB13                       ((uint32_t)0x00002000)        </span>
<a name="l01906"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gafe16c95f454da44949977e4225590658">01906</a> <span class="preprocessor">#define  CAN_F0R1_FB14                       ((uint32_t)0x00004000)        </span>
<a name="l01907"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gabb07dca9fddf64a3476f25f227e33e1f">01907</a> <span class="preprocessor">#define  CAN_F0R1_FB15                       ((uint32_t)0x00008000)        </span>
<a name="l01908"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaf019423a4b07e564dfe917b859e68e80">01908</a> <span class="preprocessor">#define  CAN_F0R1_FB16                       ((uint32_t)0x00010000)        </span>
<a name="l01909"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga6ee508d40637a9d558d2ab85753395bd">01909</a> <span class="preprocessor">#define  CAN_F0R1_FB17                       ((uint32_t)0x00020000)        </span>
<a name="l01910"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga827a459cd51a193d571a16e1d38fac22">01910</a> <span class="preprocessor">#define  CAN_F0R1_FB18                       ((uint32_t)0x00040000)        </span>
<a name="l01911"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga1ecfbfd6f5e129d690f1cb62ee344d78">01911</a> <span class="preprocessor">#define  CAN_F0R1_FB19                       ((uint32_t)0x00080000)        </span>
<a name="l01912"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga3a0568e276f245e1f167e673a1f5b92e">01912</a> <span class="preprocessor">#define  CAN_F0R1_FB20                       ((uint32_t)0x00100000)        </span>
<a name="l01913"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gabb71599bae1e35e750524708ac5824f1">01913</a> <span class="preprocessor">#define  CAN_F0R1_FB21                       ((uint32_t)0x00200000)        </span>
<a name="l01914"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga7589f9a62f9f5406934266820a265f3a">01914</a> <span class="preprocessor">#define  CAN_F0R1_FB22                       ((uint32_t)0x00400000)        </span>
<a name="l01915"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga7a0db2ff3fcf3ecd929d61e548905685">01915</a> <span class="preprocessor">#define  CAN_F0R1_FB23                       ((uint32_t)0x00800000)        </span>
<a name="l01916"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga2161321c3b0857a9ca07bc45ac9cd1be">01916</a> <span class="preprocessor">#define  CAN_F0R1_FB24                       ((uint32_t)0x01000000)        </span>
<a name="l01917"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaa85c1d5ccfd6241059822a3aadc1053d">01917</a> <span class="preprocessor">#define  CAN_F0R1_FB25                       ((uint32_t)0x02000000)        </span>
<a name="l01918"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga2d82ba565f065b4dec733d002c02498b">01918</a> <span class="preprocessor">#define  CAN_F0R1_FB26                       ((uint32_t)0x04000000)        </span>
<a name="l01919"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga199d63d7155cb5212982d4902e31e70c">01919</a> <span class="preprocessor">#define  CAN_F0R1_FB27                       ((uint32_t)0x08000000)        </span>
<a name="l01920"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gac82d92ad6fb51b340e8a52da903e1009">01920</a> <span class="preprocessor">#define  CAN_F0R1_FB28                       ((uint32_t)0x10000000)        </span>
<a name="l01921"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaaa0a651933135336bc14baa3e0a56ab1">01921</a> <span class="preprocessor">#define  CAN_F0R1_FB29                       ((uint32_t)0x20000000)        </span>
<a name="l01922"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaad2a1d8bb83dfcd9f13d25e8ed098b54">01922</a> <span class="preprocessor">#define  CAN_F0R1_FB30                       ((uint32_t)0x40000000)        </span>
<a name="l01923"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga6c9745bc78a65538cbe0fb0d09911554">01923</a> <span class="preprocessor">#define  CAN_F0R1_FB31                       ((uint32_t)0x80000000)        </span>
<a name="l01925"></a>01925 <span class="preprocessor"></span><span class="comment">/*******************  Bit definition for CAN_F1R1 register  *******************/</span>
<a name="l01926"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaf74bbd84aff2eb3891f6f6d0c418793c">01926</a> <span class="preprocessor">#define  CAN_F1R1_FB0                        ((uint32_t)0x00000001)        </span>
<a name="l01927"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaa2cb33663f4220e5a0d416cbddcec193">01927</a> <span class="preprocessor">#define  CAN_F1R1_FB1                        ((uint32_t)0x00000002)        </span>
<a name="l01928"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga86d75200e9ead1afbe88add086ac4bb4">01928</a> <span class="preprocessor">#define  CAN_F1R1_FB2                        ((uint32_t)0x00000004)        </span>
<a name="l01929"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaa4dbe3b567fca94f5d5e4c877e0383d4">01929</a> <span class="preprocessor">#define  CAN_F1R1_FB3                        ((uint32_t)0x00000008)        </span>
<a name="l01930"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gab74c1e5fba0af06b783289d56a8d743a">01930</a> <span class="preprocessor">#define  CAN_F1R1_FB4                        ((uint32_t)0x00000010)        </span>
<a name="l01931"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga163dda15630c6f057bac420a8cb393d8">01931</a> <span class="preprocessor">#define  CAN_F1R1_FB5                        ((uint32_t)0x00000020)        </span>
<a name="l01932"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gadd27041e24d500c940abed9aaa53910d">01932</a> <span class="preprocessor">#define  CAN_F1R1_FB6                        ((uint32_t)0x00000040)        </span>
<a name="l01933"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaadfffc15f309b85cc3abd7439ea4b8c6">01933</a> <span class="preprocessor">#define  CAN_F1R1_FB7                        ((uint32_t)0x00000080)        </span>
<a name="l01934"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gadf2588b13464de27f12768d33a75d2ba">01934</a> <span class="preprocessor">#define  CAN_F1R1_FB8                        ((uint32_t)0x00000100)        </span>
<a name="l01935"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga979839e5c63f94eb294a09b74f5c09bf">01935</a> <span class="preprocessor">#define  CAN_F1R1_FB9                        ((uint32_t)0x00000200)        </span>
<a name="l01936"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga7f049fa606d557a8a468747c6d285357">01936</a> <span class="preprocessor">#define  CAN_F1R1_FB10                       ((uint32_t)0x00000400)        </span>
<a name="l01937"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga43409866ee9e6ea1712f50679a4bb212">01937</a> <span class="preprocessor">#define  CAN_F1R1_FB11                       ((uint32_t)0x00000800)        </span>
<a name="l01938"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga3f86fb2f2080f513d8392d389cdaa1fd">01938</a> <span class="preprocessor">#define  CAN_F1R1_FB12                       ((uint32_t)0x00001000)        </span>
<a name="l01939"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga2c1b7aeeb196a6564b2b3f049590520e">01939</a> <span class="preprocessor">#define  CAN_F1R1_FB13                       ((uint32_t)0x00002000)        </span>
<a name="l01940"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga45bad406315318f9cecb0c783ac7218d">01940</a> <span class="preprocessor">#define  CAN_F1R1_FB14                       ((uint32_t)0x00004000)        </span>
<a name="l01941"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga9b105deaf668c0e04950be0de975bcde">01941</a> <span class="preprocessor">#define  CAN_F1R1_FB15                       ((uint32_t)0x00008000)        </span>
<a name="l01942"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga84fabcf9736d7ef78587ff63cb6b1373">01942</a> <span class="preprocessor">#define  CAN_F1R1_FB16                       ((uint32_t)0x00010000)        </span>
<a name="l01943"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga966d41aca2269fd8cb6830dbbd176140">01943</a> <span class="preprocessor">#define  CAN_F1R1_FB17                       ((uint32_t)0x00020000)        </span>
<a name="l01944"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga9a53cd0cf8722dc63b8ff26d4b0fa0f7">01944</a> <span class="preprocessor">#define  CAN_F1R1_FB18                       ((uint32_t)0x00040000)        </span>
<a name="l01945"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga3fb64b2b59f73045b3ead12ab1211b4b">01945</a> <span class="preprocessor">#define  CAN_F1R1_FB19                       ((uint32_t)0x00080000)        </span>
<a name="l01946"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gad558faeeeaf748bdface31d4bd3ed5b6">01946</a> <span class="preprocessor">#define  CAN_F1R1_FB20                       ((uint32_t)0x00100000)        </span>
<a name="l01947"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gab16bc53f206b1f318e5fe8c248294fec">01947</a> <span class="preprocessor">#define  CAN_F1R1_FB21                       ((uint32_t)0x00200000)        </span>
<a name="l01948"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga42841c82744146dc70e8e679b5904e02">01948</a> <span class="preprocessor">#define  CAN_F1R1_FB22                       ((uint32_t)0x00400000)        </span>
<a name="l01949"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gad1f961b642e42faaaf495c9ec099c128">01949</a> <span class="preprocessor">#define  CAN_F1R1_FB23                       ((uint32_t)0x00800000)        </span>
<a name="l01950"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga96670686c71a15631ec2f772973dd7d5">01950</a> <span class="preprocessor">#define  CAN_F1R1_FB24                       ((uint32_t)0x01000000)        </span>
<a name="l01951"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaa2d8b1a30c3a6ae1f75369abc445ab7d">01951</a> <span class="preprocessor">#define  CAN_F1R1_FB25                       ((uint32_t)0x02000000)        </span>
<a name="l01952"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaf027c958889ab93acfb1b86988269874">01952</a> <span class="preprocessor">#define  CAN_F1R1_FB26                       ((uint32_t)0x04000000)        </span>
<a name="l01953"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga32400e283bc0037da21f0c913bb860b6">01953</a> <span class="preprocessor">#define  CAN_F1R1_FB27                       ((uint32_t)0x08000000)        </span>
<a name="l01954"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gadb0467d664f27b3ca8ef4ad220593c46">01954</a> <span class="preprocessor">#define  CAN_F1R1_FB28                       ((uint32_t)0x10000000)        </span>
<a name="l01955"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga1c3e3090ab67a54830be208a628efd8f">01955</a> <span class="preprocessor">#define  CAN_F1R1_FB29                       ((uint32_t)0x20000000)        </span>
<a name="l01956"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga85034e026be1af5e45e5d15537449e6d">01956</a> <span class="preprocessor">#define  CAN_F1R1_FB30                       ((uint32_t)0x40000000)        </span>
<a name="l01957"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga6ddfc083d58a190057fb67e4eb31136b">01957</a> <span class="preprocessor">#define  CAN_F1R1_FB31                       ((uint32_t)0x80000000)        </span>
<a name="l01959"></a>01959 <span class="preprocessor"></span><span class="comment">/*******************  Bit definition for CAN_F2R1 register  *******************/</span>
<a name="l01960"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaf17f4c3e553020ee893415796bd29d84">01960</a> <span class="preprocessor">#define  CAN_F2R1_FB0                        ((uint32_t)0x00000001)        </span>
<a name="l01961"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gae97de172023462e5f40d4b420209809b">01961</a> <span class="preprocessor">#define  CAN_F2R1_FB1                        ((uint32_t)0x00000002)        </span>
<a name="l01962"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga23008ac61893eb6a65ab9041c53a84ee">01962</a> <span class="preprocessor">#define  CAN_F2R1_FB2                        ((uint32_t)0x00000004)        </span>
<a name="l01963"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gad559580b386d0c621a6bf7292c706e36">01963</a> <span class="preprocessor">#define  CAN_F2R1_FB3                        ((uint32_t)0x00000008)        </span>
<a name="l01964"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga0e52ca421788d68f3edb9a52434374dd">01964</a> <span class="preprocessor">#define  CAN_F2R1_FB4                        ((uint32_t)0x00000010)        </span>
<a name="l01965"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga96a97a9711a0a53a7ee18907e95d8887">01965</a> <span class="preprocessor">#define  CAN_F2R1_FB5                        ((uint32_t)0x00000020)        </span>
<a name="l01966"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga6f73f1bd0d3246f27d7a91a620fb3cc7">01966</a> <span class="preprocessor">#define  CAN_F2R1_FB6                        ((uint32_t)0x00000040)        </span>
<a name="l01967"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga72bf4a6050af614eb1ac85c76feb95cc">01967</a> <span class="preprocessor">#define  CAN_F2R1_FB7                        ((uint32_t)0x00000080)        </span>
<a name="l01968"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gad484c083bc2023deda5840facc549908">01968</a> <span class="preprocessor">#define  CAN_F2R1_FB8                        ((uint32_t)0x00000100)        </span>
<a name="l01969"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga0d0e05e4824f05e2cf12b3d0a0b7f319">01969</a> <span class="preprocessor">#define  CAN_F2R1_FB9                        ((uint32_t)0x00000200)        </span>
<a name="l01970"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga022da7a86e8174aff1054eb1aef2c73c">01970</a> <span class="preprocessor">#define  CAN_F2R1_FB10                       ((uint32_t)0x00000400)        </span>
<a name="l01971"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaedf715fa1ef43c8461408944e4aecec7">01971</a> <span class="preprocessor">#define  CAN_F2R1_FB11                       ((uint32_t)0x00000800)        </span>
<a name="l01972"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga47960a79c582cbc9bfef85c411a2be94">01972</a> <span class="preprocessor">#define  CAN_F2R1_FB12                       ((uint32_t)0x00001000)        </span>
<a name="l01973"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gae8c6e3cf3a4d1e9d722e820a3a0c1b6a">01973</a> <span class="preprocessor">#define  CAN_F2R1_FB13                       ((uint32_t)0x00002000)        </span>
<a name="l01974"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga421a366074fb422686461a92abd1259e">01974</a> <span class="preprocessor">#define  CAN_F2R1_FB14                       ((uint32_t)0x00004000)        </span>
<a name="l01975"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga178a0308db954b97818401be1f28a990">01975</a> <span class="preprocessor">#define  CAN_F2R1_FB15                       ((uint32_t)0x00008000)        </span>
<a name="l01976"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gab60aef7e45f8d12777032321a33cdb38">01976</a> <span class="preprocessor">#define  CAN_F2R1_FB16                       ((uint32_t)0x00010000)        </span>
<a name="l01977"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga0483dac5b6986246a3ba106fbeb8e3bd">01977</a> <span class="preprocessor">#define  CAN_F2R1_FB17                       ((uint32_t)0x00020000)        </span>
<a name="l01978"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga259b472c9c9f158e1701c8b8d5a940b9">01978</a> <span class="preprocessor">#define  CAN_F2R1_FB18                       ((uint32_t)0x00040000)        </span>
<a name="l01979"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga23db612c79422bee815e437d6aaf5a6c">01979</a> <span class="preprocessor">#define  CAN_F2R1_FB19                       ((uint32_t)0x00080000)        </span>
<a name="l01980"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaef9a469e877bfa29f4edb66730c43d43">01980</a> <span class="preprocessor">#define  CAN_F2R1_FB20                       ((uint32_t)0x00100000)        </span>
<a name="l01981"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga4edc4a54cc13f63afe8dbe3aa37776a5">01981</a> <span class="preprocessor">#define  CAN_F2R1_FB21                       ((uint32_t)0x00200000)        </span>
<a name="l01982"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga169f5fb3dd35ae2b048c8c05c3e202d7">01982</a> <span class="preprocessor">#define  CAN_F2R1_FB22                       ((uint32_t)0x00400000)        </span>
<a name="l01983"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga0073b206235b3c33a9b831e5027e3bf0">01983</a> <span class="preprocessor">#define  CAN_F2R1_FB23                       ((uint32_t)0x00800000)        </span>
<a name="l01984"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga459caea38417d17c042e52ba38eb3c1b">01984</a> <span class="preprocessor">#define  CAN_F2R1_FB24                       ((uint32_t)0x01000000)        </span>
<a name="l01985"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gae0da8cd8657f6e67f1d86fc9f695bb4e">01985</a> <span class="preprocessor">#define  CAN_F2R1_FB25                       ((uint32_t)0x02000000)        </span>
<a name="l01986"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga80c9ae7f2eca3db813737c49d49f2b08">01986</a> <span class="preprocessor">#define  CAN_F2R1_FB26                       ((uint32_t)0x04000000)        </span>
<a name="l01987"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga1d6b6c109e359e3d2a07e6626c2b4aff">01987</a> <span class="preprocessor">#define  CAN_F2R1_FB27                       ((uint32_t)0x08000000)        </span>
<a name="l01988"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga3c4d05997d8930291c8ab2bb19545714">01988</a> <span class="preprocessor">#define  CAN_F2R1_FB28                       ((uint32_t)0x10000000)        </span>
<a name="l01989"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gad5431f98aafd2a7f8158a335d65ebea1">01989</a> <span class="preprocessor">#define  CAN_F2R1_FB29                       ((uint32_t)0x20000000)        </span>
<a name="l01990"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gad79345a758898023543bd5384be09758">01990</a> <span class="preprocessor">#define  CAN_F2R1_FB30                       ((uint32_t)0x40000000)        </span>
<a name="l01991"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaada8442f47c1fffb00c13e404d036122">01991</a> <span class="preprocessor">#define  CAN_F2R1_FB31                       ((uint32_t)0x80000000)        </span>
<a name="l01993"></a>01993 <span class="preprocessor"></span><span class="comment">/*******************  Bit definition for CAN_F3R1 register  *******************/</span>
<a name="l01994"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga6bc065319a9862c1f5ca7326b790ef53">01994</a> <span class="preprocessor">#define  CAN_F3R1_FB0                        ((uint32_t)0x00000001)        </span>
<a name="l01995"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga42e636521c72a20aa8380fe4fe150b91">01995</a> <span class="preprocessor">#define  CAN_F3R1_FB1                        ((uint32_t)0x00000002)        </span>
<a name="l01996"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga217f5b77e4fefb2d1135187ee2b5bbf2">01996</a> <span class="preprocessor">#define  CAN_F3R1_FB2                        ((uint32_t)0x00000004)        </span>
<a name="l01997"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga7693dcf6c0011bbeb19e0413a5ce1f56">01997</a> <span class="preprocessor">#define  CAN_F3R1_FB3                        ((uint32_t)0x00000008)        </span>
<a name="l01998"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga0bffde5d3e1e2e75f4facc98903620f7">01998</a> <span class="preprocessor">#define  CAN_F3R1_FB4                        ((uint32_t)0x00000010)        </span>
<a name="l01999"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga30ccdfd3676f314e749cc205ffcfe1cf">01999</a> <span class="preprocessor">#define  CAN_F3R1_FB5                        ((uint32_t)0x00000020)        </span>
<a name="l02000"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga2b2aa80397b4961a33b41303aa348ea1">02000</a> <span class="preprocessor">#define  CAN_F3R1_FB6                        ((uint32_t)0x00000040)        </span>
<a name="l02001"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga7b7072c9b829c7df660eb2dea05ee8d8">02001</a> <span class="preprocessor">#define  CAN_F3R1_FB7                        ((uint32_t)0x00000080)        </span>
<a name="l02002"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gad016208d1aa9008aaba9a887a1e8b6fa">02002</a> <span class="preprocessor">#define  CAN_F3R1_FB8                        ((uint32_t)0x00000100)        </span>
<a name="l02003"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gad4f4f0d2b56860e36f7777ab397e8609">02003</a> <span class="preprocessor">#define  CAN_F3R1_FB9                        ((uint32_t)0x00000200)        </span>
<a name="l02004"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gadcfc2559b456c3af3804a22e0fb5c50d">02004</a> <span class="preprocessor">#define  CAN_F3R1_FB10                       ((uint32_t)0x00000400)        </span>
<a name="l02005"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga7df8031e3a2f661b45fdbde58a26c6b6">02005</a> <span class="preprocessor">#define  CAN_F3R1_FB11                       ((uint32_t)0x00000800)        </span>
<a name="l02006"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga6c6baa9ac6a1cdd55c2d51ee40cf8f2d">02006</a> <span class="preprocessor">#define  CAN_F3R1_FB12                       ((uint32_t)0x00001000)        </span>
<a name="l02007"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga95fc8c778ffa6deac5a202985fdd98ae">02007</a> <span class="preprocessor">#define  CAN_F3R1_FB13                       ((uint32_t)0x00002000)        </span>
<a name="l02008"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga0c4a4998f2ddc12771da116b1c20d765">02008</a> <span class="preprocessor">#define  CAN_F3R1_FB14                       ((uint32_t)0x00004000)        </span>
<a name="l02009"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga5fb6157fc48147e6c74ed348d156bfa1">02009</a> <span class="preprocessor">#define  CAN_F3R1_FB15                       ((uint32_t)0x00008000)        </span>
<a name="l02010"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaadcf2a14e752519bf8a90129fb9d42b1">02010</a> <span class="preprocessor">#define  CAN_F3R1_FB16                       ((uint32_t)0x00010000)        </span>
<a name="l02011"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga47c5296c991b481548302478df85e477">02011</a> <span class="preprocessor">#define  CAN_F3R1_FB17                       ((uint32_t)0x00020000)        </span>
<a name="l02012"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga657b8cda94fd736a4831ab4086ae746f">02012</a> <span class="preprocessor">#define  CAN_F3R1_FB18                       ((uint32_t)0x00040000)        </span>
<a name="l02013"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga435edc4b2055ac2d1c3ce616a9c1b236">02013</a> <span class="preprocessor">#define  CAN_F3R1_FB19                       ((uint32_t)0x00080000)        </span>
<a name="l02014"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaaa508de7087eb832ecaf353a4b6821ef">02014</a> <span class="preprocessor">#define  CAN_F3R1_FB20                       ((uint32_t)0x00100000)        </span>
<a name="l02015"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga643ceb9293665b8307e63ae0e1700d91">02015</a> <span class="preprocessor">#define  CAN_F3R1_FB21                       ((uint32_t)0x00200000)        </span>
<a name="l02016"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga91f5887e884fcf423d680798f4e372bb">02016</a> <span class="preprocessor">#define  CAN_F3R1_FB22                       ((uint32_t)0x00400000)        </span>
<a name="l02017"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga6adc9c7706f39f7c33760fe6b8c5d17e">02017</a> <span class="preprocessor">#define  CAN_F3R1_FB23                       ((uint32_t)0x00800000)        </span>
<a name="l02018"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gad7581186f0241f6db9f63a0a0db22919">02018</a> <span class="preprocessor">#define  CAN_F3R1_FB24                       ((uint32_t)0x01000000)        </span>
<a name="l02019"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga43b4c084e802398ad265ceb69cfd7519">02019</a> <span class="preprocessor">#define  CAN_F3R1_FB25                       ((uint32_t)0x02000000)        </span>
<a name="l02020"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gade732503a8d41e3f1bb338a2a8103bd2">02020</a> <span class="preprocessor">#define  CAN_F3R1_FB26                       ((uint32_t)0x04000000)        </span>
<a name="l02021"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga7539a7f651425a757a549205544e508c">02021</a> <span class="preprocessor">#define  CAN_F3R1_FB27                       ((uint32_t)0x08000000)        </span>
<a name="l02022"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga1ec25e4ba3ebaf53780e2b8da63e4a3b">02022</a> <span class="preprocessor">#define  CAN_F3R1_FB28                       ((uint32_t)0x10000000)        </span>
<a name="l02023"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gae8268be8b5477f813c165e851acd41a2">02023</a> <span class="preprocessor">#define  CAN_F3R1_FB29                       ((uint32_t)0x20000000)        </span>
<a name="l02024"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga494ad7f35d8552b8494379916a987074">02024</a> <span class="preprocessor">#define  CAN_F3R1_FB30                       ((uint32_t)0x40000000)        </span>
<a name="l02025"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga15bbe0d2d24dc95e10156c2541feb4c4">02025</a> <span class="preprocessor">#define  CAN_F3R1_FB31                       ((uint32_t)0x80000000)        </span>
<a name="l02027"></a>02027 <span class="preprocessor"></span><span class="comment">/*******************  Bit definition for CAN_F4R1 register  *******************/</span>
<a name="l02028"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga0eb0d4d21c082c8381271ab146431993">02028</a> <span class="preprocessor">#define  CAN_F4R1_FB0                        ((uint32_t)0x00000001)        </span>
<a name="l02029"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga91922c78bf92f051b8e8abbf9cc1f6e9">02029</a> <span class="preprocessor">#define  CAN_F4R1_FB1                        ((uint32_t)0x00000002)        </span>
<a name="l02030"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gae56f77f869114e69525353f96004f955">02030</a> <span class="preprocessor">#define  CAN_F4R1_FB2                        ((uint32_t)0x00000004)        </span>
<a name="l02031"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga951a8213e55b01ecedcef870c85841e7">02031</a> <span class="preprocessor">#define  CAN_F4R1_FB3                        ((uint32_t)0x00000008)        </span>
<a name="l02032"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga453f90cdd0b520b7d65e19af3868d4ec">02032</a> <span class="preprocessor">#define  CAN_F4R1_FB4                        ((uint32_t)0x00000010)        </span>
<a name="l02033"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gace348ba56c1f9676e5b605a6fe0cd52e">02033</a> <span class="preprocessor">#define  CAN_F4R1_FB5                        ((uint32_t)0x00000020)        </span>
<a name="l02034"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gae99d36b50a16c38b2006fdba4683ddd9">02034</a> <span class="preprocessor">#define  CAN_F4R1_FB6                        ((uint32_t)0x00000040)        </span>
<a name="l02035"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga5d61ae4af9acc61476493b640cfb4745">02035</a> <span class="preprocessor">#define  CAN_F4R1_FB7                        ((uint32_t)0x00000080)        </span>
<a name="l02036"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga89ded00ec0b6c0918b019457d6cf43f5">02036</a> <span class="preprocessor">#define  CAN_F4R1_FB8                        ((uint32_t)0x00000100)        </span>
<a name="l02037"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gac658a1ced873fd9dff54833d8c413536">02037</a> <span class="preprocessor">#define  CAN_F4R1_FB9                        ((uint32_t)0x00000200)        </span>
<a name="l02038"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gad06bc748776a78f008895be9e0cc7a1d">02038</a> <span class="preprocessor">#define  CAN_F4R1_FB10                       ((uint32_t)0x00000400)        </span>
<a name="l02039"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaf612f239dcf45bd933136a5c8c5909f9">02039</a> <span class="preprocessor">#define  CAN_F4R1_FB11                       ((uint32_t)0x00000800)        </span>
<a name="l02040"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga6dc611a52acf6dfa1df7ebf867bc7e2f">02040</a> <span class="preprocessor">#define  CAN_F4R1_FB12                       ((uint32_t)0x00001000)        </span>
<a name="l02041"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga1736bc2808a37aa82358fe1c36c963a6">02041</a> <span class="preprocessor">#define  CAN_F4R1_FB13                       ((uint32_t)0x00002000)        </span>
<a name="l02042"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga7d7ec466bbf196a41f6da2a7b506675d">02042</a> <span class="preprocessor">#define  CAN_F4R1_FB14                       ((uint32_t)0x00004000)        </span>
<a name="l02043"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gad30ff7e7b0c0f7e56821ecbcd6fcc23c">02043</a> <span class="preprocessor">#define  CAN_F4R1_FB15                       ((uint32_t)0x00008000)        </span>
<a name="l02044"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga199bd29b6f3ff56150a9dcd71c8ea13f">02044</a> <span class="preprocessor">#define  CAN_F4R1_FB16                       ((uint32_t)0x00010000)        </span>
<a name="l02045"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga893837534cbc7a043fa995de4619e2da">02045</a> <span class="preprocessor">#define  CAN_F4R1_FB17                       ((uint32_t)0x00020000)        </span>
<a name="l02046"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga551e80c41958417cbcf1d0c53e4947a3">02046</a> <span class="preprocessor">#define  CAN_F4R1_FB18                       ((uint32_t)0x00040000)        </span>
<a name="l02047"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga80d9a946bd39dae4b0a862cf21f262ed">02047</a> <span class="preprocessor">#define  CAN_F4R1_FB19                       ((uint32_t)0x00080000)        </span>
<a name="l02048"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga5646609987ce174cf3b94bb4538172f4">02048</a> <span class="preprocessor">#define  CAN_F4R1_FB20                       ((uint32_t)0x00100000)        </span>
<a name="l02049"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga356faa77de97c61e9b5f6b763173a987">02049</a> <span class="preprocessor">#define  CAN_F4R1_FB21                       ((uint32_t)0x00200000)        </span>
<a name="l02050"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gac6b246b3df35cc1db06e8c809137562f">02050</a> <span class="preprocessor">#define  CAN_F4R1_FB22                       ((uint32_t)0x00400000)        </span>
<a name="l02051"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga4882da3ee5be3aed3d5eb46923859674">02051</a> <span class="preprocessor">#define  CAN_F4R1_FB23                       ((uint32_t)0x00800000)        </span>
<a name="l02052"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga1e178aa8c6f98a866aaae511b9da86c8">02052</a> <span class="preprocessor">#define  CAN_F4R1_FB24                       ((uint32_t)0x01000000)        </span>
<a name="l02053"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga9a5ca327060530761d71362d39b2d364">02053</a> <span class="preprocessor">#define  CAN_F4R1_FB25                       ((uint32_t)0x02000000)        </span>
<a name="l02054"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaeabe4836aed74af4adba72b2c7684a6e">02054</a> <span class="preprocessor">#define  CAN_F4R1_FB26                       ((uint32_t)0x04000000)        </span>
<a name="l02055"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaaa8e7d74919e74723f7df71357cc994a">02055</a> <span class="preprocessor">#define  CAN_F4R1_FB27                       ((uint32_t)0x08000000)        </span>
<a name="l02056"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga6e2b2b9bd5b397e58d57fb379546110b">02056</a> <span class="preprocessor">#define  CAN_F4R1_FB28                       ((uint32_t)0x10000000)        </span>
<a name="l02057"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaeb165ede225dc35a825647e5efcab437">02057</a> <span class="preprocessor">#define  CAN_F4R1_FB29                       ((uint32_t)0x20000000)        </span>
<a name="l02058"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga7898b1f422424fd7fc0896b908748e7c">02058</a> <span class="preprocessor">#define  CAN_F4R1_FB30                       ((uint32_t)0x40000000)        </span>
<a name="l02059"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga92d7e6a44e87911e9cc14f6bff854fa2">02059</a> <span class="preprocessor">#define  CAN_F4R1_FB31                       ((uint32_t)0x80000000)        </span>
<a name="l02061"></a>02061 <span class="preprocessor"></span><span class="comment">/*******************  Bit definition for CAN_F5R1 register  *******************/</span>
<a name="l02062"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga5cdf98e317662e286ad2a3344ee516df">02062</a> <span class="preprocessor">#define  CAN_F5R1_FB0                        ((uint32_t)0x00000001)        </span>
<a name="l02063"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaac814c424ed2ccc11645da6e62f3fb81">02063</a> <span class="preprocessor">#define  CAN_F5R1_FB1                        ((uint32_t)0x00000002)        </span>
<a name="l02064"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga4b0af1936dd43bd319614e3298fd28d1">02064</a> <span class="preprocessor">#define  CAN_F5R1_FB2                        ((uint32_t)0x00000004)        </span>
<a name="l02065"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga013f84e3f3f0e148d3a9a071ccbf6738">02065</a> <span class="preprocessor">#define  CAN_F5R1_FB3                        ((uint32_t)0x00000008)        </span>
<a name="l02066"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga7cfc330921811d76ed6476d6935e84e7">02066</a> <span class="preprocessor">#define  CAN_F5R1_FB4                        ((uint32_t)0x00000010)        </span>
<a name="l02067"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaf9aebaa8e61198240c1564ce73acb1d2">02067</a> <span class="preprocessor">#define  CAN_F5R1_FB5                        ((uint32_t)0x00000020)        </span>
<a name="l02068"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gadea331fb6273fda80a8f5a3dc8eaf6f4">02068</a> <span class="preprocessor">#define  CAN_F5R1_FB6                        ((uint32_t)0x00000040)        </span>
<a name="l02069"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gafc7dfaacfba6a42a17b16281f690f952">02069</a> <span class="preprocessor">#define  CAN_F5R1_FB7                        ((uint32_t)0x00000080)        </span>
<a name="l02070"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaba0938e0f55773406fd59c2a0bd7c46e">02070</a> <span class="preprocessor">#define  CAN_F5R1_FB8                        ((uint32_t)0x00000100)        </span>
<a name="l02071"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga9715c4445159d0068172309092e574e3">02071</a> <span class="preprocessor">#define  CAN_F5R1_FB9                        ((uint32_t)0x00000200)        </span>
<a name="l02072"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gae7de15e73395473569a447023dae53c4">02072</a> <span class="preprocessor">#define  CAN_F5R1_FB10                       ((uint32_t)0x00000400)        </span>
<a name="l02073"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga39b60e0befdf681694bc4123b4b7f7bd">02073</a> <span class="preprocessor">#define  CAN_F5R1_FB11                       ((uint32_t)0x00000800)        </span>
<a name="l02074"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga0bc4598d0d603c802b7140f967d84e5c">02074</a> <span class="preprocessor">#define  CAN_F5R1_FB12                       ((uint32_t)0x00001000)        </span>
<a name="l02075"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gac8b4439ac4bc79ff74d21060ff533b12">02075</a> <span class="preprocessor">#define  CAN_F5R1_FB13                       ((uint32_t)0x00002000)        </span>
<a name="l02076"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga0d117ee64d9c1673f22f12f24bd481a4">02076</a> <span class="preprocessor">#define  CAN_F5R1_FB14                       ((uint32_t)0x00004000)        </span>
<a name="l02077"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaf761c448bf29c4d93f4c2a75981fa049">02077</a> <span class="preprocessor">#define  CAN_F5R1_FB15                       ((uint32_t)0x00008000)        </span>
<a name="l02078"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga87543e5b7c48580ca9925402ab6ca5a7">02078</a> <span class="preprocessor">#define  CAN_F5R1_FB16                       ((uint32_t)0x00010000)        </span>
<a name="l02079"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga9b9c39ec4649cd68a540c88c3c64d506">02079</a> <span class="preprocessor">#define  CAN_F5R1_FB17                       ((uint32_t)0x00020000)        </span>
<a name="l02080"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga4992301536d388de215273769708b843">02080</a> <span class="preprocessor">#define  CAN_F5R1_FB18                       ((uint32_t)0x00040000)        </span>
<a name="l02081"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gab21c0b793d7aff03497a95d5c6528ab2">02081</a> <span class="preprocessor">#define  CAN_F5R1_FB19                       ((uint32_t)0x00080000)        </span>
<a name="l02082"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaf1c4c5d06a9da5f853aaede3470b07f4">02082</a> <span class="preprocessor">#define  CAN_F5R1_FB20                       ((uint32_t)0x00100000)        </span>
<a name="l02083"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga91214f1f7dbb4b75b0c425624640fd76">02083</a> <span class="preprocessor">#define  CAN_F5R1_FB21                       ((uint32_t)0x00200000)        </span>
<a name="l02084"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga1b24151a68c59fe0f3aa15e498fdc739">02084</a> <span class="preprocessor">#define  CAN_F5R1_FB22                       ((uint32_t)0x00400000)        </span>
<a name="l02085"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gadea89ef2e5c3dafae174b671c8e083d2">02085</a> <span class="preprocessor">#define  CAN_F5R1_FB23                       ((uint32_t)0x00800000)        </span>
<a name="l02086"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga2acccf9ab5708116cd888f2d65da54cc">02086</a> <span class="preprocessor">#define  CAN_F5R1_FB24                       ((uint32_t)0x01000000)        </span>
<a name="l02087"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga3c0b9425117a2409b61032a9c746c2b5">02087</a> <span class="preprocessor">#define  CAN_F5R1_FB25                       ((uint32_t)0x02000000)        </span>
<a name="l02088"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga0a0d31d96e75ea32299e78845f584632">02088</a> <span class="preprocessor">#define  CAN_F5R1_FB26                       ((uint32_t)0x04000000)        </span>
<a name="l02089"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gade5db4ad8b19580b895356fff66bb6be">02089</a> <span class="preprocessor">#define  CAN_F5R1_FB27                       ((uint32_t)0x08000000)        </span>
<a name="l02090"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga4acec834c3eaf55af5e745d6988ddc1e">02090</a> <span class="preprocessor">#define  CAN_F5R1_FB28                       ((uint32_t)0x10000000)        </span>
<a name="l02091"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga923a0086ada8e09a9202338b588f27d1">02091</a> <span class="preprocessor">#define  CAN_F5R1_FB29                       ((uint32_t)0x20000000)        </span>
<a name="l02092"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga840d2b3f751753e9d21b2e23506e6995">02092</a> <span class="preprocessor">#define  CAN_F5R1_FB30                       ((uint32_t)0x40000000)        </span>
<a name="l02093"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gac8d28066798958e5730a95353690bcd0">02093</a> <span class="preprocessor">#define  CAN_F5R1_FB31                       ((uint32_t)0x80000000)        </span>
<a name="l02095"></a>02095 <span class="preprocessor"></span><span class="comment">/*******************  Bit definition for CAN_F6R1 register  *******************/</span>
<a name="l02096"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gacb57fe42259bd37deffe11eded640c76">02096</a> <span class="preprocessor">#define  CAN_F6R1_FB0                        ((uint32_t)0x00000001)        </span>
<a name="l02097"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga1de288e28d5547106645ecc5b0c47f2a">02097</a> <span class="preprocessor">#define  CAN_F6R1_FB1                        ((uint32_t)0x00000002)        </span>
<a name="l02098"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaaa8662caaa28aee37b2689f55400b75c">02098</a> <span class="preprocessor">#define  CAN_F6R1_FB2                        ((uint32_t)0x00000004)        </span>
<a name="l02099"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gae4ccedde67989fcbaa84cae9cae4b1eb">02099</a> <span class="preprocessor">#define  CAN_F6R1_FB3                        ((uint32_t)0x00000008)        </span>
<a name="l02100"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga45b063b3c14fd27bd63c03f878ac6cfc">02100</a> <span class="preprocessor">#define  CAN_F6R1_FB4                        ((uint32_t)0x00000010)        </span>
<a name="l02101"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga32f8566fab72dec6d52ad7262e67cbcc">02101</a> <span class="preprocessor">#define  CAN_F6R1_FB5                        ((uint32_t)0x00000020)        </span>
<a name="l02102"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga8636ecdacc3ca05d69e66737b7f2e7cf">02102</a> <span class="preprocessor">#define  CAN_F6R1_FB6                        ((uint32_t)0x00000040)        </span>
<a name="l02103"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gadb555ddab4853625c9b48b24e88d0dd8">02103</a> <span class="preprocessor">#define  CAN_F6R1_FB7                        ((uint32_t)0x00000080)        </span>
<a name="l02104"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaa1e7ca2d014d77152ff0e6bbb8d5fb63">02104</a> <span class="preprocessor">#define  CAN_F6R1_FB8                        ((uint32_t)0x00000100)        </span>
<a name="l02105"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gafe4dc5e57c209eb4d3c5ed94b3a2e897">02105</a> <span class="preprocessor">#define  CAN_F6R1_FB9                        ((uint32_t)0x00000200)        </span>
<a name="l02106"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaa63ca9ec114f553d68e0b0d38ae57ff0">02106</a> <span class="preprocessor">#define  CAN_F6R1_FB10                       ((uint32_t)0x00000400)        </span>
<a name="l02107"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gadf3394a2675a7cb30556a40cc5b77c08">02107</a> <span class="preprocessor">#define  CAN_F6R1_FB11                       ((uint32_t)0x00000800)        </span>
<a name="l02108"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gae9c9c04edb492e48619de926196ab695">02108</a> <span class="preprocessor">#define  CAN_F6R1_FB12                       ((uint32_t)0x00001000)        </span>
<a name="l02109"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga070e91897e07ae11a9d2f60ff31e196a">02109</a> <span class="preprocessor">#define  CAN_F6R1_FB13                       ((uint32_t)0x00002000)        </span>
<a name="l02110"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga3479321a85f1f55e24a1b56d13226a22">02110</a> <span class="preprocessor">#define  CAN_F6R1_FB14                       ((uint32_t)0x00004000)        </span>
<a name="l02111"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga9a998a2b37fde5207b286a58c115a9e8">02111</a> <span class="preprocessor">#define  CAN_F6R1_FB15                       ((uint32_t)0x00008000)        </span>
<a name="l02112"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga891ad3d341cee397d49fc982c509f7d5">02112</a> <span class="preprocessor">#define  CAN_F6R1_FB16                       ((uint32_t)0x00010000)        </span>
<a name="l02113"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gac4a70606f1b07a6bbb5ae4fe8ad374e5">02113</a> <span class="preprocessor">#define  CAN_F6R1_FB17                       ((uint32_t)0x00020000)        </span>
<a name="l02114"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga1542ea54030e3052c8991b249cd0e504">02114</a> <span class="preprocessor">#define  CAN_F6R1_FB18                       ((uint32_t)0x00040000)        </span>
<a name="l02115"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga1e1a7c680bcfc57c6cc521cbaa0749d6">02115</a> <span class="preprocessor">#define  CAN_F6R1_FB19                       ((uint32_t)0x00080000)        </span>
<a name="l02116"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga6fba31d938ab3492c8855c26bebfbef2">02116</a> <span class="preprocessor">#define  CAN_F6R1_FB20                       ((uint32_t)0x00100000)        </span>
<a name="l02117"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga556f3b08cee839e038109e604e5bba4c">02117</a> <span class="preprocessor">#define  CAN_F6R1_FB21                       ((uint32_t)0x00200000)        </span>
<a name="l02118"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gafdc41162219ed6f5be1b5ae7ba328754">02118</a> <span class="preprocessor">#define  CAN_F6R1_FB22                       ((uint32_t)0x00400000)        </span>
<a name="l02119"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga89f4fd5c28d2fd7475081b39b2b358c6">02119</a> <span class="preprocessor">#define  CAN_F6R1_FB23                       ((uint32_t)0x00800000)        </span>
<a name="l02120"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gac5eb9d0f3cad0eeea398f2ba5fd83cf2">02120</a> <span class="preprocessor">#define  CAN_F6R1_FB24                       ((uint32_t)0x01000000)        </span>
<a name="l02121"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaa3fa46e9d1fafcb3eb1189d6d43692cd">02121</a> <span class="preprocessor">#define  CAN_F6R1_FB25                       ((uint32_t)0x02000000)        </span>
<a name="l02122"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gab9168b4d12ddb654b397ce3ffb66af4c">02122</a> <span class="preprocessor">#define  CAN_F6R1_FB26                       ((uint32_t)0x04000000)        </span>
<a name="l02123"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga610fdf301fb1cff5af38f83b4e0c81b1">02123</a> <span class="preprocessor">#define  CAN_F6R1_FB27                       ((uint32_t)0x08000000)        </span>
<a name="l02124"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga8a3e033aae51ff31b75fb801599232f5">02124</a> <span class="preprocessor">#define  CAN_F6R1_FB28                       ((uint32_t)0x10000000)        </span>
<a name="l02125"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga868ae6fc3bbe273b44d250791a80df58">02125</a> <span class="preprocessor">#define  CAN_F6R1_FB29                       ((uint32_t)0x20000000)        </span>
<a name="l02126"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gafe08696e215f9e8f1605e60e4817dd8b">02126</a> <span class="preprocessor">#define  CAN_F6R1_FB30                       ((uint32_t)0x40000000)        </span>
<a name="l02127"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga69b2dffd9969ff8658b45a7a2bb1c5ee">02127</a> <span class="preprocessor">#define  CAN_F6R1_FB31                       ((uint32_t)0x80000000)        </span>
<a name="l02129"></a>02129 <span class="preprocessor"></span><span class="comment">/*******************  Bit definition for CAN_F7R1 register  *******************/</span>
<a name="l02130"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga2217bcc5b82de25751d3984884b0e0c1">02130</a> <span class="preprocessor">#define  CAN_F7R1_FB0                        ((uint32_t)0x00000001)        </span>
<a name="l02131"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaf71cbdd5cbe109fde119adb86d64f0a7">02131</a> <span class="preprocessor">#define  CAN_F7R1_FB1                        ((uint32_t)0x00000002)        </span>
<a name="l02132"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaa0a7a004058a6b10b5cb3374eb82dd1d">02132</a> <span class="preprocessor">#define  CAN_F7R1_FB2                        ((uint32_t)0x00000004)        </span>
<a name="l02133"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga2224329373b490c8dd4f0c148ef58997">02133</a> <span class="preprocessor">#define  CAN_F7R1_FB3                        ((uint32_t)0x00000008)        </span>
<a name="l02134"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gad3574ea4882319ac08e0df065bdd3566">02134</a> <span class="preprocessor">#define  CAN_F7R1_FB4                        ((uint32_t)0x00000010)        </span>
<a name="l02135"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga76f63e712a9a57dacab2874dd695254d">02135</a> <span class="preprocessor">#define  CAN_F7R1_FB5                        ((uint32_t)0x00000020)        </span>
<a name="l02136"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga22d969f17f8a25a63cb056ee2cb622d3">02136</a> <span class="preprocessor">#define  CAN_F7R1_FB6                        ((uint32_t)0x00000040)        </span>
<a name="l02137"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaae89ec51b51c83c108880e361caf17ac">02137</a> <span class="preprocessor">#define  CAN_F7R1_FB7                        ((uint32_t)0x00000080)        </span>
<a name="l02138"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga67fca99c67cab6713605e14d96a9df62">02138</a> <span class="preprocessor">#define  CAN_F7R1_FB8                        ((uint32_t)0x00000100)        </span>
<a name="l02139"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaacd1ef8f0870bc5a5422a6bedbb61d40">02139</a> <span class="preprocessor">#define  CAN_F7R1_FB9                        ((uint32_t)0x00000200)        </span>
<a name="l02140"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaf56408d9914f566396d64609830e2d4f">02140</a> <span class="preprocessor">#define  CAN_F7R1_FB10                       ((uint32_t)0x00000400)        </span>
<a name="l02141"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga65947100832111c7fb427d1982f801eb">02141</a> <span class="preprocessor">#define  CAN_F7R1_FB11                       ((uint32_t)0x00000800)        </span>
<a name="l02142"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga175ed9cdbbf756ec76b9c6fb1f69adff">02142</a> <span class="preprocessor">#define  CAN_F7R1_FB12                       ((uint32_t)0x00001000)        </span>
<a name="l02143"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga91af48b8cd11f119d257311dcf2cc291">02143</a> <span class="preprocessor">#define  CAN_F7R1_FB13                       ((uint32_t)0x00002000)        </span>
<a name="l02144"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga7108bc449a6e328748dd8d2209b83753">02144</a> <span class="preprocessor">#define  CAN_F7R1_FB14                       ((uint32_t)0x00004000)        </span>
<a name="l02145"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gacc47acac1bb59603f58d9aef661d9334">02145</a> <span class="preprocessor">#define  CAN_F7R1_FB15                       ((uint32_t)0x00008000)        </span>
<a name="l02146"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga7b07b4ebfaac9e60d6042b1bff98ec33">02146</a> <span class="preprocessor">#define  CAN_F7R1_FB16                       ((uint32_t)0x00010000)        </span>
<a name="l02147"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gad3328e95d8ae911adc0e5dd4128f8161">02147</a> <span class="preprocessor">#define  CAN_F7R1_FB17                       ((uint32_t)0x00020000)        </span>
<a name="l02148"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga473e4917f35772cd08b06e166d6e475e">02148</a> <span class="preprocessor">#define  CAN_F7R1_FB18                       ((uint32_t)0x00040000)        </span>
<a name="l02149"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaf40a4dd0979fb7ffba4b4192fe6dde5f">02149</a> <span class="preprocessor">#define  CAN_F7R1_FB19                       ((uint32_t)0x00080000)        </span>
<a name="l02150"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga5854aa102655334a6242e43c0b25aede">02150</a> <span class="preprocessor">#define  CAN_F7R1_FB20                       ((uint32_t)0x00100000)        </span>
<a name="l02151"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga505dbdeaf89d103795046fb689b81664">02151</a> <span class="preprocessor">#define  CAN_F7R1_FB21                       ((uint32_t)0x00200000)        </span>
<a name="l02152"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga692f7a0bbc73be14e9d554394dceb176">02152</a> <span class="preprocessor">#define  CAN_F7R1_FB22                       ((uint32_t)0x00400000)        </span>
<a name="l02153"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga5a93f243e7acf3f749f2b6ec8ae7bc5f">02153</a> <span class="preprocessor">#define  CAN_F7R1_FB23                       ((uint32_t)0x00800000)        </span>
<a name="l02154"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga68815c969c231268a63c8809a55bc866">02154</a> <span class="preprocessor">#define  CAN_F7R1_FB24                       ((uint32_t)0x01000000)        </span>
<a name="l02155"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga7055881b4a6d9fe51e8dcfb99a546139">02155</a> <span class="preprocessor">#define  CAN_F7R1_FB25                       ((uint32_t)0x02000000)        </span>
<a name="l02156"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga19ab918d9499635e8199a143833c6fdb">02156</a> <span class="preprocessor">#define  CAN_F7R1_FB26                       ((uint32_t)0x04000000)        </span>
<a name="l02157"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga8360f2a2ba21a1b2f361d4330026edfd">02157</a> <span class="preprocessor">#define  CAN_F7R1_FB27                       ((uint32_t)0x08000000)        </span>
<a name="l02158"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga681e922052442801310265bab7356fc4">02158</a> <span class="preprocessor">#define  CAN_F7R1_FB28                       ((uint32_t)0x10000000)        </span>
<a name="l02159"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gab12aa3a716a85bf96a1496ecaeae0cec">02159</a> <span class="preprocessor">#define  CAN_F7R1_FB29                       ((uint32_t)0x20000000)        </span>
<a name="l02160"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga6774583920f7cd42976daa4cf389eff3">02160</a> <span class="preprocessor">#define  CAN_F7R1_FB30                       ((uint32_t)0x40000000)        </span>
<a name="l02161"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga9990b9fd20bbe0ff114acace0cb47ad7">02161</a> <span class="preprocessor">#define  CAN_F7R1_FB31                       ((uint32_t)0x80000000)        </span>
<a name="l02163"></a>02163 <span class="preprocessor"></span><span class="comment">/*******************  Bit definition for CAN_F8R1 register  *******************/</span>
<a name="l02164"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga13cd870005a4712c3a8b9675a962c642">02164</a> <span class="preprocessor">#define  CAN_F8R1_FB0                        ((uint32_t)0x00000001)        </span>
<a name="l02165"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga49082d55960382ded8b2f7235dd3b33d">02165</a> <span class="preprocessor">#define  CAN_F8R1_FB1                        ((uint32_t)0x00000002)        </span>
<a name="l02166"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gafdb99f376b40d3933ce6a28ad31f496a">02166</a> <span class="preprocessor">#define  CAN_F8R1_FB2                        ((uint32_t)0x00000004)        </span>
<a name="l02167"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga2cd97fc37fa6ffadbb7af4f9ddf1d014">02167</a> <span class="preprocessor">#define  CAN_F8R1_FB3                        ((uint32_t)0x00000008)        </span>
<a name="l02168"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga5842614b55172086992fc085955168d7">02168</a> <span class="preprocessor">#define  CAN_F8R1_FB4                        ((uint32_t)0x00000010)        </span>
<a name="l02169"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga373c77cab88912e816a6e12195bd3205">02169</a> <span class="preprocessor">#define  CAN_F8R1_FB5                        ((uint32_t)0x00000020)        </span>
<a name="l02170"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga5937607627dd44c4fb79f9063534e2b1">02170</a> <span class="preprocessor">#define  CAN_F8R1_FB6                        ((uint32_t)0x00000040)        </span>
<a name="l02171"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga5b6765194a47f1a6d7dfbf78e0b4139c">02171</a> <span class="preprocessor">#define  CAN_F8R1_FB7                        ((uint32_t)0x00000080)        </span>
<a name="l02172"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaa79159b413994d12b593cc4f1b23d1fa">02172</a> <span class="preprocessor">#define  CAN_F8R1_FB8                        ((uint32_t)0x00000100)        </span>
<a name="l02173"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga2b959e903cdac33f5da71aa5c7477a0d">02173</a> <span class="preprocessor">#define  CAN_F8R1_FB9                        ((uint32_t)0x00000200)        </span>
<a name="l02174"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gab5de7f304ca7bfcb9e78c9c2d346d300">02174</a> <span class="preprocessor">#define  CAN_F8R1_FB10                       ((uint32_t)0x00000400)        </span>
<a name="l02175"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga0d5a19fa7032ef2b68e2feebd0db15e6">02175</a> <span class="preprocessor">#define  CAN_F8R1_FB11                       ((uint32_t)0x00000800)        </span>
<a name="l02176"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga943a685663474ed7aa509eaccbda2ffb">02176</a> <span class="preprocessor">#define  CAN_F8R1_FB12                       ((uint32_t)0x00001000)        </span>
<a name="l02177"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga668cb8a75c4166b5287a09ba98c8ec70">02177</a> <span class="preprocessor">#define  CAN_F8R1_FB13                       ((uint32_t)0x00002000)        </span>
<a name="l02178"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga84727d6a0fdcb2870529d7a371a0b660">02178</a> <span class="preprocessor">#define  CAN_F8R1_FB14                       ((uint32_t)0x00004000)        </span>
<a name="l02179"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga9eb9c851eb03c49bc02f686aee490a28">02179</a> <span class="preprocessor">#define  CAN_F8R1_FB15                       ((uint32_t)0x00008000)        </span>
<a name="l02180"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga4ccc46770c70da8546bbbcf492bcdd95">02180</a> <span class="preprocessor">#define  CAN_F8R1_FB16                       ((uint32_t)0x00010000)        </span>
<a name="l02181"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaf24b0628e89b2c27cb9e13b0492876eb">02181</a> <span class="preprocessor">#define  CAN_F8R1_FB17                       ((uint32_t)0x00020000)        </span>
<a name="l02182"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga36b946c123c3c3f1cdbd1272db24c58b">02182</a> <span class="preprocessor">#define  CAN_F8R1_FB18                       ((uint32_t)0x00040000)        </span>
<a name="l02183"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gab91129b8b7746111a31a968c1f1a8b19">02183</a> <span class="preprocessor">#define  CAN_F8R1_FB19                       ((uint32_t)0x00080000)        </span>
<a name="l02184"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga19663b29868ae926896961451768d748">02184</a> <span class="preprocessor">#define  CAN_F8R1_FB20                       ((uint32_t)0x00100000)        </span>
<a name="l02185"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga19d8c89621a78de5177481d217bb5033">02185</a> <span class="preprocessor">#define  CAN_F8R1_FB21                       ((uint32_t)0x00200000)        </span>
<a name="l02186"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gab265fadfeb8674b869264ad25bedcac4">02186</a> <span class="preprocessor">#define  CAN_F8R1_FB22                       ((uint32_t)0x00400000)        </span>
<a name="l02187"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga102fdb92fecd6aa86e5dbd2fea2b2e79">02187</a> <span class="preprocessor">#define  CAN_F8R1_FB23                       ((uint32_t)0x00800000)        </span>
<a name="l02188"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga0b73f4ab4941e6d920e75f7197ed025b">02188</a> <span class="preprocessor">#define  CAN_F8R1_FB24                       ((uint32_t)0x01000000)        </span>
<a name="l02189"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga9d72a1b4728fa13d4a2a3f7478f8398b">02189</a> <span class="preprocessor">#define  CAN_F8R1_FB25                       ((uint32_t)0x02000000)        </span>
<a name="l02190"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga5826d272442cf9b69336172a039bc439">02190</a> <span class="preprocessor">#define  CAN_F8R1_FB26                       ((uint32_t)0x04000000)        </span>
<a name="l02191"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gacdb656881f89c0da122383403a816ce1">02191</a> <span class="preprocessor">#define  CAN_F8R1_FB27                       ((uint32_t)0x08000000)        </span>
<a name="l02192"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga2d8c536aab73553ff1913ba806be351c">02192</a> <span class="preprocessor">#define  CAN_F8R1_FB28                       ((uint32_t)0x10000000)        </span>
<a name="l02193"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga8fb8328cdbf23c9982b769bd39a24113">02193</a> <span class="preprocessor">#define  CAN_F8R1_FB29                       ((uint32_t)0x20000000)        </span>
<a name="l02194"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga78861665c78657330f9fcfc17283529f">02194</a> <span class="preprocessor">#define  CAN_F8R1_FB30                       ((uint32_t)0x40000000)        </span>
<a name="l02195"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga6b2fa38175302b2d91f2b45ae16c5db7">02195</a> <span class="preprocessor">#define  CAN_F8R1_FB31                       ((uint32_t)0x80000000)        </span>
<a name="l02197"></a>02197 <span class="preprocessor"></span><span class="comment">/*******************  Bit definition for CAN_F9R1 register  *******************/</span>
<a name="l02198"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga930a17d830cb9a95a79531dac2220785">02198</a> <span class="preprocessor">#define  CAN_F9R1_FB0                        ((uint32_t)0x00000001)        </span>
<a name="l02199"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga8671eac978ebea75e6345adbcdf78026">02199</a> <span class="preprocessor">#define  CAN_F9R1_FB1                        ((uint32_t)0x00000002)        </span>
<a name="l02200"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaee3585fb5ee4081dffeb2a2dda1ce72f">02200</a> <span class="preprocessor">#define  CAN_F9R1_FB2                        ((uint32_t)0x00000004)        </span>
<a name="l02201"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga807e831fafa69e9df65618de855ea186">02201</a> <span class="preprocessor">#define  CAN_F9R1_FB3                        ((uint32_t)0x00000008)        </span>
<a name="l02202"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaddce646e28626a508b2f98c4f35148b3">02202</a> <span class="preprocessor">#define  CAN_F9R1_FB4                        ((uint32_t)0x00000010)        </span>
<a name="l02203"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga9ea72662e0243714ace5c0b48e7912f6">02203</a> <span class="preprocessor">#define  CAN_F9R1_FB5                        ((uint32_t)0x00000020)        </span>
<a name="l02204"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga6b08ddbc0bed91c6a1933e6485ded5e2">02204</a> <span class="preprocessor">#define  CAN_F9R1_FB6                        ((uint32_t)0x00000040)        </span>
<a name="l02205"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gae21fd9c8c790d4bc229c7ccb6d99dd36">02205</a> <span class="preprocessor">#define  CAN_F9R1_FB7                        ((uint32_t)0x00000080)        </span>
<a name="l02206"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gadf1a8f02576caccfddc12f2ead734762">02206</a> <span class="preprocessor">#define  CAN_F9R1_FB8                        ((uint32_t)0x00000100)        </span>
<a name="l02207"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga80a2594aaa275fd88225927e7115085b">02207</a> <span class="preprocessor">#define  CAN_F9R1_FB9                        ((uint32_t)0x00000200)        </span>
<a name="l02208"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga3db445a3214057317d84269116c9a3de">02208</a> <span class="preprocessor">#define  CAN_F9R1_FB10                       ((uint32_t)0x00000400)        </span>
<a name="l02209"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gadf09c1d038af593122315a878c15f608">02209</a> <span class="preprocessor">#define  CAN_F9R1_FB11                       ((uint32_t)0x00000800)        </span>
<a name="l02210"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga12b2a29143ddf47eb1eddf76f9289cb9">02210</a> <span class="preprocessor">#define  CAN_F9R1_FB12                       ((uint32_t)0x00001000)        </span>
<a name="l02211"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga691bc907b71c30dffdf246c95240ac9b">02211</a> <span class="preprocessor">#define  CAN_F9R1_FB13                       ((uint32_t)0x00002000)        </span>
<a name="l02212"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaf8669ceaa46f5aecada88accedfb4dbb">02212</a> <span class="preprocessor">#define  CAN_F9R1_FB14                       ((uint32_t)0x00004000)        </span>
<a name="l02213"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga35e8769a1e21c4cf3714667e07201804">02213</a> <span class="preprocessor">#define  CAN_F9R1_FB15                       ((uint32_t)0x00008000)        </span>
<a name="l02214"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gad7060a1863aa5b08ce8469001d46c630">02214</a> <span class="preprocessor">#define  CAN_F9R1_FB16                       ((uint32_t)0x00010000)        </span>
<a name="l02215"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gacf015fb7231bd315f82948019dcfc725">02215</a> <span class="preprocessor">#define  CAN_F9R1_FB17                       ((uint32_t)0x00020000)        </span>
<a name="l02216"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga02c06b01abb3414394747a7cf8eac888">02216</a> <span class="preprocessor">#define  CAN_F9R1_FB18                       ((uint32_t)0x00040000)        </span>
<a name="l02217"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga99a1a20417252e33a4817c0530745239">02217</a> <span class="preprocessor">#define  CAN_F9R1_FB19                       ((uint32_t)0x00080000)        </span>
<a name="l02218"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga09c0f503e2ef85b3b6332ccbca7b0251">02218</a> <span class="preprocessor">#define  CAN_F9R1_FB20                       ((uint32_t)0x00100000)        </span>
<a name="l02219"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gacab12d06dee3d6dad5fd7c56c23c70d1">02219</a> <span class="preprocessor">#define  CAN_F9R1_FB21                       ((uint32_t)0x00200000)        </span>
<a name="l02220"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga5c72a8d17db1de69086f19579b169c04">02220</a> <span class="preprocessor">#define  CAN_F9R1_FB22                       ((uint32_t)0x00400000)        </span>
<a name="l02221"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga4bb3ba674ec6c82ed108f6c0bfb2f854">02221</a> <span class="preprocessor">#define  CAN_F9R1_FB23                       ((uint32_t)0x00800000)        </span>
<a name="l02222"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaba13bd7fa1e4c2eaef3de31d933cbc10">02222</a> <span class="preprocessor">#define  CAN_F9R1_FB24                       ((uint32_t)0x01000000)        </span>
<a name="l02223"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaa72247fe16d8f777c26726063fa43536">02223</a> <span class="preprocessor">#define  CAN_F9R1_FB25                       ((uint32_t)0x02000000)        </span>
<a name="l02224"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga32d7c1678449ff8f4e4b6f548ba85be4">02224</a> <span class="preprocessor">#define  CAN_F9R1_FB26                       ((uint32_t)0x04000000)        </span>
<a name="l02225"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga678d4a0a39b379db5c2e0285782c686f">02225</a> <span class="preprocessor">#define  CAN_F9R1_FB27                       ((uint32_t)0x08000000)        </span>
<a name="l02226"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga6033aa5f4d140dc48ddb4a777583163c">02226</a> <span class="preprocessor">#define  CAN_F9R1_FB28                       ((uint32_t)0x10000000)        </span>
<a name="l02227"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga9fda159c684d7361094da1883473b544">02227</a> <span class="preprocessor">#define  CAN_F9R1_FB29                       ((uint32_t)0x20000000)        </span>
<a name="l02228"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga83cf4080564c51a0123b97840576c0ab">02228</a> <span class="preprocessor">#define  CAN_F9R1_FB30                       ((uint32_t)0x40000000)        </span>
<a name="l02229"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga127c155bc5c5236f04cfdcf96ff66cc5">02229</a> <span class="preprocessor">#define  CAN_F9R1_FB31                       ((uint32_t)0x80000000)        </span>
<a name="l02231"></a>02231 <span class="preprocessor"></span><span class="comment">/*******************  Bit definition for CAN_F10R1 register  ******************/</span>
<a name="l02232"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga1d5b5b7bc147da430d9c8fbe03679ca3">02232</a> <span class="preprocessor">#define  CAN_F10R1_FB0                       ((uint32_t)0x00000001)        </span>
<a name="l02233"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga3ed7be0180fd7096f10cfde27261ecc9">02233</a> <span class="preprocessor">#define  CAN_F10R1_FB1                       ((uint32_t)0x00000002)        </span>
<a name="l02234"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gad099442eb6b71912a81d1f6fccbaec0a">02234</a> <span class="preprocessor">#define  CAN_F10R1_FB2                       ((uint32_t)0x00000004)        </span>
<a name="l02235"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga4024c53b7b0cec550baed99ae92e3465">02235</a> <span class="preprocessor">#define  CAN_F10R1_FB3                       ((uint32_t)0x00000008)        </span>
<a name="l02236"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga1859eaac9ae1220c752218e5ad526179">02236</a> <span class="preprocessor">#define  CAN_F10R1_FB4                       ((uint32_t)0x00000010)        </span>
<a name="l02237"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga5683dc25f0aae9a802a5f57c88bec856">02237</a> <span class="preprocessor">#define  CAN_F10R1_FB5                       ((uint32_t)0x00000020)        </span>
<a name="l02238"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gae83dd9ce8a2c7917e278ce4755f8f43e">02238</a> <span class="preprocessor">#define  CAN_F10R1_FB6                       ((uint32_t)0x00000040)        </span>
<a name="l02239"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga93ad070c9f5abca3c9b9095e3a13db9c">02239</a> <span class="preprocessor">#define  CAN_F10R1_FB7                       ((uint32_t)0x00000080)        </span>
<a name="l02240"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gadd32db3ffec3536cd842e17c34c210d9">02240</a> <span class="preprocessor">#define  CAN_F10R1_FB8                       ((uint32_t)0x00000100)        </span>
<a name="l02241"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga85673ce7a92ae8ca9a13ed2fb5574a76">02241</a> <span class="preprocessor">#define  CAN_F10R1_FB9                       ((uint32_t)0x00000200)        </span>
<a name="l02242"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga6d525825fe4bfc1d4ffccc21ab89a3fa">02242</a> <span class="preprocessor">#define  CAN_F10R1_FB10                      ((uint32_t)0x00000400)        </span>
<a name="l02243"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga33336e283eeee9b77f1f289d77f2304e">02243</a> <span class="preprocessor">#define  CAN_F10R1_FB11                      ((uint32_t)0x00000800)        </span>
<a name="l02244"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gadf74ee01e72b3de69d6e8fcc092f7461">02244</a> <span class="preprocessor">#define  CAN_F10R1_FB12                      ((uint32_t)0x00001000)        </span>
<a name="l02245"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga8ee416ff22b47bb289bab34afbc74f19">02245</a> <span class="preprocessor">#define  CAN_F10R1_FB13                      ((uint32_t)0x00002000)        </span>
<a name="l02246"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga97a8d8586c64910b0f6c09fef44c4ea7">02246</a> <span class="preprocessor">#define  CAN_F10R1_FB14                      ((uint32_t)0x00004000)        </span>
<a name="l02247"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gab9e8e43adc56ba1e593b97e062c79075">02247</a> <span class="preprocessor">#define  CAN_F10R1_FB15                      ((uint32_t)0x00008000)        </span>
<a name="l02248"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaa64a0b16c073b51cb5e90b94c638fd95">02248</a> <span class="preprocessor">#define  CAN_F10R1_FB16                      ((uint32_t)0x00010000)        </span>
<a name="l02249"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga65f5cc396cfcf3bad71a71326e64f7d9">02249</a> <span class="preprocessor">#define  CAN_F10R1_FB17                      ((uint32_t)0x00020000)        </span>
<a name="l02250"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga424940f535aa9a1520e25df53673d01f">02250</a> <span class="preprocessor">#define  CAN_F10R1_FB18                      ((uint32_t)0x00040000)        </span>
<a name="l02251"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga166a4035770c58147d583c3dc571d10a">02251</a> <span class="preprocessor">#define  CAN_F10R1_FB19                      ((uint32_t)0x00080000)        </span>
<a name="l02252"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga302214ece439e8913b47949bd07d118a">02252</a> <span class="preprocessor">#define  CAN_F10R1_FB20                      ((uint32_t)0x00100000)        </span>
<a name="l02253"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gad9abe6ae1dcb2bd140e7e28d37fd8abb">02253</a> <span class="preprocessor">#define  CAN_F10R1_FB21                      ((uint32_t)0x00200000)        </span>
<a name="l02254"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga99063956b41c4dcf6c78cc29305b1cd1">02254</a> <span class="preprocessor">#define  CAN_F10R1_FB22                      ((uint32_t)0x00400000)        </span>
<a name="l02255"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga81ae64786c3a83bdd21cf72c560c7c1e">02255</a> <span class="preprocessor">#define  CAN_F10R1_FB23                      ((uint32_t)0x00800000)        </span>
<a name="l02256"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga0f9083faf8395701c892814694b45d2c">02256</a> <span class="preprocessor">#define  CAN_F10R1_FB24                      ((uint32_t)0x01000000)        </span>
<a name="l02257"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaaeb6942affe306b407940fdf01534e4a">02257</a> <span class="preprocessor">#define  CAN_F10R1_FB25                      ((uint32_t)0x02000000)        </span>
<a name="l02258"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga1e4ee946a9614316f666852bc266c1f7">02258</a> <span class="preprocessor">#define  CAN_F10R1_FB26                      ((uint32_t)0x04000000)        </span>
<a name="l02259"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga99153cddc8fc7e846fcc44383936541f">02259</a> <span class="preprocessor">#define  CAN_F10R1_FB27                      ((uint32_t)0x08000000)        </span>
<a name="l02260"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga0e2ba1740577246368e60d94fd3d7c69">02260</a> <span class="preprocessor">#define  CAN_F10R1_FB28                      ((uint32_t)0x10000000)        </span>
<a name="l02261"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaca062686821fba26a0e5e5b0a6c5b855">02261</a> <span class="preprocessor">#define  CAN_F10R1_FB29                      ((uint32_t)0x20000000)        </span>
<a name="l02262"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga8981f420ef4c8fe1976a09f27a9c13f1">02262</a> <span class="preprocessor">#define  CAN_F10R1_FB30                      ((uint32_t)0x40000000)        </span>
<a name="l02263"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga0424bf38917058b166a8bfd861d22b40">02263</a> <span class="preprocessor">#define  CAN_F10R1_FB31                      ((uint32_t)0x80000000)        </span>
<a name="l02265"></a>02265 <span class="preprocessor"></span><span class="comment">/*******************  Bit definition for CAN_F11R1 register  ******************/</span>
<a name="l02266"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gad059cc9b2fe5634b9330b44c37dadf06">02266</a> <span class="preprocessor">#define  CAN_F11R1_FB0                       ((uint32_t)0x00000001)        </span>
<a name="l02267"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gad74b116cda63fcd1a662c4de835616e7">02267</a> <span class="preprocessor">#define  CAN_F11R1_FB1                       ((uint32_t)0x00000002)        </span>
<a name="l02268"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga4e05bb0c2a5bdcebb974f7dd409724bc">02268</a> <span class="preprocessor">#define  CAN_F11R1_FB2                       ((uint32_t)0x00000004)        </span>
<a name="l02269"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaa17242aed4365034dc660ef9e8b9f1bf">02269</a> <span class="preprocessor">#define  CAN_F11R1_FB3                       ((uint32_t)0x00000008)        </span>
<a name="l02270"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga450dbed19882423d70ed7606aada2453">02270</a> <span class="preprocessor">#define  CAN_F11R1_FB4                       ((uint32_t)0x00000010)        </span>
<a name="l02271"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gad7ace73f2d3db1e2a1e55257d210fa04">02271</a> <span class="preprocessor">#define  CAN_F11R1_FB5                       ((uint32_t)0x00000020)        </span>
<a name="l02272"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga1459d395a3b08a948c3f5002e0914516">02272</a> <span class="preprocessor">#define  CAN_F11R1_FB6                       ((uint32_t)0x00000040)        </span>
<a name="l02273"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga30fc2236c2a18b7cb6e493fad36d8efe">02273</a> <span class="preprocessor">#define  CAN_F11R1_FB7                       ((uint32_t)0x00000080)        </span>
<a name="l02274"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga74ab4a6f6b5a751acda410e0c39b87af">02274</a> <span class="preprocessor">#define  CAN_F11R1_FB8                       ((uint32_t)0x00000100)        </span>
<a name="l02275"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga4e69f7001534264fd027371fa188ac52">02275</a> <span class="preprocessor">#define  CAN_F11R1_FB9                       ((uint32_t)0x00000200)        </span>
<a name="l02276"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga1e858dd29f741910c8ed8c512cae81b1">02276</a> <span class="preprocessor">#define  CAN_F11R1_FB10                      ((uint32_t)0x00000400)        </span>
<a name="l02277"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaf6ba167c6cd5bc080065430e24c3a866">02277</a> <span class="preprocessor">#define  CAN_F11R1_FB11                      ((uint32_t)0x00000800)        </span>
<a name="l02278"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga4629ab1e8632c82f3fb2648a574963b1">02278</a> <span class="preprocessor">#define  CAN_F11R1_FB12                      ((uint32_t)0x00001000)        </span>
<a name="l02279"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga833c408a165cc4ac87a242c08d4ba9b9">02279</a> <span class="preprocessor">#define  CAN_F11R1_FB13                      ((uint32_t)0x00002000)        </span>
<a name="l02280"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gabfecd6bbe1a15cd341942d1840b476cc">02280</a> <span class="preprocessor">#define  CAN_F11R1_FB14                      ((uint32_t)0x00004000)        </span>
<a name="l02281"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaf50e1747d1d9369b7b22c5d591ae82b9">02281</a> <span class="preprocessor">#define  CAN_F11R1_FB15                      ((uint32_t)0x00008000)        </span>
<a name="l02282"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga603d63333a621594a15696cb03f59eeb">02282</a> <span class="preprocessor">#define  CAN_F11R1_FB16                      ((uint32_t)0x00010000)        </span>
<a name="l02283"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gadb361a00177e6aa2ee19aa5a2d1781aa">02283</a> <span class="preprocessor">#define  CAN_F11R1_FB17                      ((uint32_t)0x00020000)        </span>
<a name="l02284"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaf111110e0f5dbda31962f7732e3480c7">02284</a> <span class="preprocessor">#define  CAN_F11R1_FB18                      ((uint32_t)0x00040000)        </span>
<a name="l02285"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gabf2c4828b07b2b315d27b382818de285">02285</a> <span class="preprocessor">#define  CAN_F11R1_FB19                      ((uint32_t)0x00080000)        </span>
<a name="l02286"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga5afa52941bb68a03ec9804b817d5a90e">02286</a> <span class="preprocessor">#define  CAN_F11R1_FB20                      ((uint32_t)0x00100000)        </span>
<a name="l02287"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gac042471dbcb1a32ce161f38a144ac5aa">02287</a> <span class="preprocessor">#define  CAN_F11R1_FB21                      ((uint32_t)0x00200000)        </span>
<a name="l02288"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaac46f233c9692cb2a2e246daf6547a38">02288</a> <span class="preprocessor">#define  CAN_F11R1_FB22                      ((uint32_t)0x00400000)        </span>
<a name="l02289"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gab8b379e3832482f2b18f01713d3338d5">02289</a> <span class="preprocessor">#define  CAN_F11R1_FB23                      ((uint32_t)0x00800000)        </span>
<a name="l02290"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga60eabd8db9ec6b439d60dbc2374ce84d">02290</a> <span class="preprocessor">#define  CAN_F11R1_FB24                      ((uint32_t)0x01000000)        </span>
<a name="l02291"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga351a183cfab10d3daab415c85cc16203">02291</a> <span class="preprocessor">#define  CAN_F11R1_FB25                      ((uint32_t)0x02000000)        </span>
<a name="l02292"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gabb854a85c7a575a45cdade37efb4edee">02292</a> <span class="preprocessor">#define  CAN_F11R1_FB26                      ((uint32_t)0x04000000)        </span>
<a name="l02293"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga131776c359f81500d3d2a97535d7e718">02293</a> <span class="preprocessor">#define  CAN_F11R1_FB27                      ((uint32_t)0x08000000)        </span>
<a name="l02294"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga680d7e4c7ebc431a8c72c00e9f110563">02294</a> <span class="preprocessor">#define  CAN_F11R1_FB28                      ((uint32_t)0x10000000)        </span>
<a name="l02295"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga9c1fa00ee18804c169541d18995dc3c1">02295</a> <span class="preprocessor">#define  CAN_F11R1_FB29                      ((uint32_t)0x20000000)        </span>
<a name="l02296"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaec35d8d1097816c5ef8e28ff61469669">02296</a> <span class="preprocessor">#define  CAN_F11R1_FB30                      ((uint32_t)0x40000000)        </span>
<a name="l02297"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga96180b8c64aabd33f016fb97ba152f07">02297</a> <span class="preprocessor">#define  CAN_F11R1_FB31                      ((uint32_t)0x80000000)        </span>
<a name="l02299"></a>02299 <span class="preprocessor"></span><span class="comment">/*******************  Bit definition for CAN_F12R1 register  ******************/</span>
<a name="l02300"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaccbe3637fb55f28496ca7f692a69f6ca">02300</a> <span class="preprocessor">#define  CAN_F12R1_FB0                       ((uint32_t)0x00000001)        </span>
<a name="l02301"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gae625d21947ae82cc3509b06363ad0635">02301</a> <span class="preprocessor">#define  CAN_F12R1_FB1                       ((uint32_t)0x00000002)        </span>
<a name="l02302"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga9de7cc313f2b6b16a564b13b1bc30157">02302</a> <span class="preprocessor">#define  CAN_F12R1_FB2                       ((uint32_t)0x00000004)        </span>
<a name="l02303"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gac039cc1ce2281cf10be62cbc44748f5f">02303</a> <span class="preprocessor">#define  CAN_F12R1_FB3                       ((uint32_t)0x00000008)        </span>
<a name="l02304"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gabc3a35b6f6b3a46c176398ec322fd6fb">02304</a> <span class="preprocessor">#define  CAN_F12R1_FB4                       ((uint32_t)0x00000010)        </span>
<a name="l02305"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga4d005c10fe75169336104c3155294000">02305</a> <span class="preprocessor">#define  CAN_F12R1_FB5                       ((uint32_t)0x00000020)        </span>
<a name="l02306"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga51256bfed734a95da3e7880e279432bf">02306</a> <span class="preprocessor">#define  CAN_F12R1_FB6                       ((uint32_t)0x00000040)        </span>
<a name="l02307"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga2c967f124b03968372d801e1393fa209">02307</a> <span class="preprocessor">#define  CAN_F12R1_FB7                       ((uint32_t)0x00000080)        </span>
<a name="l02308"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga592f9953deeb56888144c72060d04e24">02308</a> <span class="preprocessor">#define  CAN_F12R1_FB8                       ((uint32_t)0x00000100)        </span>
<a name="l02309"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga4d1613eac2aaeafda711cf3308ccd44c">02309</a> <span class="preprocessor">#define  CAN_F12R1_FB9                       ((uint32_t)0x00000200)        </span>
<a name="l02310"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga1b8594ab0c5d9124accd2d6ca85cf4bd">02310</a> <span class="preprocessor">#define  CAN_F12R1_FB10                      ((uint32_t)0x00000400)        </span>
<a name="l02311"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga4025ed76892f23e5a63d0d8ac6a2be5f">02311</a> <span class="preprocessor">#define  CAN_F12R1_FB11                      ((uint32_t)0x00000800)        </span>
<a name="l02312"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga6e2e318cc14828c118bd40d982922e14">02312</a> <span class="preprocessor">#define  CAN_F12R1_FB12                      ((uint32_t)0x00001000)        </span>
<a name="l02313"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga4e0ff698b5e9f3f99a421166611b041d">02313</a> <span class="preprocessor">#define  CAN_F12R1_FB13                      ((uint32_t)0x00002000)        </span>
<a name="l02314"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga6b0666538a7646ddc0fcd882a261f5d9">02314</a> <span class="preprocessor">#define  CAN_F12R1_FB14                      ((uint32_t)0x00004000)        </span>
<a name="l02315"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga846d84b3d53e305b093198379f442528">02315</a> <span class="preprocessor">#define  CAN_F12R1_FB15                      ((uint32_t)0x00008000)        </span>
<a name="l02316"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gad7940c0898c2ef1d9f829bf1b6b5fcf3">02316</a> <span class="preprocessor">#define  CAN_F12R1_FB16                      ((uint32_t)0x00010000)        </span>
<a name="l02317"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga6bdc7bd4dbad1f8e3bb622343bd7c522">02317</a> <span class="preprocessor">#define  CAN_F12R1_FB17                      ((uint32_t)0x00020000)        </span>
<a name="l02318"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga7c870a6fbae41b4f1c6d66ab690789d6">02318</a> <span class="preprocessor">#define  CAN_F12R1_FB18                      ((uint32_t)0x00040000)        </span>
<a name="l02319"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga09e179b38460e47b81616c46a5f356f8">02319</a> <span class="preprocessor">#define  CAN_F12R1_FB19                      ((uint32_t)0x00080000)        </span>
<a name="l02320"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gad42e298d4d97c98cc5149bc552a598fa">02320</a> <span class="preprocessor">#define  CAN_F12R1_FB20                      ((uint32_t)0x00100000)        </span>
<a name="l02321"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga318e2a6ae62d5172dcdb45e011d5e0c4">02321</a> <span class="preprocessor">#define  CAN_F12R1_FB21                      ((uint32_t)0x00200000)        </span>
<a name="l02322"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga90e95cb0020289335acd5d7f4b62a880">02322</a> <span class="preprocessor">#define  CAN_F12R1_FB22                      ((uint32_t)0x00400000)        </span>
<a name="l02323"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga2e2720e18fdff00c9fb75d5136e485dc">02323</a> <span class="preprocessor">#define  CAN_F12R1_FB23                      ((uint32_t)0x00800000)        </span>
<a name="l02324"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gae4a87123ae5ff76992162152fbb4c92a">02324</a> <span class="preprocessor">#define  CAN_F12R1_FB24                      ((uint32_t)0x01000000)        </span>
<a name="l02325"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga9582717e16455f97c7dff65f7beadd6e">02325</a> <span class="preprocessor">#define  CAN_F12R1_FB25                      ((uint32_t)0x02000000)        </span>
<a name="l02326"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaf15e362beb5a3b733c08c8c2ab81efcb">02326</a> <span class="preprocessor">#define  CAN_F12R1_FB26                      ((uint32_t)0x04000000)        </span>
<a name="l02327"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga3d600a7a39c7069c216db511d3a5d866">02327</a> <span class="preprocessor">#define  CAN_F12R1_FB27                      ((uint32_t)0x08000000)        </span>
<a name="l02328"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gab9a6addc248c6db2118d1ce6e049d331">02328</a> <span class="preprocessor">#define  CAN_F12R1_FB28                      ((uint32_t)0x10000000)        </span>
<a name="l02329"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga31d3a46845cd9ca6670472aae2aa2ebe">02329</a> <span class="preprocessor">#define  CAN_F12R1_FB29                      ((uint32_t)0x20000000)        </span>
<a name="l02330"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaa06596dcbb545fbeea2ec20f629d9555">02330</a> <span class="preprocessor">#define  CAN_F12R1_FB30                      ((uint32_t)0x40000000)        </span>
<a name="l02331"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gac441b11b1be9b3608b9a09c2b8069722">02331</a> <span class="preprocessor">#define  CAN_F12R1_FB31                      ((uint32_t)0x80000000)        </span>
<a name="l02333"></a>02333 <span class="preprocessor"></span><span class="comment">/*******************  Bit definition for CAN_F13R1 register  ******************/</span>
<a name="l02334"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaa20d063950ad122a1965527a17d93c37">02334</a> <span class="preprocessor">#define  CAN_F13R1_FB0                       ((uint32_t)0x00000001)        </span>
<a name="l02335"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaf60decd61c8a8dc9e4342de8ad67ea76">02335</a> <span class="preprocessor">#define  CAN_F13R1_FB1                       ((uint32_t)0x00000002)        </span>
<a name="l02336"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga7863b3af06385d0e9037c57a5d2091e2">02336</a> <span class="preprocessor">#define  CAN_F13R1_FB2                       ((uint32_t)0x00000004)        </span>
<a name="l02337"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga043282b30813ce88dbdb320936ff6aca">02337</a> <span class="preprocessor">#define  CAN_F13R1_FB3                       ((uint32_t)0x00000008)        </span>
<a name="l02338"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga3bbc9e9866f20d9d2f3cea1c6777c673">02338</a> <span class="preprocessor">#define  CAN_F13R1_FB4                       ((uint32_t)0x00000010)        </span>
<a name="l02339"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga885b36e017b013ab6deedd91d9ac2c66">02339</a> <span class="preprocessor">#define  CAN_F13R1_FB5                       ((uint32_t)0x00000020)        </span>
<a name="l02340"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaa389b53582e5cacf326fff4512626d68">02340</a> <span class="preprocessor">#define  CAN_F13R1_FB6                       ((uint32_t)0x00000040)        </span>
<a name="l02341"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gad09b75feeda08b16962db7da6a32dc9b">02341</a> <span class="preprocessor">#define  CAN_F13R1_FB7                       ((uint32_t)0x00000080)        </span>
<a name="l02342"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaaba75675c019979882ecd8c6ef82d7a4">02342</a> <span class="preprocessor">#define  CAN_F13R1_FB8                       ((uint32_t)0x00000100)        </span>
<a name="l02343"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gac579473f666edec0e0fcce278b642a9d">02343</a> <span class="preprocessor">#define  CAN_F13R1_FB9                       ((uint32_t)0x00000200)        </span>
<a name="l02344"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga14640c225c434428ef1870f462eb9bbd">02344</a> <span class="preprocessor">#define  CAN_F13R1_FB10                      ((uint32_t)0x00000400)        </span>
<a name="l02345"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga7d8c9f5879cc4e31fe2e63f82febbc69">02345</a> <span class="preprocessor">#define  CAN_F13R1_FB11                      ((uint32_t)0x00000800)        </span>
<a name="l02346"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga8e0e3cfe033bb34f62312cfe47d1b84a">02346</a> <span class="preprocessor">#define  CAN_F13R1_FB12                      ((uint32_t)0x00001000)        </span>
<a name="l02347"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga93d91a28c1ffca3f72f10e0b44040791">02347</a> <span class="preprocessor">#define  CAN_F13R1_FB13                      ((uint32_t)0x00002000)        </span>
<a name="l02348"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga355b438a5abccec89e13bdd00206b36f">02348</a> <span class="preprocessor">#define  CAN_F13R1_FB14                      ((uint32_t)0x00004000)        </span>
<a name="l02349"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga89b23d147d2c040eb2317633b3ef46da">02349</a> <span class="preprocessor">#define  CAN_F13R1_FB15                      ((uint32_t)0x00008000)        </span>
<a name="l02350"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga81d184cd46306fe24b46087a90e8f8f2">02350</a> <span class="preprocessor">#define  CAN_F13R1_FB16                      ((uint32_t)0x00010000)        </span>
<a name="l02351"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga151a0e903046edc92bddcd0ef4a23449">02351</a> <span class="preprocessor">#define  CAN_F13R1_FB17                      ((uint32_t)0x00020000)        </span>
<a name="l02352"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga9e95e6d0d060fb2cfdf31e1b5fdfe3de">02352</a> <span class="preprocessor">#define  CAN_F13R1_FB18                      ((uint32_t)0x00040000)        </span>
<a name="l02353"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga1e0fb1cf032c57f954dd2679a05f8115">02353</a> <span class="preprocessor">#define  CAN_F13R1_FB19                      ((uint32_t)0x00080000)        </span>
<a name="l02354"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaeb775bb1ded6a8f55f2a0849bec2eeac">02354</a> <span class="preprocessor">#define  CAN_F13R1_FB20                      ((uint32_t)0x00100000)        </span>
<a name="l02355"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga8743dfb60255d98911ea66605efd3b2f">02355</a> <span class="preprocessor">#define  CAN_F13R1_FB21                      ((uint32_t)0x00200000)        </span>
<a name="l02356"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga54b067c38f3be3ad6041ea12fec15700">02356</a> <span class="preprocessor">#define  CAN_F13R1_FB22                      ((uint32_t)0x00400000)        </span>
<a name="l02357"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga00fe1942d9a8767a76f139bd74eafea0">02357</a> <span class="preprocessor">#define  CAN_F13R1_FB23                      ((uint32_t)0x00800000)        </span>
<a name="l02358"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga05db1c0a2e6e051d616b59f386dc7b1e">02358</a> <span class="preprocessor">#define  CAN_F13R1_FB24                      ((uint32_t)0x01000000)        </span>
<a name="l02359"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga66dd0da9fd8ef27b30f1ad56a9982caf">02359</a> <span class="preprocessor">#define  CAN_F13R1_FB25                      ((uint32_t)0x02000000)        </span>
<a name="l02360"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaf3b8381bc6ce5ab107cc1a92e565387a">02360</a> <span class="preprocessor">#define  CAN_F13R1_FB26                      ((uint32_t)0x04000000)        </span>
<a name="l02361"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga91c99de5ae099ecdee50ebd62e552df5">02361</a> <span class="preprocessor">#define  CAN_F13R1_FB27                      ((uint32_t)0x08000000)        </span>
<a name="l02362"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga83713f9e2c3c90f001ab378d9ca1f488">02362</a> <span class="preprocessor">#define  CAN_F13R1_FB28                      ((uint32_t)0x10000000)        </span>
<a name="l02363"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga050fb1e9555d0d24f81682e194677684">02363</a> <span class="preprocessor">#define  CAN_F13R1_FB29                      ((uint32_t)0x20000000)        </span>
<a name="l02364"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga761164856a25bc246396c7c82fdeb447">02364</a> <span class="preprocessor">#define  CAN_F13R1_FB30                      ((uint32_t)0x40000000)        </span>
<a name="l02365"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga1a750d71e94876d2f6e73a0e8b7217b2">02365</a> <span class="preprocessor">#define  CAN_F13R1_FB31                      ((uint32_t)0x80000000)        </span>
<a name="l02367"></a>02367 <span class="preprocessor"></span><span class="comment">/*******************  Bit definition for CAN_F0R2 register  *******************/</span>
<a name="l02368"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga34282ddec559ecea4b613f2430334237">02368</a> <span class="preprocessor">#define  CAN_F0R2_FB0                        ((uint32_t)0x00000001)        </span>
<a name="l02369"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga6f23fc3814e0eb6af35c01e22c5dc6a7">02369</a> <span class="preprocessor">#define  CAN_F0R2_FB1                        ((uint32_t)0x00000002)        </span>
<a name="l02370"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga82ee32b6ec44d763b4364fa032d3439c">02370</a> <span class="preprocessor">#define  CAN_F0R2_FB2                        ((uint32_t)0x00000004)        </span>
<a name="l02371"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga7867b1d377088c63cdcc615932101997">02371</a> <span class="preprocessor">#define  CAN_F0R2_FB3                        ((uint32_t)0x00000008)        </span>
<a name="l02372"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga37fc5c9115eb669f1ac493b1c7296250">02372</a> <span class="preprocessor">#define  CAN_F0R2_FB4                        ((uint32_t)0x00000010)        </span>
<a name="l02373"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gae04b27aad09a3027f20a4eb48884c463">02373</a> <span class="preprocessor">#define  CAN_F0R2_FB5                        ((uint32_t)0x00000020)        </span>
<a name="l02374"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gae58d87c9513c11593041c3d43b955e8b">02374</a> <span class="preprocessor">#define  CAN_F0R2_FB6                        ((uint32_t)0x00000040)        </span>
<a name="l02375"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga03a6328d408b8015bb472c76f96a4dd8">02375</a> <span class="preprocessor">#define  CAN_F0R2_FB7                        ((uint32_t)0x00000080)        </span>
<a name="l02376"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga92fd1acf48665f966b670a0457456deb">02376</a> <span class="preprocessor">#define  CAN_F0R2_FB8                        ((uint32_t)0x00000100)        </span>
<a name="l02377"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaa853cff5493c4e857b7bb1ad28678ed4">02377</a> <span class="preprocessor">#define  CAN_F0R2_FB9                        ((uint32_t)0x00000200)        </span>
<a name="l02378"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaa43bba65dd777c71e07130fde3fa6216">02378</a> <span class="preprocessor">#define  CAN_F0R2_FB10                       ((uint32_t)0x00000400)        </span>
<a name="l02379"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga9077b9c35c6721d2a0e090a42af0eaaf">02379</a> <span class="preprocessor">#define  CAN_F0R2_FB11                       ((uint32_t)0x00000800)        </span>
<a name="l02380"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga23af8df7d4e843a6e196b1542421ef45">02380</a> <span class="preprocessor">#define  CAN_F0R2_FB12                       ((uint32_t)0x00001000)        </span>
<a name="l02381"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga0fe7776af3adce7d203aeb16d55d86d4">02381</a> <span class="preprocessor">#define  CAN_F0R2_FB13                       ((uint32_t)0x00002000)        </span>
<a name="l02382"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga81168efb90a776e44a96d1fe5e3b88c3">02382</a> <span class="preprocessor">#define  CAN_F0R2_FB14                       ((uint32_t)0x00004000)        </span>
<a name="l02383"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gae9708e7cde70a19e8e8fa33291e1b9d5">02383</a> <span class="preprocessor">#define  CAN_F0R2_FB15                       ((uint32_t)0x00008000)        </span>
<a name="l02384"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gab2f2154c3030cebcfc3f1e4aed74fbf1">02384</a> <span class="preprocessor">#define  CAN_F0R2_FB16                       ((uint32_t)0x00010000)        </span>
<a name="l02385"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gae87c14b75911aa0a9d0349d02d342711">02385</a> <span class="preprocessor">#define  CAN_F0R2_FB17                       ((uint32_t)0x00020000)        </span>
<a name="l02386"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga6fd7859cfc05300f68b175f520ddc31e">02386</a> <span class="preprocessor">#define  CAN_F0R2_FB18                       ((uint32_t)0x00040000)        </span>
<a name="l02387"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaaea36db8fcada46357137efeea256457">02387</a> <span class="preprocessor">#define  CAN_F0R2_FB19                       ((uint32_t)0x00080000)        </span>
<a name="l02388"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga57872dcfea1f8a56170640842edf9c1a">02388</a> <span class="preprocessor">#define  CAN_F0R2_FB20                       ((uint32_t)0x00100000)        </span>
<a name="l02389"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gacc01e7f26d0e85da93ca78d0d71a4fed">02389</a> <span class="preprocessor">#define  CAN_F0R2_FB21                       ((uint32_t)0x00200000)        </span>
<a name="l02390"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga07d8c3c8c3eb3c97b5979388c548e2fc">02390</a> <span class="preprocessor">#define  CAN_F0R2_FB22                       ((uint32_t)0x00400000)        </span>
<a name="l02391"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gade31bd75624afeaef9b5ab45a5057db9">02391</a> <span class="preprocessor">#define  CAN_F0R2_FB23                       ((uint32_t)0x00800000)        </span>
<a name="l02392"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaa78ff8fcfe0f14655aaf94ecc92d7532">02392</a> <span class="preprocessor">#define  CAN_F0R2_FB24                       ((uint32_t)0x01000000)        </span>
<a name="l02393"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaad577ebd9a8cedd1b8b13d5a41d2fbab">02393</a> <span class="preprocessor">#define  CAN_F0R2_FB25                       ((uint32_t)0x02000000)        </span>
<a name="l02394"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gab814105bcd2a2c636c26197b21ead2b0">02394</a> <span class="preprocessor">#define  CAN_F0R2_FB26                       ((uint32_t)0x04000000)        </span>
<a name="l02395"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaea82daeaa71ecddb187613df9517e51c">02395</a> <span class="preprocessor">#define  CAN_F0R2_FB27                       ((uint32_t)0x08000000)        </span>
<a name="l02396"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaef5036edf5bd310e5e06f3ea5cb818a2">02396</a> <span class="preprocessor">#define  CAN_F0R2_FB28                       ((uint32_t)0x10000000)        </span>
<a name="l02397"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaa0c2db96ddbcfa1b838c283e20ca554b">02397</a> <span class="preprocessor">#define  CAN_F0R2_FB29                       ((uint32_t)0x20000000)        </span>
<a name="l02398"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga5afb46a2d4ccb3f28e8579b26e2b2e2e">02398</a> <span class="preprocessor">#define  CAN_F0R2_FB30                       ((uint32_t)0x40000000)        </span>
<a name="l02399"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga1ace83e798931f35c123507e1ef59fbb">02399</a> <span class="preprocessor">#define  CAN_F0R2_FB31                       ((uint32_t)0x80000000)        </span>
<a name="l02401"></a>02401 <span class="preprocessor"></span><span class="comment">/*******************  Bit definition for CAN_F1R2 register  *******************/</span>
<a name="l02402"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga7ea3c5d8ab8962d9cd0e2b067167d3d4">02402</a> <span class="preprocessor">#define  CAN_F1R2_FB0                        ((uint32_t)0x00000001)        </span>
<a name="l02403"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gacfa5449488e7330d8f11f75fcf3e75cd">02403</a> <span class="preprocessor">#define  CAN_F1R2_FB1                        ((uint32_t)0x00000002)        </span>
<a name="l02404"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gafe49a3e224459f1bd9b3279ebfa8803b">02404</a> <span class="preprocessor">#define  CAN_F1R2_FB2                        ((uint32_t)0x00000004)        </span>
<a name="l02405"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga77cf2217ec29e2043bada827249dedd5">02405</a> <span class="preprocessor">#define  CAN_F1R2_FB3                        ((uint32_t)0x00000008)        </span>
<a name="l02406"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaf35643f0148ed0f93e3ba52e95a4cf6b">02406</a> <span class="preprocessor">#define  CAN_F1R2_FB4                        ((uint32_t)0x00000010)        </span>
<a name="l02407"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gae08798adabd9cc0fb2b07eaff6444878">02407</a> <span class="preprocessor">#define  CAN_F1R2_FB5                        ((uint32_t)0x00000020)        </span>
<a name="l02408"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga06659c9a418d7f4a8729d87bc397be23">02408</a> <span class="preprocessor">#define  CAN_F1R2_FB6                        ((uint32_t)0x00000040)        </span>
<a name="l02409"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga36bb9ca8dadd6714052f8d31cb01cb7b">02409</a> <span class="preprocessor">#define  CAN_F1R2_FB7                        ((uint32_t)0x00000080)        </span>
<a name="l02410"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga2d400044261146be3deb722d9cf3d5c1">02410</a> <span class="preprocessor">#define  CAN_F1R2_FB8                        ((uint32_t)0x00000100)        </span>
<a name="l02411"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gab3e5769ea8faaed16c6cb2ce979d28a9">02411</a> <span class="preprocessor">#define  CAN_F1R2_FB9                        ((uint32_t)0x00000200)        </span>
<a name="l02412"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga915236a6b5081c2c30bd4d49144bc463">02412</a> <span class="preprocessor">#define  CAN_F1R2_FB10                       ((uint32_t)0x00000400)        </span>
<a name="l02413"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gabf1aa2e62d4eede199196f81795d309c">02413</a> <span class="preprocessor">#define  CAN_F1R2_FB11                       ((uint32_t)0x00000800)        </span>
<a name="l02414"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga7db0ae3dcaab35e4c496c8a800b5c994">02414</a> <span class="preprocessor">#define  CAN_F1R2_FB12                       ((uint32_t)0x00001000)        </span>
<a name="l02415"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga02cdb71c56a5d9994ecd2dee668c7184">02415</a> <span class="preprocessor">#define  CAN_F1R2_FB13                       ((uint32_t)0x00002000)        </span>
<a name="l02416"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gac66691ca840db6c861460d311a942a87">02416</a> <span class="preprocessor">#define  CAN_F1R2_FB14                       ((uint32_t)0x00004000)        </span>
<a name="l02417"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gabcdd57022e26859db1f81f2df08c8725">02417</a> <span class="preprocessor">#define  CAN_F1R2_FB15                       ((uint32_t)0x00008000)        </span>
<a name="l02418"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga211795b36769a0b87044f0d82a7a72b1">02418</a> <span class="preprocessor">#define  CAN_F1R2_FB16                       ((uint32_t)0x00010000)        </span>
<a name="l02419"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gabc8c427731f33c76fad0873bb29a4b4c">02419</a> <span class="preprocessor">#define  CAN_F1R2_FB17                       ((uint32_t)0x00020000)        </span>
<a name="l02420"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga10a3e6be9968b8007562e7afe6b3b342">02420</a> <span class="preprocessor">#define  CAN_F1R2_FB18                       ((uint32_t)0x00040000)        </span>
<a name="l02421"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga4aac6ab4bd4cdeecbe621adf1d11b95a">02421</a> <span class="preprocessor">#define  CAN_F1R2_FB19                       ((uint32_t)0x00080000)        </span>
<a name="l02422"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga30140ced3da0d0a526c4f4f5881987c1">02422</a> <span class="preprocessor">#define  CAN_F1R2_FB20                       ((uint32_t)0x00100000)        </span>
<a name="l02423"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga49f36aec2e851ed18c5a382a0708bbcb">02423</a> <span class="preprocessor">#define  CAN_F1R2_FB21                       ((uint32_t)0x00200000)        </span>
<a name="l02424"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga99ccab06a8a97616a2fc3e026f36351d">02424</a> <span class="preprocessor">#define  CAN_F1R2_FB22                       ((uint32_t)0x00400000)        </span>
<a name="l02425"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaaa408889ff6478d6558d4c53c9114bde">02425</a> <span class="preprocessor">#define  CAN_F1R2_FB23                       ((uint32_t)0x00800000)        </span>
<a name="l02426"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga032dd8dc11aa9013cc0e824e31932951">02426</a> <span class="preprocessor">#define  CAN_F1R2_FB24                       ((uint32_t)0x01000000)        </span>
<a name="l02427"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga76f29020524ec6403a40de4e260a2ea8">02427</a> <span class="preprocessor">#define  CAN_F1R2_FB25                       ((uint32_t)0x02000000)        </span>
<a name="l02428"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga0bb51cd27fea671be51a59ce7a83008e">02428</a> <span class="preprocessor">#define  CAN_F1R2_FB26                       ((uint32_t)0x04000000)        </span>
<a name="l02429"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga085c38b511aa4895b6c939a06070c916">02429</a> <span class="preprocessor">#define  CAN_F1R2_FB27                       ((uint32_t)0x08000000)        </span>
<a name="l02430"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gabe299378c771da8d7d8e72a6f6e41f7f">02430</a> <span class="preprocessor">#define  CAN_F1R2_FB28                       ((uint32_t)0x10000000)        </span>
<a name="l02431"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaabc8bef79b09bcfcb0df6ba467ed906b">02431</a> <span class="preprocessor">#define  CAN_F1R2_FB29                       ((uint32_t)0x20000000)        </span>
<a name="l02432"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gabc4aba2c95f27229987d9eb4cda9890c">02432</a> <span class="preprocessor">#define  CAN_F1R2_FB30                       ((uint32_t)0x40000000)        </span>
<a name="l02433"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga21cbfc217d67062d265753964c871065">02433</a> <span class="preprocessor">#define  CAN_F1R2_FB31                       ((uint32_t)0x80000000)        </span>
<a name="l02435"></a>02435 <span class="preprocessor"></span><span class="comment">/*******************  Bit definition for CAN_F2R2 register  *******************/</span>
<a name="l02436"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga36964e4bf6aa10467b3d95781da56814">02436</a> <span class="preprocessor">#define  CAN_F2R2_FB0                        ((uint32_t)0x00000001)        </span>
<a name="l02437"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga0d0541eb1a4f8ae0afe429ac0757de6a">02437</a> <span class="preprocessor">#define  CAN_F2R2_FB1                        ((uint32_t)0x00000002)        </span>
<a name="l02438"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga14fd5aff8767df509b396190ddf7fa28">02438</a> <span class="preprocessor">#define  CAN_F2R2_FB2                        ((uint32_t)0x00000004)        </span>
<a name="l02439"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga7283e2a71983078144fa9a8e5ae563a9">02439</a> <span class="preprocessor">#define  CAN_F2R2_FB3                        ((uint32_t)0x00000008)        </span>
<a name="l02440"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaeba1324d32b084c477a0ece7b904a4cd">02440</a> <span class="preprocessor">#define  CAN_F2R2_FB4                        ((uint32_t)0x00000010)        </span>
<a name="l02441"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga1a367cf9f2f7e604e9f5e30b5ed30779">02441</a> <span class="preprocessor">#define  CAN_F2R2_FB5                        ((uint32_t)0x00000020)        </span>
<a name="l02442"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga6b92ac9785e2f7c890130e9b7d792c79">02442</a> <span class="preprocessor">#define  CAN_F2R2_FB6                        ((uint32_t)0x00000040)        </span>
<a name="l02443"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gac969a33d20353d5cd7fb317f5fa71138">02443</a> <span class="preprocessor">#define  CAN_F2R2_FB7                        ((uint32_t)0x00000080)        </span>
<a name="l02444"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gafeaac84fa5eec0173c531e9940327f86">02444</a> <span class="preprocessor">#define  CAN_F2R2_FB8                        ((uint32_t)0x00000100)        </span>
<a name="l02445"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga532413ea309fa031e65397a5b31ac92c">02445</a> <span class="preprocessor">#define  CAN_F2R2_FB9                        ((uint32_t)0x00000200)        </span>
<a name="l02446"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga360e02860472400a9000ef2fc8ba7bb1">02446</a> <span class="preprocessor">#define  CAN_F2R2_FB10                       ((uint32_t)0x00000400)        </span>
<a name="l02447"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga4c917a5b5e1a010229caaa5b3a41d7a6">02447</a> <span class="preprocessor">#define  CAN_F2R2_FB11                       ((uint32_t)0x00000800)        </span>
<a name="l02448"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga0956873246e63b41c0a640bc8d117319">02448</a> <span class="preprocessor">#define  CAN_F2R2_FB12                       ((uint32_t)0x00001000)        </span>
<a name="l02449"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga53202218de27d073d577c27427fe0cbe">02449</a> <span class="preprocessor">#define  CAN_F2R2_FB13                       ((uint32_t)0x00002000)        </span>
<a name="l02450"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga960a1ffd4b153168494d91df69e30742">02450</a> <span class="preprocessor">#define  CAN_F2R2_FB14                       ((uint32_t)0x00004000)        </span>
<a name="l02451"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gafc81e9ab9ab926d1ca30c5b6060a126b">02451</a> <span class="preprocessor">#define  CAN_F2R2_FB15                       ((uint32_t)0x00008000)        </span>
<a name="l02452"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaa5f9a5279398454a3a2493b3e1783f52">02452</a> <span class="preprocessor">#define  CAN_F2R2_FB16                       ((uint32_t)0x00010000)        </span>
<a name="l02453"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga0275ec7527a223a33289118f9e0a2edd">02453</a> <span class="preprocessor">#define  CAN_F2R2_FB17                       ((uint32_t)0x00020000)        </span>
<a name="l02454"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga34028a240868ca7dd365ce98e31e84ca">02454</a> <span class="preprocessor">#define  CAN_F2R2_FB18                       ((uint32_t)0x00040000)        </span>
<a name="l02455"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga807cfa122b6c74d85fdab233dd9ed502">02455</a> <span class="preprocessor">#define  CAN_F2R2_FB19                       ((uint32_t)0x00080000)        </span>
<a name="l02456"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga1187f1ab7514c90af34b44eff80858fa">02456</a> <span class="preprocessor">#define  CAN_F2R2_FB20                       ((uint32_t)0x00100000)        </span>
<a name="l02457"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gacecb18e779a44989b724901f6c2af84f">02457</a> <span class="preprocessor">#define  CAN_F2R2_FB21                       ((uint32_t)0x00200000)        </span>
<a name="l02458"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga3f2a6017895d8d139dcbc3d0e6e69e69">02458</a> <span class="preprocessor">#define  CAN_F2R2_FB22                       ((uint32_t)0x00400000)        </span>
<a name="l02459"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaceff2f283cbd4935ec5d45ceaa18efe0">02459</a> <span class="preprocessor">#define  CAN_F2R2_FB23                       ((uint32_t)0x00800000)        </span>
<a name="l02460"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga3086667a209f91ed6d6b496b83111044">02460</a> <span class="preprocessor">#define  CAN_F2R2_FB24                       ((uint32_t)0x01000000)        </span>
<a name="l02461"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga5c8c7b240bb0dd2a3ec8b6c4c25af7ba">02461</a> <span class="preprocessor">#define  CAN_F2R2_FB25                       ((uint32_t)0x02000000)        </span>
<a name="l02462"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga51498379a1e3b81a83bf8d164c4f7e5e">02462</a> <span class="preprocessor">#define  CAN_F2R2_FB26                       ((uint32_t)0x04000000)        </span>
<a name="l02463"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaa1f78e7c530a3ef26d44b9353fa9ee36">02463</a> <span class="preprocessor">#define  CAN_F2R2_FB27                       ((uint32_t)0x08000000)        </span>
<a name="l02464"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga7e30d0e50fca346ca8cb427a6c85f9dc">02464</a> <span class="preprocessor">#define  CAN_F2R2_FB28                       ((uint32_t)0x10000000)        </span>
<a name="l02465"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga77586d252cad5a0a866b1d9deb6835ba">02465</a> <span class="preprocessor">#define  CAN_F2R2_FB29                       ((uint32_t)0x20000000)        </span>
<a name="l02466"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga6a10903e507b35b7425b3ae98a8c6800">02466</a> <span class="preprocessor">#define  CAN_F2R2_FB30                       ((uint32_t)0x40000000)        </span>
<a name="l02467"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gac34bca92730b6f7cd0de8af1a2d0014f">02467</a> <span class="preprocessor">#define  CAN_F2R2_FB31                       ((uint32_t)0x80000000)        </span>
<a name="l02469"></a>02469 <span class="preprocessor"></span><span class="comment">/*******************  Bit definition for CAN_F3R2 register  *******************/</span>
<a name="l02470"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga46730b7e64aa771087b6c9d5deb273e1">02470</a> <span class="preprocessor">#define  CAN_F3R2_FB0                        ((uint32_t)0x00000001)        </span>
<a name="l02471"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaeb12b61624912b90382a4ad95281e7f4">02471</a> <span class="preprocessor">#define  CAN_F3R2_FB1                        ((uint32_t)0x00000002)        </span>
<a name="l02472"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga6621759dddc575c01f5bbaab43d1f04e">02472</a> <span class="preprocessor">#define  CAN_F3R2_FB2                        ((uint32_t)0x00000004)        </span>
<a name="l02473"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga29d052fc2597171767d8cf5d72388ad5">02473</a> <span class="preprocessor">#define  CAN_F3R2_FB3                        ((uint32_t)0x00000008)        </span>
<a name="l02474"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga731e9949d77054ba176340652083ad46">02474</a> <span class="preprocessor">#define  CAN_F3R2_FB4                        ((uint32_t)0x00000010)        </span>
<a name="l02475"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga93c52f51fe9eefe7f0cf094522a592b6">02475</a> <span class="preprocessor">#define  CAN_F3R2_FB5                        ((uint32_t)0x00000020)        </span>
<a name="l02476"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gad675c2d3f72d8bc42e0f3088ddbcc3c9">02476</a> <span class="preprocessor">#define  CAN_F3R2_FB6                        ((uint32_t)0x00000040)        </span>
<a name="l02477"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga1734cf6a5a72d403cd043eb704246c85">02477</a> <span class="preprocessor">#define  CAN_F3R2_FB7                        ((uint32_t)0x00000080)        </span>
<a name="l02478"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga97d82554ce38567e44cd87ed99175928">02478</a> <span class="preprocessor">#define  CAN_F3R2_FB8                        ((uint32_t)0x00000100)        </span>
<a name="l02479"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga505f85fadba4397e6d9a241bbc9229bc">02479</a> <span class="preprocessor">#define  CAN_F3R2_FB9                        ((uint32_t)0x00000200)        </span>
<a name="l02480"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gabb635843951fb42ffeb776d8564d7e14">02480</a> <span class="preprocessor">#define  CAN_F3R2_FB10                       ((uint32_t)0x00000400)        </span>
<a name="l02481"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga5db557239646008004286de15847ced4">02481</a> <span class="preprocessor">#define  CAN_F3R2_FB11                       ((uint32_t)0x00000800)        </span>
<a name="l02482"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga118b2044dae4c93c66aaa4f28c5b695c">02482</a> <span class="preprocessor">#define  CAN_F3R2_FB12                       ((uint32_t)0x00001000)        </span>
<a name="l02483"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga8c041a2b8162a8055a1894d0a0b3d682">02483</a> <span class="preprocessor">#define  CAN_F3R2_FB13                       ((uint32_t)0x00002000)        </span>
<a name="l02484"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gafb6e0947fcb7594d12dcbca38d60c9f8">02484</a> <span class="preprocessor">#define  CAN_F3R2_FB14                       ((uint32_t)0x00004000)        </span>
<a name="l02485"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga1dae8addc6fa59e824e1a67fc8c91ddd">02485</a> <span class="preprocessor">#define  CAN_F3R2_FB15                       ((uint32_t)0x00008000)        </span>
<a name="l02486"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga992795c5e0b3b8a8c5d4d6e9eceb7366">02486</a> <span class="preprocessor">#define  CAN_F3R2_FB16                       ((uint32_t)0x00010000)        </span>
<a name="l02487"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga1637eff70416eb85d5d2a54e1f5d412e">02487</a> <span class="preprocessor">#define  CAN_F3R2_FB17                       ((uint32_t)0x00020000)        </span>
<a name="l02488"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga7bbfdfa29b84ea60e67d41f775c6ffc6">02488</a> <span class="preprocessor">#define  CAN_F3R2_FB18                       ((uint32_t)0x00040000)        </span>
<a name="l02489"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga827747e8cc66e4dcd22498c59e45c776">02489</a> <span class="preprocessor">#define  CAN_F3R2_FB19                       ((uint32_t)0x00080000)        </span>
<a name="l02490"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gabe0bb6919615ec6311e8c39f62bca618">02490</a> <span class="preprocessor">#define  CAN_F3R2_FB20                       ((uint32_t)0x00100000)        </span>
<a name="l02491"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga3c3e4716d3e52ec99451a942dceb59de">02491</a> <span class="preprocessor">#define  CAN_F3R2_FB21                       ((uint32_t)0x00200000)        </span>
<a name="l02492"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaffefb44a948d36dcd94248f63aa68d2b">02492</a> <span class="preprocessor">#define  CAN_F3R2_FB22                       ((uint32_t)0x00400000)        </span>
<a name="l02493"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga79ce25d44a38f520b4a93384d6f5ac40">02493</a> <span class="preprocessor">#define  CAN_F3R2_FB23                       ((uint32_t)0x00800000)        </span>
<a name="l02494"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga3fe1ced752dc811f9418181275c8c3fe">02494</a> <span class="preprocessor">#define  CAN_F3R2_FB24                       ((uint32_t)0x01000000)        </span>
<a name="l02495"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga9fb2f469246193f6fc9e4ade42192d28">02495</a> <span class="preprocessor">#define  CAN_F3R2_FB25                       ((uint32_t)0x02000000)        </span>
<a name="l02496"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaae85be7f7d7a9ddb8a60edb30d2a5727">02496</a> <span class="preprocessor">#define  CAN_F3R2_FB26                       ((uint32_t)0x04000000)        </span>
<a name="l02497"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga850c21b26100c68b9cb57608c0249543">02497</a> <span class="preprocessor">#define  CAN_F3R2_FB27                       ((uint32_t)0x08000000)        </span>
<a name="l02498"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga82ec6ad2ad1b6115496adcb3e66fae25">02498</a> <span class="preprocessor">#define  CAN_F3R2_FB28                       ((uint32_t)0x10000000)        </span>
<a name="l02499"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaf4fa34cc998edfdd1b3db93395ee6500">02499</a> <span class="preprocessor">#define  CAN_F3R2_FB29                       ((uint32_t)0x20000000)        </span>
<a name="l02500"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga7f4fea5ecec28e7f47647067b75cb24e">02500</a> <span class="preprocessor">#define  CAN_F3R2_FB30                       ((uint32_t)0x40000000)        </span>
<a name="l02501"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga58a154f4d0cb787f23429b3f7cf70fd6">02501</a> <span class="preprocessor">#define  CAN_F3R2_FB31                       ((uint32_t)0x80000000)        </span>
<a name="l02503"></a>02503 <span class="preprocessor"></span><span class="comment">/*******************  Bit definition for CAN_F4R2 register  *******************/</span>
<a name="l02504"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga97250d3eed2504846f39c50dce71c9d0">02504</a> <span class="preprocessor">#define  CAN_F4R2_FB0                        ((uint32_t)0x00000001)        </span>
<a name="l02505"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga145e11678ee6062df5164894ad8f80b1">02505</a> <span class="preprocessor">#define  CAN_F4R2_FB1                        ((uint32_t)0x00000002)        </span>
<a name="l02506"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga9d19193baf5412ec2e38822d062196b8">02506</a> <span class="preprocessor">#define  CAN_F4R2_FB2                        ((uint32_t)0x00000004)        </span>
<a name="l02507"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga94b8b1428b640932aced6446f8b41f83">02507</a> <span class="preprocessor">#define  CAN_F4R2_FB3                        ((uint32_t)0x00000008)        </span>
<a name="l02508"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga93164ec00412eb5eed168e8a30557f25">02508</a> <span class="preprocessor">#define  CAN_F4R2_FB4                        ((uint32_t)0x00000010)        </span>
<a name="l02509"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga04e44c5a14e44c20f3b81044a915db13">02509</a> <span class="preprocessor">#define  CAN_F4R2_FB5                        ((uint32_t)0x00000020)        </span>
<a name="l02510"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga37e57dec99c33f462a2dbb6273df2f57">02510</a> <span class="preprocessor">#define  CAN_F4R2_FB6                        ((uint32_t)0x00000040)        </span>
<a name="l02511"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaf6c7d3ec0375e356192583142f7fccca">02511</a> <span class="preprocessor">#define  CAN_F4R2_FB7                        ((uint32_t)0x00000080)        </span>
<a name="l02512"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gad33f7d788aea161826a86bc2c5567450">02512</a> <span class="preprocessor">#define  CAN_F4R2_FB8                        ((uint32_t)0x00000100)        </span>
<a name="l02513"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaab998448b0bd20ff6384c26ad9e6baaf">02513</a> <span class="preprocessor">#define  CAN_F4R2_FB9                        ((uint32_t)0x00000200)        </span>
<a name="l02514"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gad8794112fcbb0dca0c7d0316ac8725e8">02514</a> <span class="preprocessor">#define  CAN_F4R2_FB10                       ((uint32_t)0x00000400)        </span>
<a name="l02515"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga0d22e782a9ca087f99ab9f53b2626aed">02515</a> <span class="preprocessor">#define  CAN_F4R2_FB11                       ((uint32_t)0x00000800)        </span>
<a name="l02516"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaaa8d5c2635a62bdfa6e3a5a12b127fc8">02516</a> <span class="preprocessor">#define  CAN_F4R2_FB12                       ((uint32_t)0x00001000)        </span>
<a name="l02517"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gad491689799985f0c8f17b270cd8873c4">02517</a> <span class="preprocessor">#define  CAN_F4R2_FB13                       ((uint32_t)0x00002000)        </span>
<a name="l02518"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gab1b80d40d87204de4687735de852f47f">02518</a> <span class="preprocessor">#define  CAN_F4R2_FB14                       ((uint32_t)0x00004000)        </span>
<a name="l02519"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga0994b341ba8a73b950f01d83d012780d">02519</a> <span class="preprocessor">#define  CAN_F4R2_FB15                       ((uint32_t)0x00008000)        </span>
<a name="l02520"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga6ae8b77d791ba7403618989a77e62922">02520</a> <span class="preprocessor">#define  CAN_F4R2_FB16                       ((uint32_t)0x00010000)        </span>
<a name="l02521"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gabc116988117a7e7fabc722855351d257">02521</a> <span class="preprocessor">#define  CAN_F4R2_FB17                       ((uint32_t)0x00020000)        </span>
<a name="l02522"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga07b1fc6ee0dc4cc892d69ed496b59007">02522</a> <span class="preprocessor">#define  CAN_F4R2_FB18                       ((uint32_t)0x00040000)        </span>
<a name="l02523"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaa58785812f0d3e73a657426b81f0b78b">02523</a> <span class="preprocessor">#define  CAN_F4R2_FB19                       ((uint32_t)0x00080000)        </span>
<a name="l02524"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga363da353073d7ee6421cf171688ef52b">02524</a> <span class="preprocessor">#define  CAN_F4R2_FB20                       ((uint32_t)0x00100000)        </span>
<a name="l02525"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga4f22695359aa9a1b07763aef44a9a1c4">02525</a> <span class="preprocessor">#define  CAN_F4R2_FB21                       ((uint32_t)0x00200000)        </span>
<a name="l02526"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gac0f8c1ef382225198407474f2b7fa073">02526</a> <span class="preprocessor">#define  CAN_F4R2_FB22                       ((uint32_t)0x00400000)        </span>
<a name="l02527"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga9476c54044db3182ee789e9df1d1aa19">02527</a> <span class="preprocessor">#define  CAN_F4R2_FB23                       ((uint32_t)0x00800000)        </span>
<a name="l02528"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga73158a3669d2ef96db84e4f196d040bf">02528</a> <span class="preprocessor">#define  CAN_F4R2_FB24                       ((uint32_t)0x01000000)        </span>
<a name="l02529"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga17d36fcf8e08c76597a7b2c05e831f98">02529</a> <span class="preprocessor">#define  CAN_F4R2_FB25                       ((uint32_t)0x02000000)        </span>
<a name="l02530"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaa683635426f418ead45032c25e0179ee">02530</a> <span class="preprocessor">#define  CAN_F4R2_FB26                       ((uint32_t)0x04000000)        </span>
<a name="l02531"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga23c77145ea84805a785b49c0a7f31774">02531</a> <span class="preprocessor">#define  CAN_F4R2_FB27                       ((uint32_t)0x08000000)        </span>
<a name="l02532"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga18492e954ec07174a1b140104062f941">02532</a> <span class="preprocessor">#define  CAN_F4R2_FB28                       ((uint32_t)0x10000000)        </span>
<a name="l02533"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaaf94626a8450c20e241ad6298660ec23">02533</a> <span class="preprocessor">#define  CAN_F4R2_FB29                       ((uint32_t)0x20000000)        </span>
<a name="l02534"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga4d7da9aa234705aff3ddc9845b1589d4">02534</a> <span class="preprocessor">#define  CAN_F4R2_FB30                       ((uint32_t)0x40000000)        </span>
<a name="l02535"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga70293ff8a71e353d84a3da134eb427d9">02535</a> <span class="preprocessor">#define  CAN_F4R2_FB31                       ((uint32_t)0x80000000)        </span>
<a name="l02537"></a>02537 <span class="preprocessor"></span><span class="comment">/*******************  Bit definition for CAN_F5R2 register  *******************/</span>
<a name="l02538"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga17b264aaa84a3c6ab5a35014eb5dfb09">02538</a> <span class="preprocessor">#define  CAN_F5R2_FB0                        ((uint32_t)0x00000001)        </span>
<a name="l02539"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaa871f5bc692996efc8c1bad1d08b43c5">02539</a> <span class="preprocessor">#define  CAN_F5R2_FB1                        ((uint32_t)0x00000002)        </span>
<a name="l02540"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaf44a72156023a5889a1c22d77e188e2e">02540</a> <span class="preprocessor">#define  CAN_F5R2_FB2                        ((uint32_t)0x00000004)        </span>
<a name="l02541"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga3d8828885a79299bc65c2011f71240e2">02541</a> <span class="preprocessor">#define  CAN_F5R2_FB3                        ((uint32_t)0x00000008)        </span>
<a name="l02542"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gadfa978108927c827e3021499a20d0372">02542</a> <span class="preprocessor">#define  CAN_F5R2_FB4                        ((uint32_t)0x00000010)        </span>
<a name="l02543"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaf3b3c48011935170a9bd120b724030fe">02543</a> <span class="preprocessor">#define  CAN_F5R2_FB5                        ((uint32_t)0x00000020)        </span>
<a name="l02544"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga56cf7f6d0bf48847f3d8f72777774e58">02544</a> <span class="preprocessor">#define  CAN_F5R2_FB6                        ((uint32_t)0x00000040)        </span>
<a name="l02545"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga2cb8a5551d90c8d79b09b4d82f3f59c2">02545</a> <span class="preprocessor">#define  CAN_F5R2_FB7                        ((uint32_t)0x00000080)        </span>
<a name="l02546"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga423b7b77bfd5dd6791f1b1dd16e9807a">02546</a> <span class="preprocessor">#define  CAN_F5R2_FB8                        ((uint32_t)0x00000100)        </span>
<a name="l02547"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga9c50420a128a70341e63ad23b0bedba5">02547</a> <span class="preprocessor">#define  CAN_F5R2_FB9                        ((uint32_t)0x00000200)        </span>
<a name="l02548"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga392844657c800d2e16e7916ed5fb9891">02548</a> <span class="preprocessor">#define  CAN_F5R2_FB10                       ((uint32_t)0x00000400)        </span>
<a name="l02549"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gabb35a3bbc447c46929643115490e250d">02549</a> <span class="preprocessor">#define  CAN_F5R2_FB11                       ((uint32_t)0x00000800)        </span>
<a name="l02550"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga974bae58f9819eee0377d709c985bcbe">02550</a> <span class="preprocessor">#define  CAN_F5R2_FB12                       ((uint32_t)0x00001000)        </span>
<a name="l02551"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga2823bb25e138cc52d11b154456947ab7">02551</a> <span class="preprocessor">#define  CAN_F5R2_FB13                       ((uint32_t)0x00002000)        </span>
<a name="l02552"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga98cf223bdcc1a106f7573b57f836f9ed">02552</a> <span class="preprocessor">#define  CAN_F5R2_FB14                       ((uint32_t)0x00004000)        </span>
<a name="l02553"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga26bfd14720495dd180f1524f2fdb3743">02553</a> <span class="preprocessor">#define  CAN_F5R2_FB15                       ((uint32_t)0x00008000)        </span>
<a name="l02554"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga41b457c721dc855d05b2f353c22a83a7">02554</a> <span class="preprocessor">#define  CAN_F5R2_FB16                       ((uint32_t)0x00010000)        </span>
<a name="l02555"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga1bc89534aaf3f810a2151b04b0086717">02555</a> <span class="preprocessor">#define  CAN_F5R2_FB17                       ((uint32_t)0x00020000)        </span>
<a name="l02556"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga070940536728fad3c0e5336926131b4b">02556</a> <span class="preprocessor">#define  CAN_F5R2_FB18                       ((uint32_t)0x00040000)        </span>
<a name="l02557"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaddf2e4aa8107150a86d37ce03a0e1c0e">02557</a> <span class="preprocessor">#define  CAN_F5R2_FB19                       ((uint32_t)0x00080000)        </span>
<a name="l02558"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga1788704faad47f1d45017df41a35f053">02558</a> <span class="preprocessor">#define  CAN_F5R2_FB20                       ((uint32_t)0x00100000)        </span>
<a name="l02559"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga11c4aeffb6646643c412e19e6f5cc015">02559</a> <span class="preprocessor">#define  CAN_F5R2_FB21                       ((uint32_t)0x00200000)        </span>
<a name="l02560"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaef348c2d37f96f5e5324368f90c80d42">02560</a> <span class="preprocessor">#define  CAN_F5R2_FB22                       ((uint32_t)0x00400000)        </span>
<a name="l02561"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga398d842cfcb2d441d999e1407fc54f83">02561</a> <span class="preprocessor">#define  CAN_F5R2_FB23                       ((uint32_t)0x00800000)        </span>
<a name="l02562"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga6575f8d4d154e2e8342b3f88352a9d52">02562</a> <span class="preprocessor">#define  CAN_F5R2_FB24                       ((uint32_t)0x01000000)        </span>
<a name="l02563"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gae9e6ad77b1d8ac7303e920658aceb354">02563</a> <span class="preprocessor">#define  CAN_F5R2_FB25                       ((uint32_t)0x02000000)        </span>
<a name="l02564"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga911ade78e30d1a037d35dda5eb7cbd4b">02564</a> <span class="preprocessor">#define  CAN_F5R2_FB26                       ((uint32_t)0x04000000)        </span>
<a name="l02565"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga49542b9334bc4917e25d6808c78787d1">02565</a> <span class="preprocessor">#define  CAN_F5R2_FB27                       ((uint32_t)0x08000000)        </span>
<a name="l02566"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga255da64f4a66ff888f6633d6e51658c6">02566</a> <span class="preprocessor">#define  CAN_F5R2_FB28                       ((uint32_t)0x10000000)        </span>
<a name="l02567"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga8335d23f9fd156f40dc7fd63ba6783cb">02567</a> <span class="preprocessor">#define  CAN_F5R2_FB29                       ((uint32_t)0x20000000)        </span>
<a name="l02568"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaf81786b7519b39f705729de2c55e4faa">02568</a> <span class="preprocessor">#define  CAN_F5R2_FB30                       ((uint32_t)0x40000000)        </span>
<a name="l02569"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga4f7122b0ad8cb4fc1797d0dbecbb4a05">02569</a> <span class="preprocessor">#define  CAN_F5R2_FB31                       ((uint32_t)0x80000000)        </span>
<a name="l02571"></a>02571 <span class="preprocessor"></span><span class="comment">/*******************  Bit definition for CAN_F6R2 register  *******************/</span>
<a name="l02572"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga71ad6452660daed3d6c436533a25efc2">02572</a> <span class="preprocessor">#define  CAN_F6R2_FB0                        ((uint32_t)0x00000001)        </span>
<a name="l02573"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gac9e24abd8d2f0775661415b6565f4f6d">02573</a> <span class="preprocessor">#define  CAN_F6R2_FB1                        ((uint32_t)0x00000002)        </span>
<a name="l02574"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaf6dc3f6ce4dde435743aadbe17cc78b9">02574</a> <span class="preprocessor">#define  CAN_F6R2_FB2                        ((uint32_t)0x00000004)        </span>
<a name="l02575"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gae1f5163490dffe1f4d7c635458359c2f">02575</a> <span class="preprocessor">#define  CAN_F6R2_FB3                        ((uint32_t)0x00000008)        </span>
<a name="l02576"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga89e9191d214d05f4d90fbcd38daa73e1">02576</a> <span class="preprocessor">#define  CAN_F6R2_FB4                        ((uint32_t)0x00000010)        </span>
<a name="l02577"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga97d29588281c546d98e09760cc5ef593">02577</a> <span class="preprocessor">#define  CAN_F6R2_FB5                        ((uint32_t)0x00000020)        </span>
<a name="l02578"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga53f5717aca9932255049b133661765bf">02578</a> <span class="preprocessor">#define  CAN_F6R2_FB6                        ((uint32_t)0x00000040)        </span>
<a name="l02579"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga7ec93958e936379d891bc3450dba3d1d">02579</a> <span class="preprocessor">#define  CAN_F6R2_FB7                        ((uint32_t)0x00000080)        </span>
<a name="l02580"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga8f97c7eb9d6e69d589db38d745ae321c">02580</a> <span class="preprocessor">#define  CAN_F6R2_FB8                        ((uint32_t)0x00000100)        </span>
<a name="l02581"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga372ebb5d42d147d41688f7c0fcf467d2">02581</a> <span class="preprocessor">#define  CAN_F6R2_FB9                        ((uint32_t)0x00000200)        </span>
<a name="l02582"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga47baa2c9c05c7c422a49994b8f80016f">02582</a> <span class="preprocessor">#define  CAN_F6R2_FB10                       ((uint32_t)0x00000400)        </span>
<a name="l02583"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga55d7665b118e98586c2a9b1900ce7292">02583</a> <span class="preprocessor">#define  CAN_F6R2_FB11                       ((uint32_t)0x00000800)        </span>
<a name="l02584"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga5095a203d07244e75dd6deca125b4468">02584</a> <span class="preprocessor">#define  CAN_F6R2_FB12                       ((uint32_t)0x00001000)        </span>
<a name="l02585"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga533dbb10e8fce9aa6ec23573fb49c339">02585</a> <span class="preprocessor">#define  CAN_F6R2_FB13                       ((uint32_t)0x00002000)        </span>
<a name="l02586"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga8b95be922291e534609302c0c833f1f7">02586</a> <span class="preprocessor">#define  CAN_F6R2_FB14                       ((uint32_t)0x00004000)        </span>
<a name="l02587"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga17301d50c7b6ad30ffc05ee2c63f6171">02587</a> <span class="preprocessor">#define  CAN_F6R2_FB15                       ((uint32_t)0x00008000)        </span>
<a name="l02588"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaf23dfb03247544122ed01472b8a31b4d">02588</a> <span class="preprocessor">#define  CAN_F6R2_FB16                       ((uint32_t)0x00010000)        </span>
<a name="l02589"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gadf8d35fbfa677fc446da68f4043b633e">02589</a> <span class="preprocessor">#define  CAN_F6R2_FB17                       ((uint32_t)0x00020000)        </span>
<a name="l02590"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga6c81a1972ec8d87421c6113bb9747c3e">02590</a> <span class="preprocessor">#define  CAN_F6R2_FB18                       ((uint32_t)0x00040000)        </span>
<a name="l02591"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga11ea1bd4bae8b27a5fd73d210eb83d39">02591</a> <span class="preprocessor">#define  CAN_F6R2_FB19                       ((uint32_t)0x00080000)        </span>
<a name="l02592"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga4c48dcd1ac5e23827813ed695bdff0d1">02592</a> <span class="preprocessor">#define  CAN_F6R2_FB20                       ((uint32_t)0x00100000)        </span>
<a name="l02593"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gacd115d29d9f0a8fddc13a32c013af26b">02593</a> <span class="preprocessor">#define  CAN_F6R2_FB21                       ((uint32_t)0x00200000)        </span>
<a name="l02594"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaa3f116b2e31dd40bcdd6617fee83907e">02594</a> <span class="preprocessor">#define  CAN_F6R2_FB22                       ((uint32_t)0x00400000)        </span>
<a name="l02595"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga090da76d2d9379dbfc54f7c3fcf69fe4">02595</a> <span class="preprocessor">#define  CAN_F6R2_FB23                       ((uint32_t)0x00800000)        </span>
<a name="l02596"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gae9c8a59a8065400f4a75be49a78e2a9e">02596</a> <span class="preprocessor">#define  CAN_F6R2_FB24                       ((uint32_t)0x01000000)        </span>
<a name="l02597"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga3854a1a11c72e64d3c4722494f463421">02597</a> <span class="preprocessor">#define  CAN_F6R2_FB25                       ((uint32_t)0x02000000)        </span>
<a name="l02598"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga7b5ceb9d7ae0c6e34490b8d8659919c9">02598</a> <span class="preprocessor">#define  CAN_F6R2_FB26                       ((uint32_t)0x04000000)        </span>
<a name="l02599"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gac01a4accedd624ceccf8f8976a043177">02599</a> <span class="preprocessor">#define  CAN_F6R2_FB27                       ((uint32_t)0x08000000)        </span>
<a name="l02600"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gacc2d754207055a5a87696eb1bb7d8cae">02600</a> <span class="preprocessor">#define  CAN_F6R2_FB28                       ((uint32_t)0x10000000)        </span>
<a name="l02601"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga471631ee112af3bde77d848c22d743ef">02601</a> <span class="preprocessor">#define  CAN_F6R2_FB29                       ((uint32_t)0x20000000)        </span>
<a name="l02602"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga9574ec7dddcea6b80368778c01f62598">02602</a> <span class="preprocessor">#define  CAN_F6R2_FB30                       ((uint32_t)0x40000000)        </span>
<a name="l02603"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga64bcb159347ad8e2a2609ce89ed030df">02603</a> <span class="preprocessor">#define  CAN_F6R2_FB31                       ((uint32_t)0x80000000)        </span>
<a name="l02605"></a>02605 <span class="preprocessor"></span><span class="comment">/*******************  Bit definition for CAN_F7R2 register  *******************/</span>
<a name="l02606"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaec0803330590bf9aba9d09342034b2c1">02606</a> <span class="preprocessor">#define  CAN_F7R2_FB0                        ((uint32_t)0x00000001)        </span>
<a name="l02607"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga8c633d4cbfdf79f09ae1df5e75c98439">02607</a> <span class="preprocessor">#define  CAN_F7R2_FB1                        ((uint32_t)0x00000002)        </span>
<a name="l02608"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga31a0c4ece8b73760ad295344b8558ddb">02608</a> <span class="preprocessor">#define  CAN_F7R2_FB2                        ((uint32_t)0x00000004)        </span>
<a name="l02609"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gafe2fc15309540b87538ea3e8460d8d11">02609</a> <span class="preprocessor">#define  CAN_F7R2_FB3                        ((uint32_t)0x00000008)        </span>
<a name="l02610"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gac81d4c021f4579021ddf9485472a84f5">02610</a> <span class="preprocessor">#define  CAN_F7R2_FB4                        ((uint32_t)0x00000010)        </span>
<a name="l02611"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga5dd6a00bb403a3e19e66c68f5ee308e2">02611</a> <span class="preprocessor">#define  CAN_F7R2_FB5                        ((uint32_t)0x00000020)        </span>
<a name="l02612"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga9b5eaf37458d0426fd7f847775fd41e9">02612</a> <span class="preprocessor">#define  CAN_F7R2_FB6                        ((uint32_t)0x00000040)        </span>
<a name="l02613"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga780440ce173cde12fd117b519419424c">02613</a> <span class="preprocessor">#define  CAN_F7R2_FB7                        ((uint32_t)0x00000080)        </span>
<a name="l02614"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga99ae0e27d14b42fef4551d83ee88b4ac">02614</a> <span class="preprocessor">#define  CAN_F7R2_FB8                        ((uint32_t)0x00000100)        </span>
<a name="l02615"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gace90c0624446480421fac233739413dc">02615</a> <span class="preprocessor">#define  CAN_F7R2_FB9                        ((uint32_t)0x00000200)        </span>
<a name="l02616"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaae60d566699df87580584ed496681562">02616</a> <span class="preprocessor">#define  CAN_F7R2_FB10                       ((uint32_t)0x00000400)        </span>
<a name="l02617"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga6325b37cc369b92b2334e482dbe3bf06">02617</a> <span class="preprocessor">#define  CAN_F7R2_FB11                       ((uint32_t)0x00000800)        </span>
<a name="l02618"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gace846d293ac11d535ee2aad17cf099bc">02618</a> <span class="preprocessor">#define  CAN_F7R2_FB12                       ((uint32_t)0x00001000)        </span>
<a name="l02619"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga91b26397a75fc4c0124e84903d31221e">02619</a> <span class="preprocessor">#define  CAN_F7R2_FB13                       ((uint32_t)0x00002000)        </span>
<a name="l02620"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gada2e01c05c216ba6ff4756d043297c0e">02620</a> <span class="preprocessor">#define  CAN_F7R2_FB14                       ((uint32_t)0x00004000)        </span>
<a name="l02621"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaeef08aa6565ff24bd9863b4b8a9c2ff5">02621</a> <span class="preprocessor">#define  CAN_F7R2_FB15                       ((uint32_t)0x00008000)        </span>
<a name="l02622"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga16c3ccb033b9541b57c338b9737f18dd">02622</a> <span class="preprocessor">#define  CAN_F7R2_FB16                       ((uint32_t)0x00010000)        </span>
<a name="l02623"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gad898ca382f57efb1842884d46217245c">02623</a> <span class="preprocessor">#define  CAN_F7R2_FB17                       ((uint32_t)0x00020000)        </span>
<a name="l02624"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaf419938e132cc1a0bf59a6c058e2c7c5">02624</a> <span class="preprocessor">#define  CAN_F7R2_FB18                       ((uint32_t)0x00040000)        </span>
<a name="l02625"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gae991abb6f2e64443be7e39633f192aba">02625</a> <span class="preprocessor">#define  CAN_F7R2_FB19                       ((uint32_t)0x00080000)        </span>
<a name="l02626"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga3738a42e2767c928de21a2f784ce6bce">02626</a> <span class="preprocessor">#define  CAN_F7R2_FB20                       ((uint32_t)0x00100000)        </span>
<a name="l02627"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gae5cb252582e6b7bd706b37447f71d6cd">02627</a> <span class="preprocessor">#define  CAN_F7R2_FB21                       ((uint32_t)0x00200000)        </span>
<a name="l02628"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gae616e53b9d961571eea4ff2df31f8399">02628</a> <span class="preprocessor">#define  CAN_F7R2_FB22                       ((uint32_t)0x00400000)        </span>
<a name="l02629"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gab2049c9bb27af3cde01334b1901aa417">02629</a> <span class="preprocessor">#define  CAN_F7R2_FB23                       ((uint32_t)0x00800000)        </span>
<a name="l02630"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga8e69c2fd32e2c523c9e939df825fc605">02630</a> <span class="preprocessor">#define  CAN_F7R2_FB24                       ((uint32_t)0x01000000)        </span>
<a name="l02631"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga659cc84b9186e279c37e88b94e1c9829">02631</a> <span class="preprocessor">#define  CAN_F7R2_FB25                       ((uint32_t)0x02000000)        </span>
<a name="l02632"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga43c9da5ad4c2d261858f73b779cc3dae">02632</a> <span class="preprocessor">#define  CAN_F7R2_FB26                       ((uint32_t)0x04000000)        </span>
<a name="l02633"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga0a1ea8d66ada6cea7268fba151c00d91">02633</a> <span class="preprocessor">#define  CAN_F7R2_FB27                       ((uint32_t)0x08000000)        </span>
<a name="l02634"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gabbd6032652515423412ad73b8a004bbb">02634</a> <span class="preprocessor">#define  CAN_F7R2_FB28                       ((uint32_t)0x10000000)        </span>
<a name="l02635"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga3a991a0bb5a81748b091d6b96c59fc37">02635</a> <span class="preprocessor">#define  CAN_F7R2_FB29                       ((uint32_t)0x20000000)        </span>
<a name="l02636"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaedae5e816af0dd734311bf44be7571f2">02636</a> <span class="preprocessor">#define  CAN_F7R2_FB30                       ((uint32_t)0x40000000)        </span>
<a name="l02637"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga2f88a239b8a39ff3343b1cfe70b06139">02637</a> <span class="preprocessor">#define  CAN_F7R2_FB31                       ((uint32_t)0x80000000)        </span>
<a name="l02639"></a>02639 <span class="preprocessor"></span><span class="comment">/*******************  Bit definition for CAN_F8R2 register  *******************/</span>
<a name="l02640"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga3cfe399fb494ff6ab1d5b91258c42764">02640</a> <span class="preprocessor">#define  CAN_F8R2_FB0                        ((uint32_t)0x00000001)        </span>
<a name="l02641"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga9ca04b514b4d6a3b19619932513b8953">02641</a> <span class="preprocessor">#define  CAN_F8R2_FB1                        ((uint32_t)0x00000002)        </span>
<a name="l02642"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gac4c3c099bf7db702b7bf5f71cddaaec2">02642</a> <span class="preprocessor">#define  CAN_F8R2_FB2                        ((uint32_t)0x00000004)        </span>
<a name="l02643"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gae1e53037e7f7171d8a7358590f0e7420">02643</a> <span class="preprocessor">#define  CAN_F8R2_FB3                        ((uint32_t)0x00000008)        </span>
<a name="l02644"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga51e2af45725e06538c4d09ad07296316">02644</a> <span class="preprocessor">#define  CAN_F8R2_FB4                        ((uint32_t)0x00000010)        </span>
<a name="l02645"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga2ee5e9d68190f0d41a5b8603d1933922">02645</a> <span class="preprocessor">#define  CAN_F8R2_FB5                        ((uint32_t)0x00000020)        </span>
<a name="l02646"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga66c636150cfad43a32652dba3ded8383">02646</a> <span class="preprocessor">#define  CAN_F8R2_FB6                        ((uint32_t)0x00000040)        </span>
<a name="l02647"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga0fc81a4ee32f76ce3a6fdbb3fc49425c">02647</a> <span class="preprocessor">#define  CAN_F8R2_FB7                        ((uint32_t)0x00000080)        </span>
<a name="l02648"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga68a36336242e8259c779f1c8f4544737">02648</a> <span class="preprocessor">#define  CAN_F8R2_FB8                        ((uint32_t)0x00000100)        </span>
<a name="l02649"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gad0014717b3c4c65afb7542308980803d">02649</a> <span class="preprocessor">#define  CAN_F8R2_FB9                        ((uint32_t)0x00000200)        </span>
<a name="l02650"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga315a7e30b95c05db01b7f56f4d825e62">02650</a> <span class="preprocessor">#define  CAN_F8R2_FB10                       ((uint32_t)0x00000400)        </span>
<a name="l02651"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga353aad2279bf6b72bd861f6c79253635">02651</a> <span class="preprocessor">#define  CAN_F8R2_FB11                       ((uint32_t)0x00000800)        </span>
<a name="l02652"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga25193c4b44d05db08ba40f0e0f2c45e1">02652</a> <span class="preprocessor">#define  CAN_F8R2_FB12                       ((uint32_t)0x00001000)        </span>
<a name="l02653"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga4469bfc90525f84d9d04d3a4996997e6">02653</a> <span class="preprocessor">#define  CAN_F8R2_FB13                       ((uint32_t)0x00002000)        </span>
<a name="l02654"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga3b17ebf3dd1e53d8417f955ebcf743b3">02654</a> <span class="preprocessor">#define  CAN_F8R2_FB14                       ((uint32_t)0x00004000)        </span>
<a name="l02655"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga6db6c2262434fc76213a441d8ce2edf1">02655</a> <span class="preprocessor">#define  CAN_F8R2_FB15                       ((uint32_t)0x00008000)        </span>
<a name="l02656"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga8a1e1e9aa84af36845402d19236c1214">02656</a> <span class="preprocessor">#define  CAN_F8R2_FB16                       ((uint32_t)0x00010000)        </span>
<a name="l02657"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gae0a9ee665444a6b42e98e0f988d1ba7a">02657</a> <span class="preprocessor">#define  CAN_F8R2_FB17                       ((uint32_t)0x00020000)        </span>
<a name="l02658"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga16cde37565a3d3ec3a8c41013df6f6f1">02658</a> <span class="preprocessor">#define  CAN_F8R2_FB18                       ((uint32_t)0x00040000)        </span>
<a name="l02659"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga57ca000fea3be225ddf5f295437b6e36">02659</a> <span class="preprocessor">#define  CAN_F8R2_FB19                       ((uint32_t)0x00080000)        </span>
<a name="l02660"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gad60ee9ebdce23be6d2adca113ca918e8">02660</a> <span class="preprocessor">#define  CAN_F8R2_FB20                       ((uint32_t)0x00100000)        </span>
<a name="l02661"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gae186c9794783eb47b460532801afe43a">02661</a> <span class="preprocessor">#define  CAN_F8R2_FB21                       ((uint32_t)0x00200000)        </span>
<a name="l02662"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga106a5e5b8ae8d683fcec85b076688f34">02662</a> <span class="preprocessor">#define  CAN_F8R2_FB22                       ((uint32_t)0x00400000)        </span>
<a name="l02663"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga1643a77c219a9b2706f438c5123bccc8">02663</a> <span class="preprocessor">#define  CAN_F8R2_FB23                       ((uint32_t)0x00800000)        </span>
<a name="l02664"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gab21aa6ed09bed09347e07dbcbd0e9e93">02664</a> <span class="preprocessor">#define  CAN_F8R2_FB24                       ((uint32_t)0x01000000)        </span>
<a name="l02665"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gab8267e4cdc484abd75634469f9b255c5">02665</a> <span class="preprocessor">#define  CAN_F8R2_FB25                       ((uint32_t)0x02000000)        </span>
<a name="l02666"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga697d286473e81666c91f28e853aab4ad">02666</a> <span class="preprocessor">#define  CAN_F8R2_FB26                       ((uint32_t)0x04000000)        </span>
<a name="l02667"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga295c26638700a849ee3c6504caf6ceab">02667</a> <span class="preprocessor">#define  CAN_F8R2_FB27                       ((uint32_t)0x08000000)        </span>
<a name="l02668"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga0f8469008983b405bfc5855258f4f6e6">02668</a> <span class="preprocessor">#define  CAN_F8R2_FB28                       ((uint32_t)0x10000000)        </span>
<a name="l02669"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gad18d894a75ebe73c0185d905cfb81dbf">02669</a> <span class="preprocessor">#define  CAN_F8R2_FB29                       ((uint32_t)0x20000000)        </span>
<a name="l02670"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaccdf92a69572b56641ddd2967c034a7a">02670</a> <span class="preprocessor">#define  CAN_F8R2_FB30                       ((uint32_t)0x40000000)        </span>
<a name="l02671"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga0636c9c9fd84e5e8d12e78f236f2a56c">02671</a> <span class="preprocessor">#define  CAN_F8R2_FB31                       ((uint32_t)0x80000000)        </span>
<a name="l02673"></a>02673 <span class="preprocessor"></span><span class="comment">/*******************  Bit definition for CAN_F9R2 register  *******************/</span>
<a name="l02674"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaa1209cec0d1199b7f74bb2e2b1cca424">02674</a> <span class="preprocessor">#define  CAN_F9R2_FB0                        ((uint32_t)0x00000001)        </span>
<a name="l02675"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga9fd983be0f74b7f183261f21cd2f6910">02675</a> <span class="preprocessor">#define  CAN_F9R2_FB1                        ((uint32_t)0x00000002)        </span>
<a name="l02676"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga2e363da951c1191e733a8bc603cda3f5">02676</a> <span class="preprocessor">#define  CAN_F9R2_FB2                        ((uint32_t)0x00000004)        </span>
<a name="l02677"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gabab5a59d405ae1684853988e95ab9844">02677</a> <span class="preprocessor">#define  CAN_F9R2_FB3                        ((uint32_t)0x00000008)        </span>
<a name="l02678"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga4b5b46878001f43618c726b3429e4b50">02678</a> <span class="preprocessor">#define  CAN_F9R2_FB4                        ((uint32_t)0x00000010)        </span>
<a name="l02679"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga582895a48cfeb8d7ecf6c9757ba0aa39">02679</a> <span class="preprocessor">#define  CAN_F9R2_FB5                        ((uint32_t)0x00000020)        </span>
<a name="l02680"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gafe18a44ac1a9c4cf2a6e94bb946af17f">02680</a> <span class="preprocessor">#define  CAN_F9R2_FB6                        ((uint32_t)0x00000040)        </span>
<a name="l02681"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gae497ffa0ef246a52e57a394fa57e616d">02681</a> <span class="preprocessor">#define  CAN_F9R2_FB7                        ((uint32_t)0x00000080)        </span>
<a name="l02682"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga4eedc431183ceae7240d11afc05bacfa">02682</a> <span class="preprocessor">#define  CAN_F9R2_FB8                        ((uint32_t)0x00000100)        </span>
<a name="l02683"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga71d1294050a77f52ecd4b00568cd7477">02683</a> <span class="preprocessor">#define  CAN_F9R2_FB9                        ((uint32_t)0x00000200)        </span>
<a name="l02684"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga5adc0ffeba391461d887f5d176a9b5bd">02684</a> <span class="preprocessor">#define  CAN_F9R2_FB10                       ((uint32_t)0x00000400)        </span>
<a name="l02685"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga989f1dea5a35e78b08649ac699955563">02685</a> <span class="preprocessor">#define  CAN_F9R2_FB11                       ((uint32_t)0x00000800)        </span>
<a name="l02686"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga0b71e1b7db02ef8c5853534921b33aee">02686</a> <span class="preprocessor">#define  CAN_F9R2_FB12                       ((uint32_t)0x00001000)        </span>
<a name="l02687"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga48cff2713910823bbf9c8aeb399d6695">02687</a> <span class="preprocessor">#define  CAN_F9R2_FB13                       ((uint32_t)0x00002000)        </span>
<a name="l02688"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gab9e0057c4eb0f7238d2ec98ae0702ff3">02688</a> <span class="preprocessor">#define  CAN_F9R2_FB14                       ((uint32_t)0x00004000)        </span>
<a name="l02689"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gacc16f71c9ee3bc56be17f7488c1df807">02689</a> <span class="preprocessor">#define  CAN_F9R2_FB15                       ((uint32_t)0x00008000)        </span>
<a name="l02690"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga3909a33262113171b7d4dc11fcf8c3b1">02690</a> <span class="preprocessor">#define  CAN_F9R2_FB16                       ((uint32_t)0x00010000)        </span>
<a name="l02691"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga8cead3f8d10075aa34c9446859356e2d">02691</a> <span class="preprocessor">#define  CAN_F9R2_FB17                       ((uint32_t)0x00020000)        </span>
<a name="l02692"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaf7730d43a2cf07a1568ed738a4f69692">02692</a> <span class="preprocessor">#define  CAN_F9R2_FB18                       ((uint32_t)0x00040000)        </span>
<a name="l02693"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga6b2f5ba8403cbd679694cf9665e2690f">02693</a> <span class="preprocessor">#define  CAN_F9R2_FB19                       ((uint32_t)0x00080000)        </span>
<a name="l02694"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaca5a17ed59696ed0572b80767c4bef81">02694</a> <span class="preprocessor">#define  CAN_F9R2_FB20                       ((uint32_t)0x00100000)        </span>
<a name="l02695"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gac318672024cefb98843d473cbb2d46b2">02695</a> <span class="preprocessor">#define  CAN_F9R2_FB21                       ((uint32_t)0x00200000)        </span>
<a name="l02696"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga3523d55c8cf0a308fea4837b00f89abb">02696</a> <span class="preprocessor">#define  CAN_F9R2_FB22                       ((uint32_t)0x00400000)        </span>
<a name="l02697"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga21d8d812323030dd39f417318c36b8dc">02697</a> <span class="preprocessor">#define  CAN_F9R2_FB23                       ((uint32_t)0x00800000)        </span>
<a name="l02698"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga065bba6dde8a5b81b42c2618204bf0be">02698</a> <span class="preprocessor">#define  CAN_F9R2_FB24                       ((uint32_t)0x01000000)        </span>
<a name="l02699"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gade5290535026c192f7e94a4cb98e48b4">02699</a> <span class="preprocessor">#define  CAN_F9R2_FB25                       ((uint32_t)0x02000000)        </span>
<a name="l02700"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaac7e7544d60c3084da344ee20ab6a760">02700</a> <span class="preprocessor">#define  CAN_F9R2_FB26                       ((uint32_t)0x04000000)        </span>
<a name="l02701"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gae965845f1e45d1f45831be60829e63bc">02701</a> <span class="preprocessor">#define  CAN_F9R2_FB27                       ((uint32_t)0x08000000)        </span>
<a name="l02702"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga63bbecf009bf6bd61dc9e8fe0603da73">02702</a> <span class="preprocessor">#define  CAN_F9R2_FB28                       ((uint32_t)0x10000000)        </span>
<a name="l02703"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga834cf606ef4b69b0c459b8cb9e836a9b">02703</a> <span class="preprocessor">#define  CAN_F9R2_FB29                       ((uint32_t)0x20000000)        </span>
<a name="l02704"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga9c833e07b7a842ba7425291f628c9a11">02704</a> <span class="preprocessor">#define  CAN_F9R2_FB30                       ((uint32_t)0x40000000)        </span>
<a name="l02705"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga18ef7c7bae75406a267e6a333c549a9f">02705</a> <span class="preprocessor">#define  CAN_F9R2_FB31                       ((uint32_t)0x80000000)        </span>
<a name="l02707"></a>02707 <span class="preprocessor"></span><span class="comment">/*******************  Bit definition for CAN_F10R2 register  ******************/</span>
<a name="l02708"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga616898121d5befed0eb5ab61492872f2">02708</a> <span class="preprocessor">#define  CAN_F10R2_FB0                       ((uint32_t)0x00000001)        </span>
<a name="l02709"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaa24b6ba1e723098e55e4affc793558c5">02709</a> <span class="preprocessor">#define  CAN_F10R2_FB1                       ((uint32_t)0x00000002)        </span>
<a name="l02710"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga1b7fc9db4e77e216f37bf088d7b7703c">02710</a> <span class="preprocessor">#define  CAN_F10R2_FB2                       ((uint32_t)0x00000004)        </span>
<a name="l02711"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga2348cdfff622628147e2c1df0a35363c">02711</a> <span class="preprocessor">#define  CAN_F10R2_FB3                       ((uint32_t)0x00000008)        </span>
<a name="l02712"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaebde0ea1e0aaf38fdcf1584e9c9b2063">02712</a> <span class="preprocessor">#define  CAN_F10R2_FB4                       ((uint32_t)0x00000010)        </span>
<a name="l02713"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga3b5b32b71c86c6dc7040b3044be61af7">02713</a> <span class="preprocessor">#define  CAN_F10R2_FB5                       ((uint32_t)0x00000020)        </span>
<a name="l02714"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga9df7daa799c7c73d9a56de5f92285aca">02714</a> <span class="preprocessor">#define  CAN_F10R2_FB6                       ((uint32_t)0x00000040)        </span>
<a name="l02715"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaed755173b9d4375b40d73cab90396adc">02715</a> <span class="preprocessor">#define  CAN_F10R2_FB7                       ((uint32_t)0x00000080)        </span>
<a name="l02716"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga8a8d08fea6e7307f6d1d602e113a6d27">02716</a> <span class="preprocessor">#define  CAN_F10R2_FB8                       ((uint32_t)0x00000100)        </span>
<a name="l02717"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga6aecdda55a484aa0e96c89f5d0f42aba">02717</a> <span class="preprocessor">#define  CAN_F10R2_FB9                       ((uint32_t)0x00000200)        </span>
<a name="l02718"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga4da658bf0a044b327c5efcc592e0ebe1">02718</a> <span class="preprocessor">#define  CAN_F10R2_FB10                      ((uint32_t)0x00000400)        </span>
<a name="l02719"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gae6ec91db97da763ae1da98ef3a3f7fea">02719</a> <span class="preprocessor">#define  CAN_F10R2_FB11                      ((uint32_t)0x00000800)        </span>
<a name="l02720"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga62bba82d177602a29448acf481a7f691">02720</a> <span class="preprocessor">#define  CAN_F10R2_FB12                      ((uint32_t)0x00001000)        </span>
<a name="l02721"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga6ce79aa37f7a175695fb910f986b7d81">02721</a> <span class="preprocessor">#define  CAN_F10R2_FB13                      ((uint32_t)0x00002000)        </span>
<a name="l02722"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gadf31488587e33ea32b60a5c21f3e3aff">02722</a> <span class="preprocessor">#define  CAN_F10R2_FB14                      ((uint32_t)0x00004000)        </span>
<a name="l02723"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gad8c7c289c07afb023bb3eedfe4d5a9b1">02723</a> <span class="preprocessor">#define  CAN_F10R2_FB15                      ((uint32_t)0x00008000)        </span>
<a name="l02724"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga74258ab493246fefc21ddc475dcfda4a">02724</a> <span class="preprocessor">#define  CAN_F10R2_FB16                      ((uint32_t)0x00010000)        </span>
<a name="l02725"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gabcf9f2daaa27f340a8cd4e64533f5caf">02725</a> <span class="preprocessor">#define  CAN_F10R2_FB17                      ((uint32_t)0x00020000)        </span>
<a name="l02726"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga2b8ad53931f4cb3bebb3f557d8686066">02726</a> <span class="preprocessor">#define  CAN_F10R2_FB18                      ((uint32_t)0x00040000)        </span>
<a name="l02727"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga9f0b00c508bddf59fd290091e738a340">02727</a> <span class="preprocessor">#define  CAN_F10R2_FB19                      ((uint32_t)0x00080000)        </span>
<a name="l02728"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gadb9db852d4bf1332f748a0cfc0063364">02728</a> <span class="preprocessor">#define  CAN_F10R2_FB20                      ((uint32_t)0x00100000)        </span>
<a name="l02729"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga616164fcd20341e4eed5b10a8fd2837c">02729</a> <span class="preprocessor">#define  CAN_F10R2_FB21                      ((uint32_t)0x00200000)        </span>
<a name="l02730"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gae70893925ea53547e9ce780c0480587b">02730</a> <span class="preprocessor">#define  CAN_F10R2_FB22                      ((uint32_t)0x00400000)        </span>
<a name="l02731"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaed74e80c74c6c5e12d26abbc0d923787">02731</a> <span class="preprocessor">#define  CAN_F10R2_FB23                      ((uint32_t)0x00800000)        </span>
<a name="l02732"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaecb5b90d073107f3c5612379aaffa7ce">02732</a> <span class="preprocessor">#define  CAN_F10R2_FB24                      ((uint32_t)0x01000000)        </span>
<a name="l02733"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga678702522f87f63edfcad21194be3c53">02733</a> <span class="preprocessor">#define  CAN_F10R2_FB25                      ((uint32_t)0x02000000)        </span>
<a name="l02734"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaf4523c34e7f333636fade643b895b8f5">02734</a> <span class="preprocessor">#define  CAN_F10R2_FB26                      ((uint32_t)0x04000000)        </span>
<a name="l02735"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gacf0e55fcb496970abe8fea481561f886">02735</a> <span class="preprocessor">#define  CAN_F10R2_FB27                      ((uint32_t)0x08000000)        </span>
<a name="l02736"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga4e4683223d46d60897b2c46b02addec5">02736</a> <span class="preprocessor">#define  CAN_F10R2_FB28                      ((uint32_t)0x10000000)        </span>
<a name="l02737"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga6df50371abf968f0638faf7e0bf76cc8">02737</a> <span class="preprocessor">#define  CAN_F10R2_FB29                      ((uint32_t)0x20000000)        </span>
<a name="l02738"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gab294aa73a3fdfc60672b206bd57a1e08">02738</a> <span class="preprocessor">#define  CAN_F10R2_FB30                      ((uint32_t)0x40000000)        </span>
<a name="l02739"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga2de1906dc4119b37b29bbe25e3e6dbe0">02739</a> <span class="preprocessor">#define  CAN_F10R2_FB31                      ((uint32_t)0x80000000)        </span>
<a name="l02741"></a>02741 <span class="preprocessor"></span><span class="comment">/*******************  Bit definition for CAN_F11R2 register  ******************/</span>
<a name="l02742"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gacad6560088b586891d446952bbd8fbbe">02742</a> <span class="preprocessor">#define  CAN_F11R2_FB0                       ((uint32_t)0x00000001)        </span>
<a name="l02743"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gac81bc667cb0c63aa0448f6e0eb1d105d">02743</a> <span class="preprocessor">#define  CAN_F11R2_FB1                       ((uint32_t)0x00000002)        </span>
<a name="l02744"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga8dab8868637d6d6fb707b6a37a5989b5">02744</a> <span class="preprocessor">#define  CAN_F11R2_FB2                       ((uint32_t)0x00000004)        </span>
<a name="l02745"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga559246cfa4658a5adaa282e4a3b35dd5">02745</a> <span class="preprocessor">#define  CAN_F11R2_FB3                       ((uint32_t)0x00000008)        </span>
<a name="l02746"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga499aebdfc0c14b9c399698e28fde3e50">02746</a> <span class="preprocessor">#define  CAN_F11R2_FB4                       ((uint32_t)0x00000010)        </span>
<a name="l02747"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga1613d097fe5b7107ff36f97a9263bd38">02747</a> <span class="preprocessor">#define  CAN_F11R2_FB5                       ((uint32_t)0x00000020)        </span>
<a name="l02748"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga9db1830185822d66619059a644d86ffe">02748</a> <span class="preprocessor">#define  CAN_F11R2_FB6                       ((uint32_t)0x00000040)        </span>
<a name="l02749"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gab35bedade0c9f71455abfbbac2edee14">02749</a> <span class="preprocessor">#define  CAN_F11R2_FB7                       ((uint32_t)0x00000080)        </span>
<a name="l02750"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gac79ac007ffed536eedddffdd2615c5f7">02750</a> <span class="preprocessor">#define  CAN_F11R2_FB8                       ((uint32_t)0x00000100)        </span>
<a name="l02751"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gad5900c2273c405ce35b9bd52b189c102">02751</a> <span class="preprocessor">#define  CAN_F11R2_FB9                       ((uint32_t)0x00000200)        </span>
<a name="l02752"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga9dad5ea347a6a928997a0a1c149369ce">02752</a> <span class="preprocessor">#define  CAN_F11R2_FB10                      ((uint32_t)0x00000400)        </span>
<a name="l02753"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga9285109080a523012f27b3bdbabc6949">02753</a> <span class="preprocessor">#define  CAN_F11R2_FB11                      ((uint32_t)0x00000800)        </span>
<a name="l02754"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga65cdf759738f8b0cb8c4c3231453aad8">02754</a> <span class="preprocessor">#define  CAN_F11R2_FB12                      ((uint32_t)0x00001000)        </span>
<a name="l02755"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga24a40efa6debcdcfef0f7ab6d8b3eb04">02755</a> <span class="preprocessor">#define  CAN_F11R2_FB13                      ((uint32_t)0x00002000)        </span>
<a name="l02756"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaa923634a3432436c4c84e65be1fd39d6">02756</a> <span class="preprocessor">#define  CAN_F11R2_FB14                      ((uint32_t)0x00004000)        </span>
<a name="l02757"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga65bae4ee01f83fe051acee8ee4c8a10e">02757</a> <span class="preprocessor">#define  CAN_F11R2_FB15                      ((uint32_t)0x00008000)        </span>
<a name="l02758"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga7b6762f3642ce7a06fff58270ac9f53f">02758</a> <span class="preprocessor">#define  CAN_F11R2_FB16                      ((uint32_t)0x00010000)        </span>
<a name="l02759"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga69c7d6a41708543278980035b64bd31b">02759</a> <span class="preprocessor">#define  CAN_F11R2_FB17                      ((uint32_t)0x00020000)        </span>
<a name="l02760"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga88d6d67020cbc5a4d5f0b7c5dc488aa6">02760</a> <span class="preprocessor">#define  CAN_F11R2_FB18                      ((uint32_t)0x00040000)        </span>
<a name="l02761"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga07f4a8d606f2063be35b52e1fc5e4b58">02761</a> <span class="preprocessor">#define  CAN_F11R2_FB19                      ((uint32_t)0x00080000)        </span>
<a name="l02762"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga58c6e5b0076c31b7bee1c9aea94e11fb">02762</a> <span class="preprocessor">#define  CAN_F11R2_FB20                      ((uint32_t)0x00100000)        </span>
<a name="l02763"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga93bf815d462dc3a40725f73e107e11f5">02763</a> <span class="preprocessor">#define  CAN_F11R2_FB21                      ((uint32_t)0x00200000)        </span>
<a name="l02764"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaeebe934727476f5fde11c888c424c417">02764</a> <span class="preprocessor">#define  CAN_F11R2_FB22                      ((uint32_t)0x00400000)        </span>
<a name="l02765"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga8324877e56a61c15119f2ebf929894cc">02765</a> <span class="preprocessor">#define  CAN_F11R2_FB23                      ((uint32_t)0x00800000)        </span>
<a name="l02766"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gadfd994c36da11529ac494df973b5759c">02766</a> <span class="preprocessor">#define  CAN_F11R2_FB24                      ((uint32_t)0x01000000)        </span>
<a name="l02767"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga8f3e9d272b625f7d6269057aee5d7761">02767</a> <span class="preprocessor">#define  CAN_F11R2_FB25                      ((uint32_t)0x02000000)        </span>
<a name="l02768"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga5da4d794a9797d14536197679b7b2b14">02768</a> <span class="preprocessor">#define  CAN_F11R2_FB26                      ((uint32_t)0x04000000)        </span>
<a name="l02769"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gad9b9a815f36e7c2929f4313ca424c83a">02769</a> <span class="preprocessor">#define  CAN_F11R2_FB27                      ((uint32_t)0x08000000)        </span>
<a name="l02770"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaf162471f4c070d13fa409d44467373fc">02770</a> <span class="preprocessor">#define  CAN_F11R2_FB28                      ((uint32_t)0x10000000)        </span>
<a name="l02771"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga2c301fd37e3fa27d3bd28a1f3f553e77">02771</a> <span class="preprocessor">#define  CAN_F11R2_FB29                      ((uint32_t)0x20000000)        </span>
<a name="l02772"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga2bdc4ba1d0e44ba4d7a03cfd3197b687">02772</a> <span class="preprocessor">#define  CAN_F11R2_FB30                      ((uint32_t)0x40000000)        </span>
<a name="l02773"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga6525c1ff364a229c9ea1b353b11be8c3">02773</a> <span class="preprocessor">#define  CAN_F11R2_FB31                      ((uint32_t)0x80000000)        </span>
<a name="l02775"></a>02775 <span class="preprocessor"></span><span class="comment">/*******************  Bit definition for CAN_F12R2 register  ******************/</span>
<a name="l02776"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gac5fd095552b3108c685514e78e43e52d">02776</a> <span class="preprocessor">#define  CAN_F12R2_FB0                       ((uint32_t)0x00000001)        </span>
<a name="l02777"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga450e88e19b2e478e73cbc5eef74a72d2">02777</a> <span class="preprocessor">#define  CAN_F12R2_FB1                       ((uint32_t)0x00000002)        </span>
<a name="l02778"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga17875db304b98c38e627f7d7db339136">02778</a> <span class="preprocessor">#define  CAN_F12R2_FB2                       ((uint32_t)0x00000004)        </span>
<a name="l02779"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga2960fee8bc56574e1b51975da7d2f041">02779</a> <span class="preprocessor">#define  CAN_F12R2_FB3                       ((uint32_t)0x00000008)        </span>
<a name="l02780"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga6b3b6f518fae0cb1123aa187138d90b6">02780</a> <span class="preprocessor">#define  CAN_F12R2_FB4                       ((uint32_t)0x00000010)        </span>
<a name="l02781"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga39cedc414fa80ef987825daf32e11ac4">02781</a> <span class="preprocessor">#define  CAN_F12R2_FB5                       ((uint32_t)0x00000020)        </span>
<a name="l02782"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga10aa07474c2e7cf7f2845d0d2b2bd383">02782</a> <span class="preprocessor">#define  CAN_F12R2_FB6                       ((uint32_t)0x00000040)        </span>
<a name="l02783"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga227ef5f36f6e03969cd952d62a3bc0a9">02783</a> <span class="preprocessor">#define  CAN_F12R2_FB7                       ((uint32_t)0x00000080)        </span>
<a name="l02784"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga7a946c991cee617b322ff9a372af3512">02784</a> <span class="preprocessor">#define  CAN_F12R2_FB8                       ((uint32_t)0x00000100)        </span>
<a name="l02785"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gad0ab582743e96fcd36662a9434b875bd">02785</a> <span class="preprocessor">#define  CAN_F12R2_FB9                       ((uint32_t)0x00000200)        </span>
<a name="l02786"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga854c2b7108e33d263cc8269648f8bbbe">02786</a> <span class="preprocessor">#define  CAN_F12R2_FB10                      ((uint32_t)0x00000400)        </span>
<a name="l02787"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga2ed3de0039e458bac5530d08c2e9af51">02787</a> <span class="preprocessor">#define  CAN_F12R2_FB11                      ((uint32_t)0x00000800)        </span>
<a name="l02788"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gadad0db6fe916794156f773e98b524b07">02788</a> <span class="preprocessor">#define  CAN_F12R2_FB12                      ((uint32_t)0x00001000)        </span>
<a name="l02789"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaa7a50bd0de8b4e85d9e90c1f48ef7bc8">02789</a> <span class="preprocessor">#define  CAN_F12R2_FB13                      ((uint32_t)0x00002000)        </span>
<a name="l02790"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga2c5558cc37c62c5570a5e2716e30ed99">02790</a> <span class="preprocessor">#define  CAN_F12R2_FB14                      ((uint32_t)0x00004000)        </span>
<a name="l02791"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga9fa511d56f90a2ee10e44e56e378f7ed">02791</a> <span class="preprocessor">#define  CAN_F12R2_FB15                      ((uint32_t)0x00008000)        </span>
<a name="l02792"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga77ae08ea078773a1aecbf74e89dc2a5d">02792</a> <span class="preprocessor">#define  CAN_F12R2_FB16                      ((uint32_t)0x00010000)        </span>
<a name="l02793"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga3a94ac3d4ba5c16a98fc04144ae3bb86">02793</a> <span class="preprocessor">#define  CAN_F12R2_FB17                      ((uint32_t)0x00020000)        </span>
<a name="l02794"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gae9070c9b9eec5dea6b5c4cdbaa1d5918">02794</a> <span class="preprocessor">#define  CAN_F12R2_FB18                      ((uint32_t)0x00040000)        </span>
<a name="l02795"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga758cacc8b96577bb3663da1fae36040b">02795</a> <span class="preprocessor">#define  CAN_F12R2_FB19                      ((uint32_t)0x00080000)        </span>
<a name="l02796"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga80db4704807d6df4aaee2eebfcf5210a">02796</a> <span class="preprocessor">#define  CAN_F12R2_FB20                      ((uint32_t)0x00100000)        </span>
<a name="l02797"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gac3d3fb3a9b4b6b90139024bef933bc3d">02797</a> <span class="preprocessor">#define  CAN_F12R2_FB21                      ((uint32_t)0x00200000)        </span>
<a name="l02798"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga24e87973f51235e81195d84f78489cb0">02798</a> <span class="preprocessor">#define  CAN_F12R2_FB22                      ((uint32_t)0x00400000)        </span>
<a name="l02799"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga4e917f2a362569d86a75a34eddce636c">02799</a> <span class="preprocessor">#define  CAN_F12R2_FB23                      ((uint32_t)0x00800000)        </span>
<a name="l02800"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gad6e5f2c5de8981fbfc152926fc8fb057">02800</a> <span class="preprocessor">#define  CAN_F12R2_FB24                      ((uint32_t)0x01000000)        </span>
<a name="l02801"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaaad1149501e8f926a247aa532405c0b9">02801</a> <span class="preprocessor">#define  CAN_F12R2_FB25                      ((uint32_t)0x02000000)        </span>
<a name="l02802"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga53538969afd7e43cc7fed4c400ab6f5a">02802</a> <span class="preprocessor">#define  CAN_F12R2_FB26                      ((uint32_t)0x04000000)        </span>
<a name="l02803"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga74e04fa5d17a7cc7687c0ca40dd571ce">02803</a> <span class="preprocessor">#define  CAN_F12R2_FB27                      ((uint32_t)0x08000000)        </span>
<a name="l02804"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gadc1d97354c1649fa5ddc46f4271297d9">02804</a> <span class="preprocessor">#define  CAN_F12R2_FB28                      ((uint32_t)0x10000000)        </span>
<a name="l02805"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga71b870003e469dcb24979e835a2f81a4">02805</a> <span class="preprocessor">#define  CAN_F12R2_FB29                      ((uint32_t)0x20000000)        </span>
<a name="l02806"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga2894b732a9683d32620fb90b06ba9f62">02806</a> <span class="preprocessor">#define  CAN_F12R2_FB30                      ((uint32_t)0x40000000)        </span>
<a name="l02807"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gab11cddebcb4e1ab70b7222a999d0c58a">02807</a> <span class="preprocessor">#define  CAN_F12R2_FB31                      ((uint32_t)0x80000000)        </span>
<a name="l02809"></a>02809 <span class="preprocessor"></span><span class="comment">/*******************  Bit definition for CAN_F13R2 register  ******************/</span>
<a name="l02810"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga0b6865be0c757b49a250a537d73ae85e">02810</a> <span class="preprocessor">#define  CAN_F13R2_FB0                       ((uint32_t)0x00000001)        </span>
<a name="l02811"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaf18df9b2fd549b8991fdd9f8f94e7cbb">02811</a> <span class="preprocessor">#define  CAN_F13R2_FB1                       ((uint32_t)0x00000002)        </span>
<a name="l02812"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga034e8f5b7675ce34eb2792531c7e174d">02812</a> <span class="preprocessor">#define  CAN_F13R2_FB2                       ((uint32_t)0x00000004)        </span>
<a name="l02813"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaf19767c0892dffb6eff8c5a3b0e254f5">02813</a> <span class="preprocessor">#define  CAN_F13R2_FB3                       ((uint32_t)0x00000008)        </span>
<a name="l02814"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gad03b0ab4d686a1ad858f1ba4b679fff9">02814</a> <span class="preprocessor">#define  CAN_F13R2_FB4                       ((uint32_t)0x00000010)        </span>
<a name="l02815"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga8e37522978ae2e88c27f5604c5517d42">02815</a> <span class="preprocessor">#define  CAN_F13R2_FB5                       ((uint32_t)0x00000020)        </span>
<a name="l02816"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga2bf6fff2ca4adf6e093a13b2db77adbb">02816</a> <span class="preprocessor">#define  CAN_F13R2_FB6                       ((uint32_t)0x00000040)        </span>
<a name="l02817"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gabca970c306c9c9b576ef3424f686f324">02817</a> <span class="preprocessor">#define  CAN_F13R2_FB7                       ((uint32_t)0x00000080)        </span>
<a name="l02818"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gae44e1d120c773c9dc26f418acf3cb6de">02818</a> <span class="preprocessor">#define  CAN_F13R2_FB8                       ((uint32_t)0x00000100)        </span>
<a name="l02819"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga891d1d97e1a57c4cfa1a714b61b083eb">02819</a> <span class="preprocessor">#define  CAN_F13R2_FB9                       ((uint32_t)0x00000200)        </span>
<a name="l02820"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gafb4be9c1da46b251c43c0aafe7b04497">02820</a> <span class="preprocessor">#define  CAN_F13R2_FB10                      ((uint32_t)0x00000400)        </span>
<a name="l02821"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga47f5215de00574378a489f90eb11eff4">02821</a> <span class="preprocessor">#define  CAN_F13R2_FB11                      ((uint32_t)0x00000800)        </span>
<a name="l02822"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gac3bbd5350aeb18966e2a40e2dc4223e3">02822</a> <span class="preprocessor">#define  CAN_F13R2_FB12                      ((uint32_t)0x00001000)        </span>
<a name="l02823"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gab2d97199e363dd56cd9a455aec75ef1c">02823</a> <span class="preprocessor">#define  CAN_F13R2_FB13                      ((uint32_t)0x00002000)        </span>
<a name="l02824"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga0731f4e60125130bebf88d33fd4ae3ca">02824</a> <span class="preprocessor">#define  CAN_F13R2_FB14                      ((uint32_t)0x00004000)        </span>
<a name="l02825"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga1683c0cc3b3143a919f4dd59243eba9f">02825</a> <span class="preprocessor">#define  CAN_F13R2_FB15                      ((uint32_t)0x00008000)        </span>
<a name="l02826"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gad2ed74a0929c6d397c14f49f114f13bf">02826</a> <span class="preprocessor">#define  CAN_F13R2_FB16                      ((uint32_t)0x00010000)        </span>
<a name="l02827"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gafde6cdff22bf29d31b5be1b309fe4dde">02827</a> <span class="preprocessor">#define  CAN_F13R2_FB17                      ((uint32_t)0x00020000)        </span>
<a name="l02828"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gabb873fa1c32fbf6c5a2f3be93ba2f2e6">02828</a> <span class="preprocessor">#define  CAN_F13R2_FB18                      ((uint32_t)0x00040000)        </span>
<a name="l02829"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaf82a4dfd4d3c7a13232479be997ed1f9">02829</a> <span class="preprocessor">#define  CAN_F13R2_FB19                      ((uint32_t)0x00080000)        </span>
<a name="l02830"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaa7bf4384e44f002392339a71bc9c912c">02830</a> <span class="preprocessor">#define  CAN_F13R2_FB20                      ((uint32_t)0x00100000)        </span>
<a name="l02831"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaa7023986be02dd8f736e04e658844061">02831</a> <span class="preprocessor">#define  CAN_F13R2_FB21                      ((uint32_t)0x00200000)        </span>
<a name="l02832"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gafd059121f2a882342a409ebef8a96999">02832</a> <span class="preprocessor">#define  CAN_F13R2_FB22                      ((uint32_t)0x00400000)        </span>
<a name="l02833"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga5ef57f88bf1e6e34b0096013278926c0">02833</a> <span class="preprocessor">#define  CAN_F13R2_FB23                      ((uint32_t)0x00800000)        </span>
<a name="l02834"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga4847de9f5b54fc5ce00e0fba69564d2d">02834</a> <span class="preprocessor">#define  CAN_F13R2_FB24                      ((uint32_t)0x01000000)        </span>
<a name="l02835"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga2c415fa87c556bd8a4fc0f680d25f160">02835</a> <span class="preprocessor">#define  CAN_F13R2_FB25                      ((uint32_t)0x02000000)        </span>
<a name="l02836"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga20487222c41a08fe68b9ce58dfd52fff">02836</a> <span class="preprocessor">#define  CAN_F13R2_FB26                      ((uint32_t)0x04000000)        </span>
<a name="l02837"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaa0d5ca021778a6e84fd3c0ad8981255d">02837</a> <span class="preprocessor">#define  CAN_F13R2_FB27                      ((uint32_t)0x08000000)        </span>
<a name="l02838"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga2f0c8c09be20a14f29ab46d53dd712ba">02838</a> <span class="preprocessor">#define  CAN_F13R2_FB28                      ((uint32_t)0x10000000)        </span>
<a name="l02839"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga26161b84a5fc507f959b620c8e380703">02839</a> <span class="preprocessor">#define  CAN_F13R2_FB29                      ((uint32_t)0x20000000)        </span>
<a name="l02840"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga1e753550a0a8547c7f64346e22925012">02840</a> <span class="preprocessor">#define  CAN_F13R2_FB30                      ((uint32_t)0x40000000)        </span>
<a name="l02841"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga305ac04b1c5198a4f82c78c570ce7f97">02841</a> <span class="preprocessor">#define  CAN_F13R2_FB31                      ((uint32_t)0x80000000)        </span>
<a name="l02843"></a>02843 <span class="preprocessor"></span><span class="comment">/******************************************************************************/</span>
<a name="l02844"></a>02844 <span class="comment">/*                                                                            */</span>
<a name="l02845"></a>02845 <span class="comment">/*                          CRC calculation unit                              */</span>
<a name="l02846"></a>02846 <span class="comment">/*                                                                            */</span>
<a name="l02847"></a>02847 <span class="comment">/******************************************************************************/</span>
<a name="l02848"></a>02848 <span class="comment">/*******************  Bit definition for CRC_DR register  *********************/</span>
<a name="l02849"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga2bf4701d3b15924e657942ce3caa4105">02849</a> <span class="preprocessor">#define  CRC_DR_DR                           ((uint32_t)0xFFFFFFFF) </span>
<a name="l02852"></a>02852 <span class="preprocessor"></span><span class="comment">/*******************  Bit definition for CRC_IDR register  ********************/</span>
<a name="l02853"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gae9a0feb3cf1d8c5871e663ca4a174cc0">02853</a> <span class="preprocessor">#define  CRC_IDR_IDR                         ((uint8_t)0xFF)        </span>
<a name="l02856"></a>02856 <span class="preprocessor"></span><span class="comment">/********************  Bit definition for CRC_CR register  ********************/</span>
<a name="l02857"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga7d57481fb891a0964b40f721354c56d7">02857</a> <span class="preprocessor">#define  CRC_CR_RESET                        ((uint8_t)0x01)        </span>
<a name="l02859"></a>02859 <span class="preprocessor"></span><span class="comment">/******************************************************************************/</span>
<a name="l02860"></a>02860 <span class="comment">/*                                                                            */</span>
<a name="l02861"></a>02861 <span class="comment">/*                            Crypto Processor                                */</span>
<a name="l02862"></a>02862 <span class="comment">/*                                                                            */</span>
<a name="l02863"></a>02863 <span class="comment">/******************************************************************************/</span>
<a name="l02864"></a>02864 <span class="comment">/******************* Bits definition for CRYP_CR register  ********************/</span>
<a name="l02865"></a>02865 <span class="preprocessor">#define CRYP_CR_ALGODIR                      ((uint32_t)0x00000004)</span>
<a name="l02866"></a>02866 <span class="preprocessor"></span>
<a name="l02867"></a>02867 <span class="preprocessor">#define CRYP_CR_ALGOMODE                     ((uint32_t)0x00000038)</span>
<a name="l02868"></a>02868 <span class="preprocessor"></span><span class="preprocessor">#define CRYP_CR_ALGOMODE_0                   ((uint32_t)0x00000008)</span>
<a name="l02869"></a>02869 <span class="preprocessor"></span><span class="preprocessor">#define CRYP_CR_ALGOMODE_1                   ((uint32_t)0x00000010)</span>
<a name="l02870"></a>02870 <span class="preprocessor"></span><span class="preprocessor">#define CRYP_CR_ALGOMODE_2                   ((uint32_t)0x00000020)</span>
<a name="l02871"></a>02871 <span class="preprocessor"></span><span class="preprocessor">#define CRYP_CR_ALGOMODE_TDES_ECB            ((uint32_t)0x00000000)</span>
<a name="l02872"></a>02872 <span class="preprocessor"></span><span class="preprocessor">#define CRYP_CR_ALGOMODE_TDES_CBC            ((uint32_t)0x00000008)</span>
<a name="l02873"></a>02873 <span class="preprocessor"></span><span class="preprocessor">#define CRYP_CR_ALGOMODE_DES_ECB             ((uint32_t)0x00000010)</span>
<a name="l02874"></a>02874 <span class="preprocessor"></span><span class="preprocessor">#define CRYP_CR_ALGOMODE_DES_CBC             ((uint32_t)0x00000018)</span>
<a name="l02875"></a>02875 <span class="preprocessor"></span><span class="preprocessor">#define CRYP_CR_ALGOMODE_AES_ECB             ((uint32_t)0x00000020)</span>
<a name="l02876"></a>02876 <span class="preprocessor"></span><span class="preprocessor">#define CRYP_CR_ALGOMODE_AES_CBC             ((uint32_t)0x00000028)</span>
<a name="l02877"></a>02877 <span class="preprocessor"></span><span class="preprocessor">#define CRYP_CR_ALGOMODE_AES_CTR             ((uint32_t)0x00000030)</span>
<a name="l02878"></a>02878 <span class="preprocessor"></span><span class="preprocessor">#define CRYP_CR_ALGOMODE_AES_KEY             ((uint32_t)0x00000038)</span>
<a name="l02879"></a>02879 <span class="preprocessor"></span>
<a name="l02880"></a>02880 <span class="preprocessor">#define CRYP_CR_DATATYPE                     ((uint32_t)0x000000C0)</span>
<a name="l02881"></a>02881 <span class="preprocessor"></span><span class="preprocessor">#define CRYP_CR_DATATYPE_0                   ((uint32_t)0x00000040)</span>
<a name="l02882"></a>02882 <span class="preprocessor"></span><span class="preprocessor">#define CRYP_CR_DATATYPE_1                   ((uint32_t)0x00000080)</span>
<a name="l02883"></a>02883 <span class="preprocessor"></span><span class="preprocessor">#define CRYP_CR_KEYSIZE                      ((uint32_t)0x00000300)</span>
<a name="l02884"></a>02884 <span class="preprocessor"></span><span class="preprocessor">#define CRYP_CR_KEYSIZE_0                    ((uint32_t)0x00000100)</span>
<a name="l02885"></a>02885 <span class="preprocessor"></span><span class="preprocessor">#define CRYP_CR_KEYSIZE_1                    ((uint32_t)0x00000200)</span>
<a name="l02886"></a>02886 <span class="preprocessor"></span><span class="preprocessor">#define CRYP_CR_FFLUSH                       ((uint32_t)0x00004000)</span>
<a name="l02887"></a>02887 <span class="preprocessor"></span><span class="preprocessor">#define CRYP_CR_CRYPEN                       ((uint32_t)0x00008000)</span>
<a name="l02888"></a>02888 <span class="preprocessor"></span><span class="comment">/****************** Bits definition for CRYP_SR register  *********************/</span>
<a name="l02889"></a>02889 <span class="preprocessor">#define CRYP_SR_IFEM                         ((uint32_t)0x00000001)</span>
<a name="l02890"></a>02890 <span class="preprocessor"></span><span class="preprocessor">#define CRYP_SR_IFNF                         ((uint32_t)0x00000002)</span>
<a name="l02891"></a>02891 <span class="preprocessor"></span><span class="preprocessor">#define CRYP_SR_OFNE                         ((uint32_t)0x00000004)</span>
<a name="l02892"></a>02892 <span class="preprocessor"></span><span class="preprocessor">#define CRYP_SR_OFFU                         ((uint32_t)0x00000008)</span>
<a name="l02893"></a>02893 <span class="preprocessor"></span><span class="preprocessor">#define CRYP_SR_BUSY                         ((uint32_t)0x00000010)</span>
<a name="l02894"></a>02894 <span class="preprocessor"></span><span class="comment">/****************** Bits definition for CRYP_DMACR register  ******************/</span>
<a name="l02895"></a>02895 <span class="preprocessor">#define CRYP_DMACR_DIEN                      ((uint32_t)0x00000001)</span>
<a name="l02896"></a>02896 <span class="preprocessor"></span><span class="preprocessor">#define CRYP_DMACR_DOEN                      ((uint32_t)0x00000002)</span>
<a name="l02897"></a>02897 <span class="preprocessor"></span><span class="comment">/*****************  Bits definition for CRYP_IMSCR register  ******************/</span>
<a name="l02898"></a>02898 <span class="preprocessor">#define CRYP_IMSCR_INIM                      ((uint32_t)0x00000001)</span>
<a name="l02899"></a>02899 <span class="preprocessor"></span><span class="preprocessor">#define CRYP_IMSCR_OUTIM                     ((uint32_t)0x00000002)</span>
<a name="l02900"></a>02900 <span class="preprocessor"></span><span class="comment">/****************** Bits definition for CRYP_RISR register  *******************/</span>
<a name="l02901"></a>02901 <span class="preprocessor">#define CRYP_RISR_OUTRIS                     ((uint32_t)0x00000001)</span>
<a name="l02902"></a>02902 <span class="preprocessor"></span><span class="preprocessor">#define CRYP_RISR_INRIS                      ((uint32_t)0x00000002)</span>
<a name="l02903"></a>02903 <span class="preprocessor"></span><span class="comment">/****************** Bits definition for CRYP_MISR register  *******************/</span>
<a name="l02904"></a>02904 <span class="preprocessor">#define CRYP_MISR_INMIS                      ((uint32_t)0x00000001)</span>
<a name="l02905"></a>02905 <span class="preprocessor"></span><span class="preprocessor">#define CRYP_MISR_OUTMIS                     ((uint32_t)0x00000002)</span>
<a name="l02906"></a>02906 <span class="preprocessor"></span>
<a name="l02907"></a>02907 <span class="comment">/******************************************************************************/</span>
<a name="l02908"></a>02908 <span class="comment">/*                                                                            */</span>
<a name="l02909"></a>02909 <span class="comment">/*                      Digital to Analog Converter                           */</span>
<a name="l02910"></a>02910 <span class="comment">/*                                                                            */</span>
<a name="l02911"></a>02911 <span class="comment">/******************************************************************************/</span>
<a name="l02912"></a>02912 <span class="comment">/********************  Bit definition for DAC_CR register  ********************/</span>
<a name="l02913"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gabd8cedbb3dda03d56ac0ba92d2d9cefd">02913</a> <span class="preprocessor">#define  DAC_CR_EN1                          ((uint32_t)0x00000001)        </span>
<a name="l02914"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga0b1e2b83ae1ab889cb1e34a99746c9d8">02914</a> <span class="preprocessor">#define  DAC_CR_BOFF1                        ((uint32_t)0x00000002)        </span>
<a name="l02915"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga998aa4fd791ea2f4626df6ddc8fc7109">02915</a> <span class="preprocessor">#define  DAC_CR_TEN1                         ((uint32_t)0x00000004)        </span>
<a name="l02917"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaf951c1a57a1a19e356df57d908f09c6c">02917</a> <span class="preprocessor">#define  DAC_CR_TSEL1                        ((uint32_t)0x00000038)        </span>
<a name="l02918"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga8dfa13ec123c583136e24b7890add45b">02918</a> <span class="preprocessor">#define  DAC_CR_TSEL1_0                      ((uint32_t)0x00000008)        </span>
<a name="l02919"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga265e32c4fc43310acdf3ebea01376766">02919</a> <span class="preprocessor">#define  DAC_CR_TSEL1_1                      ((uint32_t)0x00000010)        </span>
<a name="l02920"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaa625d7638422e90a616ac93edd4bf408">02920</a> <span class="preprocessor">#define  DAC_CR_TSEL1_2                      ((uint32_t)0x00000020)        </span>
<a name="l02922"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga90491f31219d07175629eecdcdc9271e">02922</a> <span class="preprocessor">#define  DAC_CR_WAVE1                        ((uint32_t)0x000000C0)        </span>
<a name="l02923"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga0871e6466e3a7378103c431832ae525a">02923</a> <span class="preprocessor">#define  DAC_CR_WAVE1_0                      ((uint32_t)0x00000040)        </span>
<a name="l02924"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga48e167ae02d2ad5bc9fd30c2f8ea5b37">02924</a> <span class="preprocessor">#define  DAC_CR_WAVE1_1                      ((uint32_t)0x00000080)        </span>
<a name="l02926"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga3bcf611b2f0b975513325895bf16e085">02926</a> <span class="preprocessor">#define  DAC_CR_MAMP1                        ((uint32_t)0x00000F00)        </span>
<a name="l02927"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga4225dcce22b440fcd3a8ad96c5f2baec">02927</a> <span class="preprocessor">#define  DAC_CR_MAMP1_0                      ((uint32_t)0x00000100)        </span>
<a name="l02928"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga6cc15817842cb7992d449c448684f68d">02928</a> <span class="preprocessor">#define  DAC_CR_MAMP1_1                      ((uint32_t)0x00000200)        </span>
<a name="l02929"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga0fefef1d798a2685b03e44bd9fdac06b">02929</a> <span class="preprocessor">#define  DAC_CR_MAMP1_2                      ((uint32_t)0x00000400)        </span>
<a name="l02930"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gafdc83b4feb742c632ba66f55d102432b">02930</a> <span class="preprocessor">#define  DAC_CR_MAMP1_3                      ((uint32_t)0x00000800)        </span>
<a name="l02932"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga995c19d8c8de9ee09057ec6151154e17">02932</a> <span class="preprocessor">#define  DAC_CR_DMAEN1                       ((uint32_t)0x00001000)        </span>
<a name="l02933"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaa65db2420e02fc6813842f57134d898f">02933</a> <span class="preprocessor">#define  DAC_CR_EN2                          ((uint32_t)0x00010000)        </span>
<a name="l02934"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gadd6f660a5f15262beca06b9098a559e9">02934</a> <span class="preprocessor">#define  DAC_CR_BOFF2                        ((uint32_t)0x00020000)        </span>
<a name="l02935"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gab8fc527f6ddb787123da09d2085b772f">02935</a> <span class="preprocessor">#define  DAC_CR_TEN2                         ((uint32_t)0x00040000)        </span>
<a name="l02937"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga73b4d0ccff78f7c3862903e7b0e66302">02937</a> <span class="preprocessor">#define  DAC_CR_TSEL2                        ((uint32_t)0x00380000)        </span>
<a name="l02938"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga9753b87f31e7106ecf77b2f01a99b237">02938</a> <span class="preprocessor">#define  DAC_CR_TSEL2_0                      ((uint32_t)0x00080000)        </span>
<a name="l02939"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gac79323a6c81bfa5c8239b23cd3db737a">02939</a> <span class="preprocessor">#define  DAC_CR_TSEL2_1                      ((uint32_t)0x00100000)        </span>
<a name="l02940"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga9ad3da8a9c5fe9566d8ffe38916caaff">02940</a> <span class="preprocessor">#define  DAC_CR_TSEL2_2                      ((uint32_t)0x00200000)        </span>
<a name="l02942"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gacf24e48cf288db4a4643057dd09e3a7b">02942</a> <span class="preprocessor">#define  DAC_CR_WAVE2                        ((uint32_t)0x00C00000)        </span>
<a name="l02943"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga55d97d8bcbfdd72d5aeb9e9fbc0d592d">02943</a> <span class="preprocessor">#define  DAC_CR_WAVE2_0                      ((uint32_t)0x00400000)        </span>
<a name="l02944"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga4798bf254010b442b4ac4288c2f1b65f">02944</a> <span class="preprocessor">#define  DAC_CR_WAVE2_1                      ((uint32_t)0x00800000)        </span>
<a name="l02946"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga7cf03fe2359cb0f11c33f793c2e92bdd">02946</a> <span class="preprocessor">#define  DAC_CR_MAMP2                        ((uint32_t)0x0F000000)        </span>
<a name="l02947"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gae8d952192721dbdcea8d707d43096454">02947</a> <span class="preprocessor">#define  DAC_CR_MAMP2_0                      ((uint32_t)0x01000000)        </span>
<a name="l02948"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga860032e8196838cd36a655c1749139d6">02948</a> <span class="preprocessor">#define  DAC_CR_MAMP2_1                      ((uint32_t)0x02000000)        </span>
<a name="l02949"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga2147ffa3282e9ff22475e5d6040f269e">02949</a> <span class="preprocessor">#define  DAC_CR_MAMP2_2                      ((uint32_t)0x04000000)        </span>
<a name="l02950"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaa0fe77a2029873111cbe723a5cba9c57">02950</a> <span class="preprocessor">#define  DAC_CR_MAMP2_3                      ((uint32_t)0x08000000)        </span>
<a name="l02952"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga6f905c2ac89f976df6c4beffdde58b53">02952</a> <span class="preprocessor">#define  DAC_CR_DMAEN2                       ((uint32_t)0x10000000)        </span>
<a name="l02954"></a>02954 <span class="preprocessor"></span><span class="comment">/*****************  Bit definition for DAC_SWTRIGR register  ******************/</span>
<a name="l02955"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga970ef02dffaceb35ff1dd7aceb67acdd">02955</a> <span class="preprocessor">#define  DAC_SWTRIGR_SWTRIG1                 ((uint8_t)0x01)               </span>
<a name="l02956"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaf0e53585b505d21f5c457476bd5a18f8">02956</a> <span class="preprocessor">#define  DAC_SWTRIGR_SWTRIG2                 ((uint8_t)0x02)               </span>
<a name="l02958"></a>02958 <span class="preprocessor"></span><span class="comment">/*****************  Bit definition for DAC_DHR12R1 register  ******************/</span>
<a name="l02959"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga5295b5cb7f5d71ed2e8a310deb00013d">02959</a> <span class="preprocessor">#define  DAC_DHR12R1_DACC1DHR                ((uint16_t)0x0FFF)            </span>
<a name="l02961"></a>02961 <span class="preprocessor"></span><span class="comment">/*****************  Bit definition for DAC_DHR12L1 register  ******************/</span>
<a name="l02962"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga0d34667f8f4b753689c8c936c28471c5">02962</a> <span class="preprocessor">#define  DAC_DHR12L1_DACC1DHR                ((uint16_t)0xFFF0)            </span>
<a name="l02964"></a>02964 <span class="preprocessor"></span><span class="comment">/******************  Bit definition for DAC_DHR8R1 register  ******************/</span>
<a name="l02965"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gae1fc9f022fe4a08f67c51646177b26cb">02965</a> <span class="preprocessor">#define  DAC_DHR8R1_DACC1DHR                 ((uint8_t)0xFF)               </span>
<a name="l02967"></a>02967 <span class="preprocessor"></span><span class="comment">/*****************  Bit definition for DAC_DHR12R2 register  ******************/</span>
<a name="l02968"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga7506e369b37d55826042b540b10e44c7">02968</a> <span class="preprocessor">#define  DAC_DHR12R2_DACC2DHR                ((uint16_t)0x0FFF)            </span>
<a name="l02970"></a>02970 <span class="preprocessor"></span><span class="comment">/*****************  Bit definition for DAC_DHR12L2 register  ******************/</span>
<a name="l02971"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga0f66bd794202221e1a55547673b7abab">02971</a> <span class="preprocessor">#define  DAC_DHR12L2_DACC2DHR                ((uint16_t)0xFFF0)            </span>
<a name="l02973"></a>02973 <span class="preprocessor"></span><span class="comment">/******************  Bit definition for DAC_DHR8R2 register  ******************/</span>
<a name="l02974"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga7da94dc053e6637efb9ccb57b7ae481c">02974</a> <span class="preprocessor">#define  DAC_DHR8R2_DACC2DHR                 ((uint8_t)0xFF)               </span>
<a name="l02976"></a>02976 <span class="preprocessor"></span><span class="comment">/*****************  Bit definition for DAC_DHR12RD register  ******************/</span>
<a name="l02977"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaca45719f3d365c9495bdcf6364ae59f8">02977</a> <span class="preprocessor">#define  DAC_DHR12RD_DACC1DHR                ((uint32_t)0x00000FFF)        </span>
<a name="l02978"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga3edd68db1697af93027e05f6b764c540">02978</a> <span class="preprocessor">#define  DAC_DHR12RD_DACC2DHR                ((uint32_t)0x0FFF0000)        </span>
<a name="l02980"></a>02980 <span class="preprocessor"></span><span class="comment">/*****************  Bit definition for DAC_DHR12LD register  ******************/</span>
<a name="l02981"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga203db656bfef6fedee17b99fb77b1bdd">02981</a> <span class="preprocessor">#define  DAC_DHR12LD_DACC1DHR                ((uint32_t)0x0000FFF0)        </span>
<a name="l02982"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga8421d613b182aab8d6c58592bcda6c17">02982</a> <span class="preprocessor">#define  DAC_DHR12LD_DACC2DHR                ((uint32_t)0xFFF00000)        </span>
<a name="l02984"></a>02984 <span class="preprocessor"></span><span class="comment">/******************  Bit definition for DAC_DHR8RD register  ******************/</span>
<a name="l02985"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga9aee01ad181fa5b541864ed62907d70d">02985</a> <span class="preprocessor">#define  DAC_DHR8RD_DACC1DHR                 ((uint16_t)0x00FF)            </span>
<a name="l02986"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gae31631eaac76ebecb059918c351ef3c9">02986</a> <span class="preprocessor">#define  DAC_DHR8RD_DACC2DHR                 ((uint16_t)0xFF00)            </span>
<a name="l02988"></a>02988 <span class="preprocessor"></span><span class="comment">/*******************  Bit definition for DAC_DOR1 register  *******************/</span>
<a name="l02989"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga5b4192938e039dc25a7df8fcc5f3932a">02989</a> <span class="preprocessor">#define  DAC_DOR1_DACC1DOR                   ((uint16_t)0x0FFF)            </span>
<a name="l02991"></a>02991 <span class="preprocessor"></span><span class="comment">/*******************  Bit definition for DAC_DOR2 register  *******************/</span>
<a name="l02992"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gacaaa39c1e82279918918b072fd56db04">02992</a> <span class="preprocessor">#define  DAC_DOR2_DACC2DOR                   ((uint16_t)0x0FFF)            </span>
<a name="l02994"></a>02994 <span class="preprocessor"></span><span class="comment">/********************  Bit definition for DAC_SR register  ********************/</span>
<a name="l02995"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga7d2048d6b521fb0946dc8c4e577a49c0">02995</a> <span class="preprocessor">#define  DAC_SR_DMAUDR1                      ((uint32_t)0x00002000)        </span>
<a name="l02996"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaf16e48ab85d9261c5b599c56b14aea5d">02996</a> <span class="preprocessor">#define  DAC_SR_DMAUDR2                      ((uint32_t)0x20000000)        </span>
<a name="l02998"></a>02998 <span class="preprocessor"></span><span class="comment">/******************************************************************************/</span>
<a name="l02999"></a>02999 <span class="comment">/*                                                                            */</span>
<a name="l03000"></a>03000 <span class="comment">/*                                 Debug MCU                                  */</span>
<a name="l03001"></a>03001 <span class="comment">/*                                                                            */</span>
<a name="l03002"></a>03002 <span class="comment">/******************************************************************************/</span>
<a name="l03003"></a>03003 
<a name="l03004"></a>03004 <span class="comment">/******************************************************************************/</span>
<a name="l03005"></a>03005 <span class="comment">/*                                                                            */</span>
<a name="l03006"></a>03006 <span class="comment">/*                                    DCMI                                    */</span>
<a name="l03007"></a>03007 <span class="comment">/*                                                                            */</span>
<a name="l03008"></a>03008 <span class="comment">/******************************************************************************/</span>
<a name="l03009"></a>03009 <span class="comment">/********************  Bits definition for DCMI_CR register  ******************/</span>
<a name="l03010"></a>03010 <span class="preprocessor">#define DCMI_CR_CAPTURE                      ((uint32_t)0x00000001)</span>
<a name="l03011"></a>03011 <span class="preprocessor"></span><span class="preprocessor">#define DCMI_CR_CM                           ((uint32_t)0x00000002)</span>
<a name="l03012"></a>03012 <span class="preprocessor"></span><span class="preprocessor">#define DCMI_CR_CROP                         ((uint32_t)0x00000004)</span>
<a name="l03013"></a>03013 <span class="preprocessor"></span><span class="preprocessor">#define DCMI_CR_JPEG                         ((uint32_t)0x00000008)</span>
<a name="l03014"></a>03014 <span class="preprocessor"></span><span class="preprocessor">#define DCMI_CR_ESS                          ((uint32_t)0x00000010)</span>
<a name="l03015"></a>03015 <span class="preprocessor"></span><span class="preprocessor">#define DCMI_CR_PCKPOL                       ((uint32_t)0x00000020)</span>
<a name="l03016"></a>03016 <span class="preprocessor"></span><span class="preprocessor">#define DCMI_CR_HSPOL                        ((uint32_t)0x00000040)</span>
<a name="l03017"></a>03017 <span class="preprocessor"></span><span class="preprocessor">#define DCMI_CR_VSPOL                        ((uint32_t)0x00000080)</span>
<a name="l03018"></a>03018 <span class="preprocessor"></span><span class="preprocessor">#define DCMI_CR_FCRC_0                       ((uint32_t)0x00000100)</span>
<a name="l03019"></a>03019 <span class="preprocessor"></span><span class="preprocessor">#define DCMI_CR_FCRC_1                       ((uint32_t)0x00000200)</span>
<a name="l03020"></a>03020 <span class="preprocessor"></span><span class="preprocessor">#define DCMI_CR_EDM_0                        ((uint32_t)0x00000400)</span>
<a name="l03021"></a>03021 <span class="preprocessor"></span><span class="preprocessor">#define DCMI_CR_EDM_1                        ((uint32_t)0x00000800)</span>
<a name="l03022"></a>03022 <span class="preprocessor"></span><span class="preprocessor">#define DCMI_CR_CRE                          ((uint32_t)0x00001000)</span>
<a name="l03023"></a>03023 <span class="preprocessor"></span><span class="preprocessor">#define DCMI_CR_ENABLE                       ((uint32_t)0x00004000)</span>
<a name="l03024"></a>03024 <span class="preprocessor"></span>
<a name="l03025"></a>03025 <span class="comment">/********************  Bits definition for DCMI_SR register  ******************/</span>
<a name="l03026"></a>03026 <span class="preprocessor">#define DCMI_SR_HSYNC                        ((uint32_t)0x00000001)</span>
<a name="l03027"></a>03027 <span class="preprocessor"></span><span class="preprocessor">#define DCMI_SR_VSYNC                        ((uint32_t)0x00000002)</span>
<a name="l03028"></a>03028 <span class="preprocessor"></span><span class="preprocessor">#define DCMI_SR_FNE                          ((uint32_t)0x00000004)</span>
<a name="l03029"></a>03029 <span class="preprocessor"></span>
<a name="l03030"></a>03030 <span class="comment">/********************  Bits definition for DCMI_RISR register  ****************/</span>
<a name="l03031"></a>03031 <span class="preprocessor">#define DCMI_RISR_FRAME_RIS                  ((uint32_t)0x00000001)</span>
<a name="l03032"></a>03032 <span class="preprocessor"></span><span class="preprocessor">#define DCMI_RISR_OVF_RIS                    ((uint32_t)0x00000002)</span>
<a name="l03033"></a>03033 <span class="preprocessor"></span><span class="preprocessor">#define DCMI_RISR_ERR_RIS                    ((uint32_t)0x00000004)</span>
<a name="l03034"></a>03034 <span class="preprocessor"></span><span class="preprocessor">#define DCMI_RISR_VSYNC_RIS                  ((uint32_t)0x00000008)</span>
<a name="l03035"></a>03035 <span class="preprocessor"></span><span class="preprocessor">#define DCMI_RISR_LINE_RIS                   ((uint32_t)0x00000010)</span>
<a name="l03036"></a>03036 <span class="preprocessor"></span>
<a name="l03037"></a>03037 <span class="comment">/********************  Bits definition for DCMI_IER register  *****************/</span>
<a name="l03038"></a>03038 <span class="preprocessor">#define DCMI_IER_FRAME_IE                    ((uint32_t)0x00000001)</span>
<a name="l03039"></a>03039 <span class="preprocessor"></span><span class="preprocessor">#define DCMI_IER_OVF_IE                      ((uint32_t)0x00000002)</span>
<a name="l03040"></a>03040 <span class="preprocessor"></span><span class="preprocessor">#define DCMI_IER_ERR_IE                      ((uint32_t)0x00000004)</span>
<a name="l03041"></a>03041 <span class="preprocessor"></span><span class="preprocessor">#define DCMI_IER_VSYNC_IE                    ((uint32_t)0x00000008)</span>
<a name="l03042"></a>03042 <span class="preprocessor"></span><span class="preprocessor">#define DCMI_IER_LINE_IE                     ((uint32_t)0x00000010)</span>
<a name="l03043"></a>03043 <span class="preprocessor"></span>
<a name="l03044"></a>03044 <span class="comment">/********************  Bits definition for DCMI_MISR register  ****************/</span>
<a name="l03045"></a>03045 <span class="preprocessor">#define DCMI_MISR_FRAME_MIS                  ((uint32_t)0x00000001)</span>
<a name="l03046"></a>03046 <span class="preprocessor"></span><span class="preprocessor">#define DCMI_MISR_OVF_MIS                    ((uint32_t)0x00000002)</span>
<a name="l03047"></a>03047 <span class="preprocessor"></span><span class="preprocessor">#define DCMI_MISR_ERR_MIS                    ((uint32_t)0x00000004)</span>
<a name="l03048"></a>03048 <span class="preprocessor"></span><span class="preprocessor">#define DCMI_MISR_VSYNC_MIS                  ((uint32_t)0x00000008)</span>
<a name="l03049"></a>03049 <span class="preprocessor"></span><span class="preprocessor">#define DCMI_MISR_LINE_MIS                   ((uint32_t)0x00000010)</span>
<a name="l03050"></a>03050 <span class="preprocessor"></span>
<a name="l03051"></a>03051 <span class="comment">/********************  Bits definition for DCMI_ICR register  *****************/</span>
<a name="l03052"></a>03052 <span class="preprocessor">#define DCMI_ICR_FRAME_ISC                   ((uint32_t)0x00000001)</span>
<a name="l03053"></a>03053 <span class="preprocessor"></span><span class="preprocessor">#define DCMI_ICR_OVF_ISC                     ((uint32_t)0x00000002)</span>
<a name="l03054"></a>03054 <span class="preprocessor"></span><span class="preprocessor">#define DCMI_ICR_ERR_ISC                     ((uint32_t)0x00000004)</span>
<a name="l03055"></a>03055 <span class="preprocessor"></span><span class="preprocessor">#define DCMI_ICR_VSYNC_ISC                   ((uint32_t)0x00000008)</span>
<a name="l03056"></a>03056 <span class="preprocessor"></span><span class="preprocessor">#define DCMI_ICR_LINE_ISC                    ((uint32_t)0x00000010)</span>
<a name="l03057"></a>03057 <span class="preprocessor"></span>
<a name="l03058"></a>03058 <span class="comment">/******************************************************************************/</span>
<a name="l03059"></a>03059 <span class="comment">/*                                                                            */</span>
<a name="l03060"></a>03060 <span class="comment">/*                             DMA Controller                                 */</span>
<a name="l03061"></a>03061 <span class="comment">/*                                                                            */</span>
<a name="l03062"></a>03062 <span class="comment">/******************************************************************************/</span>
<a name="l03063"></a>03063 <span class="comment">/********************  Bits definition for DMA_SxCR register  *****************/</span> 
<a name="l03064"></a>03064 <span class="preprocessor">#define DMA_SxCR_CHSEL                       ((uint32_t)0x0E000000)</span>
<a name="l03065"></a>03065 <span class="preprocessor"></span><span class="preprocessor">#define DMA_SxCR_CHSEL_0                     ((uint32_t)0x02000000)</span>
<a name="l03066"></a>03066 <span class="preprocessor"></span><span class="preprocessor">#define DMA_SxCR_CHSEL_1                     ((uint32_t)0x04000000)</span>
<a name="l03067"></a>03067 <span class="preprocessor"></span><span class="preprocessor">#define DMA_SxCR_CHSEL_2                     ((uint32_t)0x08000000) </span>
<a name="l03068"></a>03068 <span class="preprocessor"></span><span class="preprocessor">#define DMA_SxCR_MBURST                      ((uint32_t)0x01800000)</span>
<a name="l03069"></a>03069 <span class="preprocessor"></span><span class="preprocessor">#define DMA_SxCR_MBURST_0                    ((uint32_t)0x00800000)</span>
<a name="l03070"></a>03070 <span class="preprocessor"></span><span class="preprocessor">#define DMA_SxCR_MBURST_1                    ((uint32_t)0x01000000)</span>
<a name="l03071"></a>03071 <span class="preprocessor"></span><span class="preprocessor">#define DMA_SxCR_PBURST                      ((uint32_t)0x00600000)</span>
<a name="l03072"></a>03072 <span class="preprocessor"></span><span class="preprocessor">#define DMA_SxCR_PBURST_0                    ((uint32_t)0x00200000)</span>
<a name="l03073"></a>03073 <span class="preprocessor"></span><span class="preprocessor">#define DMA_SxCR_PBURST_1                    ((uint32_t)0x00400000)</span>
<a name="l03074"></a>03074 <span class="preprocessor"></span><span class="preprocessor">#define DMA_SxCR_ACK                         ((uint32_t)0x00100000)</span>
<a name="l03075"></a>03075 <span class="preprocessor"></span><span class="preprocessor">#define DMA_SxCR_CT                          ((uint32_t)0x00080000)  </span>
<a name="l03076"></a>03076 <span class="preprocessor"></span><span class="preprocessor">#define DMA_SxCR_DBM                         ((uint32_t)0x00040000)</span>
<a name="l03077"></a>03077 <span class="preprocessor"></span><span class="preprocessor">#define DMA_SxCR_PL                          ((uint32_t)0x00030000)</span>
<a name="l03078"></a>03078 <span class="preprocessor"></span><span class="preprocessor">#define DMA_SxCR_PL_0                        ((uint32_t)0x00010000)</span>
<a name="l03079"></a>03079 <span class="preprocessor"></span><span class="preprocessor">#define DMA_SxCR_PL_1                        ((uint32_t)0x00020000)</span>
<a name="l03080"></a>03080 <span class="preprocessor"></span><span class="preprocessor">#define DMA_SxCR_PINCOS                      ((uint32_t)0x00008000)</span>
<a name="l03081"></a>03081 <span class="preprocessor"></span><span class="preprocessor">#define DMA_SxCR_MSIZE                       ((uint32_t)0x00006000)</span>
<a name="l03082"></a>03082 <span class="preprocessor"></span><span class="preprocessor">#define DMA_SxCR_MSIZE_0                     ((uint32_t)0x00002000)</span>
<a name="l03083"></a>03083 <span class="preprocessor"></span><span class="preprocessor">#define DMA_SxCR_MSIZE_1                     ((uint32_t)0x00004000)</span>
<a name="l03084"></a>03084 <span class="preprocessor"></span><span class="preprocessor">#define DMA_SxCR_PSIZE                       ((uint32_t)0x00001800)</span>
<a name="l03085"></a>03085 <span class="preprocessor"></span><span class="preprocessor">#define DMA_SxCR_PSIZE_0                     ((uint32_t)0x00000800)</span>
<a name="l03086"></a>03086 <span class="preprocessor"></span><span class="preprocessor">#define DMA_SxCR_PSIZE_1                     ((uint32_t)0x00001000)</span>
<a name="l03087"></a>03087 <span class="preprocessor"></span><span class="preprocessor">#define DMA_SxCR_MINC                        ((uint32_t)0x00000400)</span>
<a name="l03088"></a>03088 <span class="preprocessor"></span><span class="preprocessor">#define DMA_SxCR_PINC                        ((uint32_t)0x00000200)</span>
<a name="l03089"></a>03089 <span class="preprocessor"></span><span class="preprocessor">#define DMA_SxCR_CIRC                        ((uint32_t)0x00000100)</span>
<a name="l03090"></a>03090 <span class="preprocessor"></span><span class="preprocessor">#define DMA_SxCR_DIR                         ((uint32_t)0x000000C0)</span>
<a name="l03091"></a>03091 <span class="preprocessor"></span><span class="preprocessor">#define DMA_SxCR_DIR_0                       ((uint32_t)0x00000040)</span>
<a name="l03092"></a>03092 <span class="preprocessor"></span><span class="preprocessor">#define DMA_SxCR_DIR_1                       ((uint32_t)0x00000080)</span>
<a name="l03093"></a>03093 <span class="preprocessor"></span><span class="preprocessor">#define DMA_SxCR_PFCTRL                      ((uint32_t)0x00000020)</span>
<a name="l03094"></a>03094 <span class="preprocessor"></span><span class="preprocessor">#define DMA_SxCR_TCIE                        ((uint32_t)0x00000010)</span>
<a name="l03095"></a>03095 <span class="preprocessor"></span><span class="preprocessor">#define DMA_SxCR_HTIE                        ((uint32_t)0x00000008)</span>
<a name="l03096"></a>03096 <span class="preprocessor"></span><span class="preprocessor">#define DMA_SxCR_TEIE                        ((uint32_t)0x00000004)</span>
<a name="l03097"></a>03097 <span class="preprocessor"></span><span class="preprocessor">#define DMA_SxCR_DMEIE                       ((uint32_t)0x00000002)</span>
<a name="l03098"></a>03098 <span class="preprocessor"></span><span class="preprocessor">#define DMA_SxCR_EN                          ((uint32_t)0x00000001)</span>
<a name="l03099"></a>03099 <span class="preprocessor"></span>
<a name="l03100"></a>03100 <span class="comment">/********************  Bits definition for DMA_SxCNDTR register  **************/</span>
<a name="l03101"></a>03101 <span class="preprocessor">#define DMA_SxNDT                            ((uint32_t)0x0000FFFF)</span>
<a name="l03102"></a>03102 <span class="preprocessor"></span><span class="preprocessor">#define DMA_SxNDT_0                          ((uint32_t)0x00000001)</span>
<a name="l03103"></a>03103 <span class="preprocessor"></span><span class="preprocessor">#define DMA_SxNDT_1                          ((uint32_t)0x00000002)</span>
<a name="l03104"></a>03104 <span class="preprocessor"></span><span class="preprocessor">#define DMA_SxNDT_2                          ((uint32_t)0x00000004)</span>
<a name="l03105"></a>03105 <span class="preprocessor"></span><span class="preprocessor">#define DMA_SxNDT_3                          ((uint32_t)0x00000008)</span>
<a name="l03106"></a>03106 <span class="preprocessor"></span><span class="preprocessor">#define DMA_SxNDT_4                          ((uint32_t)0x00000010)</span>
<a name="l03107"></a>03107 <span class="preprocessor"></span><span class="preprocessor">#define DMA_SxNDT_5                          ((uint32_t)0x00000020)</span>
<a name="l03108"></a>03108 <span class="preprocessor"></span><span class="preprocessor">#define DMA_SxNDT_6                          ((uint32_t)0x00000040)</span>
<a name="l03109"></a>03109 <span class="preprocessor"></span><span class="preprocessor">#define DMA_SxNDT_7                          ((uint32_t)0x00000080)</span>
<a name="l03110"></a>03110 <span class="preprocessor"></span><span class="preprocessor">#define DMA_SxNDT_8                          ((uint32_t)0x00000100)</span>
<a name="l03111"></a>03111 <span class="preprocessor"></span><span class="preprocessor">#define DMA_SxNDT_9                          ((uint32_t)0x00000200)</span>
<a name="l03112"></a>03112 <span class="preprocessor"></span><span class="preprocessor">#define DMA_SxNDT_10                         ((uint32_t)0x00000400)</span>
<a name="l03113"></a>03113 <span class="preprocessor"></span><span class="preprocessor">#define DMA_SxNDT_11                         ((uint32_t)0x00000800)</span>
<a name="l03114"></a>03114 <span class="preprocessor"></span><span class="preprocessor">#define DMA_SxNDT_12                         ((uint32_t)0x00001000)</span>
<a name="l03115"></a>03115 <span class="preprocessor"></span><span class="preprocessor">#define DMA_SxNDT_13                         ((uint32_t)0x00002000)</span>
<a name="l03116"></a>03116 <span class="preprocessor"></span><span class="preprocessor">#define DMA_SxNDT_14                         ((uint32_t)0x00004000)</span>
<a name="l03117"></a>03117 <span class="preprocessor"></span><span class="preprocessor">#define DMA_SxNDT_15                         ((uint32_t)0x00008000)</span>
<a name="l03118"></a>03118 <span class="preprocessor"></span>
<a name="l03119"></a>03119 <span class="comment">/********************  Bits definition for DMA_SxFCR register  ****************/</span> 
<a name="l03120"></a>03120 <span class="preprocessor">#define DMA_SxFCR_FEIE                       ((uint32_t)0x00000080)</span>
<a name="l03121"></a>03121 <span class="preprocessor"></span><span class="preprocessor">#define DMA_SxFCR_FS                         ((uint32_t)0x00000038)</span>
<a name="l03122"></a>03122 <span class="preprocessor"></span><span class="preprocessor">#define DMA_SxFCR_FS_0                       ((uint32_t)0x00000008)</span>
<a name="l03123"></a>03123 <span class="preprocessor"></span><span class="preprocessor">#define DMA_SxFCR_FS_1                       ((uint32_t)0x00000010)</span>
<a name="l03124"></a>03124 <span class="preprocessor"></span><span class="preprocessor">#define DMA_SxFCR_FS_2                       ((uint32_t)0x00000020)</span>
<a name="l03125"></a>03125 <span class="preprocessor"></span><span class="preprocessor">#define DMA_SxFCR_DMDIS                      ((uint32_t)0x00000004)</span>
<a name="l03126"></a>03126 <span class="preprocessor"></span><span class="preprocessor">#define DMA_SxFCR_FTH                        ((uint32_t)0x00000003)</span>
<a name="l03127"></a>03127 <span class="preprocessor"></span><span class="preprocessor">#define DMA_SxFCR_FTH_0                      ((uint32_t)0x00000001)</span>
<a name="l03128"></a>03128 <span class="preprocessor"></span><span class="preprocessor">#define DMA_SxFCR_FTH_1                      ((uint32_t)0x00000002)</span>
<a name="l03129"></a>03129 <span class="preprocessor"></span>
<a name="l03130"></a>03130 <span class="comment">/********************  Bits definition for DMA_LISR register  *****************/</span> 
<a name="l03131"></a>03131 <span class="preprocessor">#define DMA_LISR_TCIF3                       ((uint32_t)0x08000000)</span>
<a name="l03132"></a>03132 <span class="preprocessor"></span><span class="preprocessor">#define DMA_LISR_HTIF3                       ((uint32_t)0x04000000)</span>
<a name="l03133"></a>03133 <span class="preprocessor"></span><span class="preprocessor">#define DMA_LISR_TEIF3                       ((uint32_t)0x02000000)</span>
<a name="l03134"></a>03134 <span class="preprocessor"></span><span class="preprocessor">#define DMA_LISR_DMEIF3                      ((uint32_t)0x01000000)</span>
<a name="l03135"></a>03135 <span class="preprocessor"></span><span class="preprocessor">#define DMA_LISR_FEIF3                       ((uint32_t)0x00400000)</span>
<a name="l03136"></a>03136 <span class="preprocessor"></span><span class="preprocessor">#define DMA_LISR_TCIF2                       ((uint32_t)0x00200000)</span>
<a name="l03137"></a>03137 <span class="preprocessor"></span><span class="preprocessor">#define DMA_LISR_HTIF2                       ((uint32_t)0x00100000)</span>
<a name="l03138"></a>03138 <span class="preprocessor"></span><span class="preprocessor">#define DMA_LISR_TEIF2                       ((uint32_t)0x00080000)</span>
<a name="l03139"></a>03139 <span class="preprocessor"></span><span class="preprocessor">#define DMA_LISR_DMEIF2                      ((uint32_t)0x00040000)</span>
<a name="l03140"></a>03140 <span class="preprocessor"></span><span class="preprocessor">#define DMA_LISR_FEIF2                       ((uint32_t)0x00010000)</span>
<a name="l03141"></a>03141 <span class="preprocessor"></span><span class="preprocessor">#define DMA_LISR_TCIF1                       ((uint32_t)0x00000800)</span>
<a name="l03142"></a>03142 <span class="preprocessor"></span><span class="preprocessor">#define DMA_LISR_HTIF1                       ((uint32_t)0x00000400)</span>
<a name="l03143"></a>03143 <span class="preprocessor"></span><span class="preprocessor">#define DMA_LISR_TEIF1                       ((uint32_t)0x00000200)</span>
<a name="l03144"></a>03144 <span class="preprocessor"></span><span class="preprocessor">#define DMA_LISR_DMEIF1                      ((uint32_t)0x00000100)</span>
<a name="l03145"></a>03145 <span class="preprocessor"></span><span class="preprocessor">#define DMA_LISR_FEIF1                       ((uint32_t)0x00000040)</span>
<a name="l03146"></a>03146 <span class="preprocessor"></span><span class="preprocessor">#define DMA_LISR_TCIF0                       ((uint32_t)0x00000020)</span>
<a name="l03147"></a>03147 <span class="preprocessor"></span><span class="preprocessor">#define DMA_LISR_HTIF0                       ((uint32_t)0x00000010)</span>
<a name="l03148"></a>03148 <span class="preprocessor"></span><span class="preprocessor">#define DMA_LISR_TEIF0                       ((uint32_t)0x00000008)</span>
<a name="l03149"></a>03149 <span class="preprocessor"></span><span class="preprocessor">#define DMA_LISR_DMEIF0                      ((uint32_t)0x00000004)</span>
<a name="l03150"></a>03150 <span class="preprocessor"></span><span class="preprocessor">#define DMA_LISR_FEIF0                       ((uint32_t)0x00000001)</span>
<a name="l03151"></a>03151 <span class="preprocessor"></span>
<a name="l03152"></a>03152 <span class="comment">/********************  Bits definition for DMA_HISR register  *****************/</span> 
<a name="l03153"></a>03153 <span class="preprocessor">#define DMA_HISR_TCIF7                       ((uint32_t)0x08000000)</span>
<a name="l03154"></a>03154 <span class="preprocessor"></span><span class="preprocessor">#define DMA_HISR_HTIF7                       ((uint32_t)0x04000000)</span>
<a name="l03155"></a>03155 <span class="preprocessor"></span><span class="preprocessor">#define DMA_HISR_TEIF7                       ((uint32_t)0x02000000)</span>
<a name="l03156"></a>03156 <span class="preprocessor"></span><span class="preprocessor">#define DMA_HISR_DMEIF7                      ((uint32_t)0x01000000)</span>
<a name="l03157"></a>03157 <span class="preprocessor"></span><span class="preprocessor">#define DMA_HISR_FEIF7                       ((uint32_t)0x00400000)</span>
<a name="l03158"></a>03158 <span class="preprocessor"></span><span class="preprocessor">#define DMA_HISR_TCIF6                       ((uint32_t)0x00200000)</span>
<a name="l03159"></a>03159 <span class="preprocessor"></span><span class="preprocessor">#define DMA_HISR_HTIF6                       ((uint32_t)0x00100000)</span>
<a name="l03160"></a>03160 <span class="preprocessor"></span><span class="preprocessor">#define DMA_HISR_TEIF6                       ((uint32_t)0x00080000)</span>
<a name="l03161"></a>03161 <span class="preprocessor"></span><span class="preprocessor">#define DMA_HISR_DMEIF6                      ((uint32_t)0x00040000)</span>
<a name="l03162"></a>03162 <span class="preprocessor"></span><span class="preprocessor">#define DMA_HISR_FEIF6                       ((uint32_t)0x00010000)</span>
<a name="l03163"></a>03163 <span class="preprocessor"></span><span class="preprocessor">#define DMA_HISR_TCIF5                       ((uint32_t)0x00000800)</span>
<a name="l03164"></a>03164 <span class="preprocessor"></span><span class="preprocessor">#define DMA_HISR_HTIF5                       ((uint32_t)0x00000400)</span>
<a name="l03165"></a>03165 <span class="preprocessor"></span><span class="preprocessor">#define DMA_HISR_TEIF5                       ((uint32_t)0x00000200)</span>
<a name="l03166"></a>03166 <span class="preprocessor"></span><span class="preprocessor">#define DMA_HISR_DMEIF5                      ((uint32_t)0x00000100)</span>
<a name="l03167"></a>03167 <span class="preprocessor"></span><span class="preprocessor">#define DMA_HISR_FEIF5                       ((uint32_t)0x00000040)</span>
<a name="l03168"></a>03168 <span class="preprocessor"></span><span class="preprocessor">#define DMA_HISR_TCIF4                       ((uint32_t)0x00000020)</span>
<a name="l03169"></a>03169 <span class="preprocessor"></span><span class="preprocessor">#define DMA_HISR_HTIF4                       ((uint32_t)0x00000010)</span>
<a name="l03170"></a>03170 <span class="preprocessor"></span><span class="preprocessor">#define DMA_HISR_TEIF4                       ((uint32_t)0x00000008)</span>
<a name="l03171"></a>03171 <span class="preprocessor"></span><span class="preprocessor">#define DMA_HISR_DMEIF4                      ((uint32_t)0x00000004)</span>
<a name="l03172"></a>03172 <span class="preprocessor"></span><span class="preprocessor">#define DMA_HISR_FEIF4                       ((uint32_t)0x00000001)</span>
<a name="l03173"></a>03173 <span class="preprocessor"></span>
<a name="l03174"></a>03174 <span class="comment">/********************  Bits definition for DMA_LIFCR register  ****************/</span> 
<a name="l03175"></a>03175 <span class="preprocessor">#define DMA_LIFCR_CTCIF3                     ((uint32_t)0x08000000)</span>
<a name="l03176"></a>03176 <span class="preprocessor"></span><span class="preprocessor">#define DMA_LIFCR_CHTIF3                     ((uint32_t)0x04000000)</span>
<a name="l03177"></a>03177 <span class="preprocessor"></span><span class="preprocessor">#define DMA_LIFCR_CTEIF3                     ((uint32_t)0x02000000)</span>
<a name="l03178"></a>03178 <span class="preprocessor"></span><span class="preprocessor">#define DMA_LIFCR_CDMEIF3                    ((uint32_t)0x01000000)</span>
<a name="l03179"></a>03179 <span class="preprocessor"></span><span class="preprocessor">#define DMA_LIFCR_CFEIF3                     ((uint32_t)0x00400000)</span>
<a name="l03180"></a>03180 <span class="preprocessor"></span><span class="preprocessor">#define DMA_LIFCR_CTCIF2                     ((uint32_t)0x00200000)</span>
<a name="l03181"></a>03181 <span class="preprocessor"></span><span class="preprocessor">#define DMA_LIFCR_CHTIF2                     ((uint32_t)0x00100000)</span>
<a name="l03182"></a>03182 <span class="preprocessor"></span><span class="preprocessor">#define DMA_LIFCR_CTEIF2                     ((uint32_t)0x00080000)</span>
<a name="l03183"></a>03183 <span class="preprocessor"></span><span class="preprocessor">#define DMA_LIFCR_CDMEIF2                    ((uint32_t)0x00040000)</span>
<a name="l03184"></a>03184 <span class="preprocessor"></span><span class="preprocessor">#define DMA_LIFCR_CFEIF2                     ((uint32_t)0x00010000)</span>
<a name="l03185"></a>03185 <span class="preprocessor"></span><span class="preprocessor">#define DMA_LIFCR_CTCIF1                     ((uint32_t)0x00000800)</span>
<a name="l03186"></a>03186 <span class="preprocessor"></span><span class="preprocessor">#define DMA_LIFCR_CHTIF1                     ((uint32_t)0x00000400)</span>
<a name="l03187"></a>03187 <span class="preprocessor"></span><span class="preprocessor">#define DMA_LIFCR_CTEIF1                     ((uint32_t)0x00000200)</span>
<a name="l03188"></a>03188 <span class="preprocessor"></span><span class="preprocessor">#define DMA_LIFCR_CDMEIF1                    ((uint32_t)0x00000100)</span>
<a name="l03189"></a>03189 <span class="preprocessor"></span><span class="preprocessor">#define DMA_LIFCR_CFEIF1                     ((uint32_t)0x00000040)</span>
<a name="l03190"></a>03190 <span class="preprocessor"></span><span class="preprocessor">#define DMA_LIFCR_CTCIF0                     ((uint32_t)0x00000020)</span>
<a name="l03191"></a>03191 <span class="preprocessor"></span><span class="preprocessor">#define DMA_LIFCR_CHTIF0                     ((uint32_t)0x00000010)</span>
<a name="l03192"></a>03192 <span class="preprocessor"></span><span class="preprocessor">#define DMA_LIFCR_CTEIF0                     ((uint32_t)0x00000008)</span>
<a name="l03193"></a>03193 <span class="preprocessor"></span><span class="preprocessor">#define DMA_LIFCR_CDMEIF0                    ((uint32_t)0x00000004)</span>
<a name="l03194"></a>03194 <span class="preprocessor"></span><span class="preprocessor">#define DMA_LIFCR_CFEIF0                     ((uint32_t)0x00000001)</span>
<a name="l03195"></a>03195 <span class="preprocessor"></span>
<a name="l03196"></a>03196 <span class="comment">/********************  Bits definition for DMA_HIFCR  register  ****************/</span> 
<a name="l03197"></a>03197 <span class="preprocessor">#define DMA_HIFCR_CTCIF7                     ((uint32_t)0x08000000)</span>
<a name="l03198"></a>03198 <span class="preprocessor"></span><span class="preprocessor">#define DMA_HIFCR_CHTIF7                     ((uint32_t)0x04000000)</span>
<a name="l03199"></a>03199 <span class="preprocessor"></span><span class="preprocessor">#define DMA_HIFCR_CTEIF7                     ((uint32_t)0x02000000)</span>
<a name="l03200"></a>03200 <span class="preprocessor"></span><span class="preprocessor">#define DMA_HIFCR_CDMEIF7                    ((uint32_t)0x01000000)</span>
<a name="l03201"></a>03201 <span class="preprocessor"></span><span class="preprocessor">#define DMA_HIFCR_CFEIF7                     ((uint32_t)0x00400000)</span>
<a name="l03202"></a>03202 <span class="preprocessor"></span><span class="preprocessor">#define DMA_HIFCR_CTCIF6                     ((uint32_t)0x00200000)</span>
<a name="l03203"></a>03203 <span class="preprocessor"></span><span class="preprocessor">#define DMA_HIFCR_CHTIF6                     ((uint32_t)0x00100000)</span>
<a name="l03204"></a>03204 <span class="preprocessor"></span><span class="preprocessor">#define DMA_HIFCR_CTEIF6                     ((uint32_t)0x00080000)</span>
<a name="l03205"></a>03205 <span class="preprocessor"></span><span class="preprocessor">#define DMA_HIFCR_CDMEIF6                    ((uint32_t)0x00040000)</span>
<a name="l03206"></a>03206 <span class="preprocessor"></span><span class="preprocessor">#define DMA_HIFCR_CFEIF6                     ((uint32_t)0x00010000)</span>
<a name="l03207"></a>03207 <span class="preprocessor"></span><span class="preprocessor">#define DMA_HIFCR_CTCIF5                     ((uint32_t)0x00000800)</span>
<a name="l03208"></a>03208 <span class="preprocessor"></span><span class="preprocessor">#define DMA_HIFCR_CHTIF5                     ((uint32_t)0x00000400)</span>
<a name="l03209"></a>03209 <span class="preprocessor"></span><span class="preprocessor">#define DMA_HIFCR_CTEIF5                     ((uint32_t)0x00000200)</span>
<a name="l03210"></a>03210 <span class="preprocessor"></span><span class="preprocessor">#define DMA_HIFCR_CDMEIF5                    ((uint32_t)0x00000100)</span>
<a name="l03211"></a>03211 <span class="preprocessor"></span><span class="preprocessor">#define DMA_HIFCR_CFEIF5                     ((uint32_t)0x00000040)</span>
<a name="l03212"></a>03212 <span class="preprocessor"></span><span class="preprocessor">#define DMA_HIFCR_CTCIF4                     ((uint32_t)0x00000020)</span>
<a name="l03213"></a>03213 <span class="preprocessor"></span><span class="preprocessor">#define DMA_HIFCR_CHTIF4                     ((uint32_t)0x00000010)</span>
<a name="l03214"></a>03214 <span class="preprocessor"></span><span class="preprocessor">#define DMA_HIFCR_CTEIF4                     ((uint32_t)0x00000008)</span>
<a name="l03215"></a>03215 <span class="preprocessor"></span><span class="preprocessor">#define DMA_HIFCR_CDMEIF4                    ((uint32_t)0x00000004)</span>
<a name="l03216"></a>03216 <span class="preprocessor"></span><span class="preprocessor">#define DMA_HIFCR_CFEIF4                     ((uint32_t)0x00000001)</span>
<a name="l03217"></a>03217 <span class="preprocessor"></span>
<a name="l03218"></a>03218 <span class="comment">/******************************************************************************/</span>
<a name="l03219"></a>03219 <span class="comment">/*                                                                            */</span>
<a name="l03220"></a>03220 <span class="comment">/*                    External Interrupt/Event Controller                     */</span>
<a name="l03221"></a>03221 <span class="comment">/*                                                                            */</span>
<a name="l03222"></a>03222 <span class="comment">/******************************************************************************/</span>
<a name="l03223"></a>03223 <span class="comment">/*******************  Bit definition for EXTI_IMR register  *******************/</span>
<a name="l03224"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gad03b2ba6cde99065627fccabd54ac097">03224</a> <span class="preprocessor">#define  EXTI_IMR_MR0                        ((uint32_t)0x00000001)        </span>
<a name="l03225"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaaaf3f9a86c620149893db38c83f8ba58">03225</a> <span class="preprocessor">#define  EXTI_IMR_MR1                        ((uint32_t)0x00000002)        </span>
<a name="l03226"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga71604d1c29973c5e2bf69c8e94e89f67">03226</a> <span class="preprocessor">#define  EXTI_IMR_MR2                        ((uint32_t)0x00000004)        </span>
<a name="l03227"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga5edd42f9b2129c18cfa3c3598dcd1134">03227</a> <span class="preprocessor">#define  EXTI_IMR_MR3                        ((uint32_t)0x00000008)        </span>
<a name="l03228"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga23e920ad334439cd2ad4d683054914e3">03228</a> <span class="preprocessor">#define  EXTI_IMR_MR4                        ((uint32_t)0x00000010)        </span>
<a name="l03229"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga7cd3c5a2e4c4cb9b81e8965fcbf1c3a5">03229</a> <span class="preprocessor">#define  EXTI_IMR_MR5                        ((uint32_t)0x00000020)        </span>
<a name="l03230"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga5533c8ec796e3bbc9dc4474376056e06">03230</a> <span class="preprocessor">#define  EXTI_IMR_MR6                        ((uint32_t)0x00000040)        </span>
<a name="l03231"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gab620165d3fea1c564fcf1016805a1a8e">03231</a> <span class="preprocessor">#define  EXTI_IMR_MR7                        ((uint32_t)0x00000080)        </span>
<a name="l03232"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga88e8b274e4398fdcb1c68da2b6320d5b">03232</a> <span class="preprocessor">#define  EXTI_IMR_MR8                        ((uint32_t)0x00000100)        </span>
<a name="l03233"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaf4d177dcf33bb9a34f8590ec509746e8">03233</a> <span class="preprocessor">#define  EXTI_IMR_MR9                        ((uint32_t)0x00000200)        </span>
<a name="l03234"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga5fd7db9a1ce82c152ca7bc6fddf31366">03234</a> <span class="preprocessor">#define  EXTI_IMR_MR10                       ((uint32_t)0x00000400)        </span>
<a name="l03235"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga68cfe8fe938fcb0fc6925bf493ccfaa7">03235</a> <span class="preprocessor">#define  EXTI_IMR_MR11                       ((uint32_t)0x00000800)        </span>
<a name="l03236"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gad21caf923d2083fb106852493667c16e">03236</a> <span class="preprocessor">#define  EXTI_IMR_MR12                       ((uint32_t)0x00001000)        </span>
<a name="l03237"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga5e1938a063c48d7d6504cb32f7965c0e">03237</a> <span class="preprocessor">#define  EXTI_IMR_MR13                       ((uint32_t)0x00002000)        </span>
<a name="l03238"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gab8827cee06670f256bc8f6301bea9cab">03238</a> <span class="preprocessor">#define  EXTI_IMR_MR14                       ((uint32_t)0x00004000)        </span>
<a name="l03239"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga88d9990be7f8f9e530a9f930a365fa44">03239</a> <span class="preprocessor">#define  EXTI_IMR_MR15                       ((uint32_t)0x00008000)        </span>
<a name="l03240"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga7419f78ed9044bdd237b452ef49e1b7f">03240</a> <span class="preprocessor">#define  EXTI_IMR_MR16                       ((uint32_t)0x00010000)        </span>
<a name="l03241"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga4489fa85d1552b8f40faed93483a5d35">03241</a> <span class="preprocessor">#define  EXTI_IMR_MR17                       ((uint32_t)0x00020000)        </span>
<a name="l03242"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga05e16f2cda40cca58a45458cc44d510f">03242</a> <span class="preprocessor">#define  EXTI_IMR_MR18                       ((uint32_t)0x00040000)        </span>
<a name="l03243"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gad47f7a023cbba165dfb95845d3c8c55c">03243</a> <span class="preprocessor">#define  EXTI_IMR_MR19                       ((uint32_t)0x00080000)        </span>
<a name="l03245"></a>03245 <span class="preprocessor"></span><span class="comment">/*******************  Bit definition for EXTI_EMR register  *******************/</span>
<a name="l03246"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga515c0dc6d2472e06a89e4bb19725e8f3">03246</a> <span class="preprocessor">#define  EXTI_EMR_MR0                        ((uint32_t)0x00000001)        </span>
<a name="l03247"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga6d88e7c10e5985fa425ea7ab4fe4c3e5">03247</a> <span class="preprocessor">#define  EXTI_EMR_MR1                        ((uint32_t)0x00000002)        </span>
<a name="l03248"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga460d5d4c0b53bcc04d5804e1204ded21">03248</a> <span class="preprocessor">#define  EXTI_EMR_MR2                        ((uint32_t)0x00000004)        </span>
<a name="l03249"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga73944983ce5a6bde9dc172b4f483898c">03249</a> <span class="preprocessor">#define  EXTI_EMR_MR3                        ((uint32_t)0x00000008)        </span>
<a name="l03250"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gab80f809ead83e747677a31c80c6aae03">03250</a> <span class="preprocessor">#define  EXTI_EMR_MR4                        ((uint32_t)0x00000010)        </span>
<a name="l03251"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga65976f75b703f740dea3562ba3b8db59">03251</a> <span class="preprocessor">#define  EXTI_EMR_MR5                        ((uint32_t)0x00000020)        </span>
<a name="l03252"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaea480bd932cd1fa0904f5eb1caee9a12">03252</a> <span class="preprocessor">#define  EXTI_EMR_MR6                        ((uint32_t)0x00000040)        </span>
<a name="l03253"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gadbb27ff8664928994ef96f87052d14be">03253</a> <span class="preprocessor">#define  EXTI_EMR_MR7                        ((uint32_t)0x00000080)        </span>
<a name="l03254"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga4ed4b371da871ffd0cc12ee00147282f">03254</a> <span class="preprocessor">#define  EXTI_EMR_MR8                        ((uint32_t)0x00000100)        </span>
<a name="l03255"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga109af342179fff1fccfdde582834867a">03255</a> <span class="preprocessor">#define  EXTI_EMR_MR9                        ((uint32_t)0x00000200)        </span>
<a name="l03256"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaf342d34ed1b8e4aa916bf49e30c2a234">03256</a> <span class="preprocessor">#define  EXTI_EMR_MR10                       ((uint32_t)0x00000400)        </span>
<a name="l03257"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga9ec516af1de770c82c3c9c458cbc0172">03257</a> <span class="preprocessor">#define  EXTI_EMR_MR11                       ((uint32_t)0x00000800)        </span>
<a name="l03258"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga15732553e5b0de9f58180a0b024d4cad">03258</a> <span class="preprocessor">#define  EXTI_EMR_MR12                       ((uint32_t)0x00001000)        </span>
<a name="l03259"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga9fd2ec6472e46869956acb28f5e1b55f">03259</a> <span class="preprocessor">#define  EXTI_EMR_MR13                       ((uint32_t)0x00002000)        </span>
<a name="l03260"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaecf5890ea71eea034ec1cd9e96284f89">03260</a> <span class="preprocessor">#define  EXTI_EMR_MR14                       ((uint32_t)0x00004000)        </span>
<a name="l03261"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga7a7bacc32351a36aefcd5614abc76ae3">03261</a> <span class="preprocessor">#define  EXTI_EMR_MR15                       ((uint32_t)0x00008000)        </span>
<a name="l03262"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga34b1a6934265da759bc061f73d5d1374">03262</a> <span class="preprocessor">#define  EXTI_EMR_MR16                       ((uint32_t)0x00010000)        </span>
<a name="l03263"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga6a30aa20cf475eecf7e15171e83035e4">03263</a> <span class="preprocessor">#define  EXTI_EMR_MR17                       ((uint32_t)0x00020000)        </span>
<a name="l03264"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga25eee729b57b4c78a0613c184fc539e5">03264</a> <span class="preprocessor">#define  EXTI_EMR_MR18                       ((uint32_t)0x00040000)        </span>
<a name="l03265"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaaeababa85e5ebe6aa93d011d83fd7994">03265</a> <span class="preprocessor">#define  EXTI_EMR_MR19                       ((uint32_t)0x00080000)        </span>
<a name="l03267"></a>03267 <span class="preprocessor"></span><span class="comment">/******************  Bit definition for EXTI_RTSR register  *******************/</span>
<a name="l03268"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gadb1823a87cd797a6066681a3256cecc6">03268</a> <span class="preprocessor">#define  EXTI_RTSR_TR0                       ((uint32_t)0x00000001)        </span>
<a name="l03269"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga1c42cc3763c52d1061b32219fc441566">03269</a> <span class="preprocessor">#define  EXTI_RTSR_TR1                       ((uint32_t)0x00000002)        </span>
<a name="l03270"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga1c073b519f09b130e4ab4039823e290c">03270</a> <span class="preprocessor">#define  EXTI_RTSR_TR2                       ((uint32_t)0x00000004)        </span>
<a name="l03271"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga090f295579a774c215585a55e5066b11">03271</a> <span class="preprocessor">#define  EXTI_RTSR_TR3                       ((uint32_t)0x00000008)        </span>
<a name="l03272"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gabce4722e99e3f44d40bfb6afb63444cc">03272</a> <span class="preprocessor">#define  EXTI_RTSR_TR4                       ((uint32_t)0x00000010)        </span>
<a name="l03273"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gac57b970ebc88f7bb015119ece9dd32de">03273</a> <span class="preprocessor">#define  EXTI_RTSR_TR5                       ((uint32_t)0x00000020)        </span>
<a name="l03274"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaccc2212ce653d34cf48446ae0a68bed6">03274</a> <span class="preprocessor">#define  EXTI_RTSR_TR6                       ((uint32_t)0x00000040)        </span>
<a name="l03275"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gad380a0bc59524f4a0846a0b91d3c65c1">03275</a> <span class="preprocessor">#define  EXTI_RTSR_TR7                       ((uint32_t)0x00000080)        </span>
<a name="l03276"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga26cd6a5115b0bbe113f39545bff1ee39">03276</a> <span class="preprocessor">#define  EXTI_RTSR_TR8                       ((uint32_t)0x00000100)        </span>
<a name="l03277"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga3127246b2db3571b00c6af2453941d17">03277</a> <span class="preprocessor">#define  EXTI_RTSR_TR9                       ((uint32_t)0x00000200)        </span>
<a name="l03278"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaa29df7ddbd067889992eb60ecddce0e4">03278</a> <span class="preprocessor">#define  EXTI_RTSR_TR10                      ((uint32_t)0x00000400)        </span>
<a name="l03279"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga8cf7a92cdb61b3f8cf6eec9513317ab7">03279</a> <span class="preprocessor">#define  EXTI_RTSR_TR11                      ((uint32_t)0x00000800)        </span>
<a name="l03280"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga0423be12bfb13f34eec9656d6d274e04">03280</a> <span class="preprocessor">#define  EXTI_RTSR_TR12                      ((uint32_t)0x00001000)        </span>
<a name="l03281"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga5d5ef451fd76dc0fa9c76d7c520d8f12">03281</a> <span class="preprocessor">#define  EXTI_RTSR_TR13                      ((uint32_t)0x00002000)        </span>
<a name="l03282"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga95b0d883fa0fbc49105bda5596463cda">03282</a> <span class="preprocessor">#define  EXTI_RTSR_TR14                      ((uint32_t)0x00004000)        </span>
<a name="l03283"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga4fe54b09102a18676829c0bafb0aead2">03283</a> <span class="preprocessor">#define  EXTI_RTSR_TR15                      ((uint32_t)0x00008000)        </span>
<a name="l03284"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gae8e4fb52990f0fa3fb9bed5b74f1a589">03284</a> <span class="preprocessor">#define  EXTI_RTSR_TR16                      ((uint32_t)0x00010000)        </span>
<a name="l03285"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gad0a8fcb63516a4ed0d91b556f696f806">03285</a> <span class="preprocessor">#define  EXTI_RTSR_TR17                      ((uint32_t)0x00020000)        </span>
<a name="l03286"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaca4223b8c4bc8726ac96ec64837f7b62">03286</a> <span class="preprocessor">#define  EXTI_RTSR_TR18                      ((uint32_t)0x00040000)        </span>
<a name="l03287"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga40a722b0c36e832f619b2136f1510b3e">03287</a> <span class="preprocessor">#define  EXTI_RTSR_TR19                      ((uint32_t)0x00080000)        </span>
<a name="l03289"></a>03289 <span class="preprocessor"></span><span class="comment">/******************  Bit definition for EXTI_FTSR register  *******************/</span>
<a name="l03290"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gacfb6fa5ae3fcaf08aec6d86c3bfefa4c">03290</a> <span class="preprocessor">#define  EXTI_FTSR_TR0                       ((uint32_t)0x00000001)        </span>
<a name="l03291"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gac287be3bd3bad84aed48603dbe8bd4ed">03291</a> <span class="preprocessor">#define  EXTI_FTSR_TR1                       ((uint32_t)0x00000002)        </span>
<a name="l03292"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga9c4503803cbe1933cd35519cfc809041">03292</a> <span class="preprocessor">#define  EXTI_FTSR_TR2                       ((uint32_t)0x00000004)        </span>
<a name="l03293"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga23593d2b8a9ec0147bab28765af30e1f">03293</a> <span class="preprocessor">#define  EXTI_FTSR_TR3                       ((uint32_t)0x00000008)        </span>
<a name="l03294"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaa77211bfa8f4d77cf373296954dad6b2">03294</a> <span class="preprocessor">#define  EXTI_FTSR_TR4                       ((uint32_t)0x00000010)        </span>
<a name="l03295"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga903f9b080c5971dd5d7935e5b87886e2">03295</a> <span class="preprocessor">#define  EXTI_FTSR_TR5                       ((uint32_t)0x00000020)        </span>
<a name="l03296"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gae8527cce22f69e02a08ed67a67f8e5ca">03296</a> <span class="preprocessor">#define  EXTI_FTSR_TR6                       ((uint32_t)0x00000040)        </span>
<a name="l03297"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaf408315e497b902922a9bf40a4c6f567">03297</a> <span class="preprocessor">#define  EXTI_FTSR_TR7                       ((uint32_t)0x00000080)        </span>
<a name="l03298"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga00f1bded4d121e21116627b8e80784fc">03298</a> <span class="preprocessor">#define  EXTI_FTSR_TR8                       ((uint32_t)0x00000100)        </span>
<a name="l03299"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga89f0c4de2b6acb75302d206b697f83ef">03299</a> <span class="preprocessor">#define  EXTI_FTSR_TR9                       ((uint32_t)0x00000200)        </span>
<a name="l03300"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gac9a2b80699a213f0d2b03658f21ad643">03300</a> <span class="preprocessor">#define  EXTI_FTSR_TR10                      ((uint32_t)0x00000400)        </span>
<a name="l03301"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga6c74d4d520406a14c517784cdd5fc6ef">03301</a> <span class="preprocessor">#define  EXTI_FTSR_TR11                      ((uint32_t)0x00000800)        </span>
<a name="l03302"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga3992511ec1785bdf107873b139d74245">03302</a> <span class="preprocessor">#define  EXTI_FTSR_TR12                      ((uint32_t)0x00001000)        </span>
<a name="l03303"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga0714519a1edcba4695f92f1bba70e825">03303</a> <span class="preprocessor">#define  EXTI_FTSR_TR13                      ((uint32_t)0x00002000)        </span>
<a name="l03304"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga5b92577e64a95ef2069f1a56176d35ff">03304</a> <span class="preprocessor">#define  EXTI_FTSR_TR14                      ((uint32_t)0x00004000)        </span>
<a name="l03305"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga2a6cc515f13ffe1a3620d06fa08addc7">03305</a> <span class="preprocessor">#define  EXTI_FTSR_TR15                      ((uint32_t)0x00008000)        </span>
<a name="l03306"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaa1b4b850094ccc48790a1e4616ceebd2">03306</a> <span class="preprocessor">#define  EXTI_FTSR_TR16                      ((uint32_t)0x00010000)        </span>
<a name="l03307"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga009e618c9563b3a8dcaec493006115c7">03307</a> <span class="preprocessor">#define  EXTI_FTSR_TR17                      ((uint32_t)0x00020000)        </span>
<a name="l03308"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga405285cdc474ee20085b17ef1f61517e">03308</a> <span class="preprocessor">#define  EXTI_FTSR_TR18                      ((uint32_t)0x00040000)        </span>
<a name="l03309"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga1277527e2fa727fdec2dcc7a300ea1af">03309</a> <span class="preprocessor">#define  EXTI_FTSR_TR19                      ((uint32_t)0x00080000)        </span>
<a name="l03311"></a>03311 <span class="preprocessor"></span><span class="comment">/******************  Bit definition for EXTI_SWIER register  ******************/</span>
<a name="l03312"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaa6df16d2e8010a2897888a4acf19cee3">03312</a> <span class="preprocessor">#define  EXTI_SWIER_SWIER0                   ((uint32_t)0x00000001)        </span>
<a name="l03313"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaeb0c3fa5a03204d743ae92ff925421ae">03313</a> <span class="preprocessor">#define  EXTI_SWIER_SWIER1                   ((uint32_t)0x00000002)        </span>
<a name="l03314"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga6bea1dbaf71e830dd357135524166f4c">03314</a> <span class="preprocessor">#define  EXTI_SWIER_SWIER2                   ((uint32_t)0x00000004)        </span>
<a name="l03315"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga37395ac6729647ab5ee1fa4ca086c08a">03315</a> <span class="preprocessor">#define  EXTI_SWIER_SWIER3                   ((uint32_t)0x00000008)        </span>
<a name="l03316"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gab051808f7a1ed9aaf43a3df90fc6a575">03316</a> <span class="preprocessor">#define  EXTI_SWIER_SWIER4                   ((uint32_t)0x00000010)        </span>
<a name="l03317"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaa5b4ace22acacac13ce106b2063a3977">03317</a> <span class="preprocessor">#define  EXTI_SWIER_SWIER5                   ((uint32_t)0x00000020)        </span>
<a name="l03318"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gad8ad0142288597993852e4cf350f61ed">03318</a> <span class="preprocessor">#define  EXTI_SWIER_SWIER6                   ((uint32_t)0x00000040)        </span>
<a name="l03319"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gabdf8eab3e32cc03ca71f519a9111e28f">03319</a> <span class="preprocessor">#define  EXTI_SWIER_SWIER7                   ((uint32_t)0x00000080)        </span>
<a name="l03320"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga5e83a373926804449d500b115e9090ce">03320</a> <span class="preprocessor">#define  EXTI_SWIER_SWIER8                   ((uint32_t)0x00000100)        </span>
<a name="l03321"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gab102aa929ffe463ffe9f2db651704a61">03321</a> <span class="preprocessor">#define  EXTI_SWIER_SWIER9                   ((uint32_t)0x00000200)        </span>
<a name="l03322"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gae9d8691936b6cd80ff8e18c0bfe271d7">03322</a> <span class="preprocessor">#define  EXTI_SWIER_SWIER10                  ((uint32_t)0x00000400)        </span>
<a name="l03323"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga7ab9fea9935608ec8ee7fb1e1ae049e7">03323</a> <span class="preprocessor">#define  EXTI_SWIER_SWIER11                  ((uint32_t)0x00000800)        </span>
<a name="l03324"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga5d67869db50c848f57633ebf00566539">03324</a> <span class="preprocessor">#define  EXTI_SWIER_SWIER12                  ((uint32_t)0x00001000)        </span>
<a name="l03325"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga930a1d03fe3c32bd65a336ccee418826">03325</a> <span class="preprocessor">#define  EXTI_SWIER_SWIER13                  ((uint32_t)0x00002000)        </span>
<a name="l03326"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gad5d645db667cd63d1a9b91963c543a4b">03326</a> <span class="preprocessor">#define  EXTI_SWIER_SWIER14                  ((uint32_t)0x00004000)        </span>
<a name="l03327"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga0b9e64d5a1779371fa4678713ab18e08">03327</a> <span class="preprocessor">#define  EXTI_SWIER_SWIER15                  ((uint32_t)0x00008000)        </span>
<a name="l03328"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga55b528743b11f4ab93ae97ee2e639b5b">03328</a> <span class="preprocessor">#define  EXTI_SWIER_SWIER16                  ((uint32_t)0x00010000)        </span>
<a name="l03329"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga0da944251419887af3a87c86080fb455">03329</a> <span class="preprocessor">#define  EXTI_SWIER_SWIER17                  ((uint32_t)0x00020000)        </span>
<a name="l03330"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gab07aefbb7a8a18c9338b49d3b10ff068">03330</a> <span class="preprocessor">#define  EXTI_SWIER_SWIER18                  ((uint32_t)0x00040000)        </span>
<a name="l03331"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaab7c48ac5522385cdb1d7882985f909b">03331</a> <span class="preprocessor">#define  EXTI_SWIER_SWIER19                  ((uint32_t)0x00080000)        </span>
<a name="l03333"></a>03333 <span class="preprocessor"></span><span class="comment">/*******************  Bit definition for EXTI_PR register  ********************/</span>
<a name="l03334"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga6da1c8a465606de1f90a74d369fbf25a">03334</a> <span class="preprocessor">#define  EXTI_PR_PR0                         ((uint32_t)0x00000001)        </span>
<a name="l03335"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga4b9b5f97edeccf442998a65b19e77f25">03335</a> <span class="preprocessor">#define  EXTI_PR_PR1                         ((uint32_t)0x00000002)        </span>
<a name="l03336"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga085d2105381752a0aadc9be5a93ea665">03336</a> <span class="preprocessor">#define  EXTI_PR_PR2                         ((uint32_t)0x00000004)        </span>
<a name="l03337"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga064dab3e0d5689b92125713100555ce0">03337</a> <span class="preprocessor">#define  EXTI_PR_PR3                         ((uint32_t)0x00000008)        </span>
<a name="l03338"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga14f73b3693b3353a006d360cb8fd2ddc">03338</a> <span class="preprocessor">#define  EXTI_PR_PR4                         ((uint32_t)0x00000010)        </span>
<a name="l03339"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga319e167fa6e112061997d9a8d79f02f8">03339</a> <span class="preprocessor">#define  EXTI_PR_PR5                         ((uint32_t)0x00000020)        </span>
<a name="l03340"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaf6f47cd1f602692258985784ed5e8e76">03340</a> <span class="preprocessor">#define  EXTI_PR_PR6                         ((uint32_t)0x00000040)        </span>
<a name="l03341"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaa17ea7e3fb89e98fd6a232f453fcff9e">03341</a> <span class="preprocessor">#define  EXTI_PR_PR7                         ((uint32_t)0x00000080)        </span>
<a name="l03342"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaa82e0dcb4961a32a9b7ebdf30493156d">03342</a> <span class="preprocessor">#define  EXTI_PR_PR8                         ((uint32_t)0x00000100)        </span>
<a name="l03343"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga2fcc64f03d79af531febc077f45c48eb">03343</a> <span class="preprocessor">#define  EXTI_PR_PR9                         ((uint32_t)0x00000200)        </span>
<a name="l03344"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga1ef8e9c691b95763007ed228e98fa108">03344</a> <span class="preprocessor">#define  EXTI_PR_PR10                        ((uint32_t)0x00000400)        </span>
<a name="l03345"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga144f1a41abb7b87a1619c15ba5fb548b">03345</a> <span class="preprocessor">#define  EXTI_PR_PR11                        ((uint32_t)0x00000800)        </span>
<a name="l03346"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gae1a68025056b8c84bb13635af5e2a07c">03346</a> <span class="preprocessor">#define  EXTI_PR_PR12                        ((uint32_t)0x00001000)        </span>
<a name="l03347"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga3471c79d5b19813785387504a1a5f0c4">03347</a> <span class="preprocessor">#define  EXTI_PR_PR13                        ((uint32_t)0x00002000)        </span>
<a name="l03348"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gae5396ec2dbbee9d7585224fa12273598">03348</a> <span class="preprocessor">#define  EXTI_PR_PR14                        ((uint32_t)0x00004000)        </span>
<a name="l03349"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga149f9d9d6c1aab867734b59db1117c41">03349</a> <span class="preprocessor">#define  EXTI_PR_PR15                        ((uint32_t)0x00008000)        </span>
<a name="l03350"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaa47e5b07d5a407198e09f05262f18bba">03350</a> <span class="preprocessor">#define  EXTI_PR_PR16                        ((uint32_t)0x00010000)        </span>
<a name="l03351"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gadbc7d82eb61e2adf0a955ef0cc97690f">03351</a> <span class="preprocessor">#define  EXTI_PR_PR17                        ((uint32_t)0x00020000)        </span>
<a name="l03352"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga541810a93fbf4cdd9b39f2717f37240d">03352</a> <span class="preprocessor">#define  EXTI_PR_PR18                        ((uint32_t)0x00040000)        </span>
<a name="l03353"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga41e43af631a30492e09e5fd5c50f47f5">03353</a> <span class="preprocessor">#define  EXTI_PR_PR19                        ((uint32_t)0x00080000)        </span>
<a name="l03355"></a>03355 <span class="preprocessor"></span><span class="comment">/******************************************************************************/</span>
<a name="l03356"></a>03356 <span class="comment">/*                                                                            */</span>
<a name="l03357"></a>03357 <span class="comment">/*                                    FLASH                                   */</span>
<a name="l03358"></a>03358 <span class="comment">/*                                                                            */</span>
<a name="l03359"></a>03359 <span class="comment">/******************************************************************************/</span>
<a name="l03360"></a>03360 <span class="comment">/*******************  Bits definition for FLASH_ACR register  *****************/</span>
<a name="l03361"></a>03361 <span class="preprocessor">#define FLASH_ACR_LATENCY                    ((uint32_t)0x00000007)</span>
<a name="l03362"></a>03362 <span class="preprocessor"></span><span class="preprocessor">#define FLASH_ACR_LATENCY_0WS                ((uint32_t)0x00000000)</span>
<a name="l03363"></a>03363 <span class="preprocessor"></span><span class="preprocessor">#define FLASH_ACR_LATENCY_1WS                ((uint32_t)0x00000001)</span>
<a name="l03364"></a>03364 <span class="preprocessor"></span><span class="preprocessor">#define FLASH_ACR_LATENCY_2WS                ((uint32_t)0x00000002)</span>
<a name="l03365"></a>03365 <span class="preprocessor"></span><span class="preprocessor">#define FLASH_ACR_LATENCY_3WS                ((uint32_t)0x00000003)</span>
<a name="l03366"></a>03366 <span class="preprocessor"></span><span class="preprocessor">#define FLASH_ACR_LATENCY_4WS                ((uint32_t)0x00000004)</span>
<a name="l03367"></a>03367 <span class="preprocessor"></span><span class="preprocessor">#define FLASH_ACR_LATENCY_5WS                ((uint32_t)0x00000005)</span>
<a name="l03368"></a>03368 <span class="preprocessor"></span><span class="preprocessor">#define FLASH_ACR_LATENCY_6WS                ((uint32_t)0x00000006)</span>
<a name="l03369"></a>03369 <span class="preprocessor"></span><span class="preprocessor">#define FLASH_ACR_LATENCY_7WS                ((uint32_t)0x00000007)</span>
<a name="l03370"></a>03370 <span class="preprocessor"></span>
<a name="l03371"></a>03371 <span class="preprocessor">#define FLASH_ACR_PRFTEN                     ((uint32_t)0x00000100)</span>
<a name="l03372"></a>03372 <span class="preprocessor"></span><span class="preprocessor">#define FLASH_ACR_ICEN                       ((uint32_t)0x00000200)</span>
<a name="l03373"></a>03373 <span class="preprocessor"></span><span class="preprocessor">#define FLASH_ACR_DCEN                       ((uint32_t)0x00000400)</span>
<a name="l03374"></a>03374 <span class="preprocessor"></span><span class="preprocessor">#define FLASH_ACR_ICRST                      ((uint32_t)0x00000800)</span>
<a name="l03375"></a>03375 <span class="preprocessor"></span><span class="preprocessor">#define FLASH_ACR_DCRST                      ((uint32_t)0x00001000)</span>
<a name="l03376"></a>03376 <span class="preprocessor"></span><span class="preprocessor">#define FLASH_ACR_BYTE0_ADDRESS              ((uint32_t)0x40023C00)</span>
<a name="l03377"></a>03377 <span class="preprocessor"></span><span class="preprocessor">#define FLASH_ACR_BYTE2_ADDRESS              ((uint32_t)0x40023C03)</span>
<a name="l03378"></a>03378 <span class="preprocessor"></span>
<a name="l03379"></a>03379 <span class="comment">/*******************  Bits definition for FLASH_SR register  ******************/</span>
<a name="l03380"></a>03380 <span class="preprocessor">#define FLASH_SR_EOP                         ((uint32_t)0x00000001)</span>
<a name="l03381"></a>03381 <span class="preprocessor"></span><span class="preprocessor">#define FLASH_SR_SOP                         ((uint32_t)0x00000002)</span>
<a name="l03382"></a>03382 <span class="preprocessor"></span><span class="preprocessor">#define FLASH_SR_WRPERR                      ((uint32_t)0x00000010)</span>
<a name="l03383"></a>03383 <span class="preprocessor"></span><span class="preprocessor">#define FLASH_SR_PGAERR                      ((uint32_t)0x00000020)</span>
<a name="l03384"></a>03384 <span class="preprocessor"></span><span class="preprocessor">#define FLASH_SR_PGPERR                      ((uint32_t)0x00000040)</span>
<a name="l03385"></a>03385 <span class="preprocessor"></span><span class="preprocessor">#define FLASH_SR_PGSERR                      ((uint32_t)0x00000080)</span>
<a name="l03386"></a>03386 <span class="preprocessor"></span><span class="preprocessor">#define FLASH_SR_BSY                         ((uint32_t)0x00010000)</span>
<a name="l03387"></a>03387 <span class="preprocessor"></span>
<a name="l03388"></a>03388 <span class="comment">/*******************  Bits definition for FLASH_CR register  ******************/</span>
<a name="l03389"></a>03389 <span class="preprocessor">#define FLASH_CR_PG                          ((uint32_t)0x00000001)</span>
<a name="l03390"></a>03390 <span class="preprocessor"></span><span class="preprocessor">#define FLASH_CR_SER                         ((uint32_t)0x00000002)</span>
<a name="l03391"></a>03391 <span class="preprocessor"></span><span class="preprocessor">#define FLASH_CR_MER                         ((uint32_t)0x00000004)</span>
<a name="l03392"></a>03392 <span class="preprocessor"></span><span class="preprocessor">#define FLASH_CR_SNB_0                       ((uint32_t)0x00000008)</span>
<a name="l03393"></a>03393 <span class="preprocessor"></span><span class="preprocessor">#define FLASH_CR_SNB_1                       ((uint32_t)0x00000010)</span>
<a name="l03394"></a>03394 <span class="preprocessor"></span><span class="preprocessor">#define FLASH_CR_SNB_2                       ((uint32_t)0x00000020)</span>
<a name="l03395"></a>03395 <span class="preprocessor"></span><span class="preprocessor">#define FLASH_CR_SNB_3                       ((uint32_t)0x00000040)</span>
<a name="l03396"></a>03396 <span class="preprocessor"></span><span class="preprocessor">#define FLASH_CR_PSIZE_0                     ((uint32_t)0x00000100)</span>
<a name="l03397"></a>03397 <span class="preprocessor"></span><span class="preprocessor">#define FLASH_CR_PSIZE_1                     ((uint32_t)0x00000200)</span>
<a name="l03398"></a>03398 <span class="preprocessor"></span><span class="preprocessor">#define FLASH_CR_STRT                        ((uint32_t)0x00010000)</span>
<a name="l03399"></a>03399 <span class="preprocessor"></span><span class="preprocessor">#define FLASH_CR_EOPIE                       ((uint32_t)0x01000000)</span>
<a name="l03400"></a>03400 <span class="preprocessor"></span><span class="preprocessor">#define FLASH_CR_LOCK                        ((uint32_t)0x80000000)</span>
<a name="l03401"></a>03401 <span class="preprocessor"></span>
<a name="l03402"></a>03402 <span class="comment">/*******************  Bits definition for FLASH_OPTCR register  ***************/</span>
<a name="l03403"></a>03403 <span class="preprocessor">#define FLASH_OPTCR_OPTLOCK                  ((uint32_t)0x00000001)</span>
<a name="l03404"></a>03404 <span class="preprocessor"></span><span class="preprocessor">#define FLASH_OPTCR_OPTSTRT                  ((uint32_t)0x00000002)</span>
<a name="l03405"></a>03405 <span class="preprocessor"></span><span class="preprocessor">#define FLASH_OPTCR_BOR_LEV_0                ((uint32_t)0x00000004)</span>
<a name="l03406"></a>03406 <span class="preprocessor"></span><span class="preprocessor">#define FLASH_OPTCR_BOR_LEV_1                ((uint32_t)0x00000008)</span>
<a name="l03407"></a>03407 <span class="preprocessor"></span><span class="preprocessor">#define FLASH_OPTCR_BOR_LEV                  ((uint32_t)0x0000000C)</span>
<a name="l03408"></a>03408 <span class="preprocessor"></span><span class="preprocessor">#define FLASH_OPTCR_WDG_SW                   ((uint32_t)0x00000020)</span>
<a name="l03409"></a>03409 <span class="preprocessor"></span><span class="preprocessor">#define FLASH_OPTCR_nRST_STOP                ((uint32_t)0x00000040)</span>
<a name="l03410"></a>03410 <span class="preprocessor"></span><span class="preprocessor">#define FLASH_OPTCR_nRST_STDBY               ((uint32_t)0x00000080)</span>
<a name="l03411"></a>03411 <span class="preprocessor"></span><span class="preprocessor">#define FLASH_OPTCR_RDP_0                    ((uint32_t)0x00000100)</span>
<a name="l03412"></a>03412 <span class="preprocessor"></span><span class="preprocessor">#define FLASH_OPTCR_RDP_1                    ((uint32_t)0x00000200)</span>
<a name="l03413"></a>03413 <span class="preprocessor"></span><span class="preprocessor">#define FLASH_OPTCR_RDP_2                    ((uint32_t)0x00000400)</span>
<a name="l03414"></a>03414 <span class="preprocessor"></span><span class="preprocessor">#define FLASH_OPTCR_RDP_3                    ((uint32_t)0x00000800)</span>
<a name="l03415"></a>03415 <span class="preprocessor"></span><span class="preprocessor">#define FLASH_OPTCR_RDP_4                    ((uint32_t)0x00001000)</span>
<a name="l03416"></a>03416 <span class="preprocessor"></span><span class="preprocessor">#define FLASH_OPTCR_RDP_5                    ((uint32_t)0x00002000)</span>
<a name="l03417"></a>03417 <span class="preprocessor"></span><span class="preprocessor">#define FLASH_OPTCR_RDP_6                    ((uint32_t)0x00004000)</span>
<a name="l03418"></a>03418 <span class="preprocessor"></span><span class="preprocessor">#define FLASH_OPTCR_RDP_7                    ((uint32_t)0x00008000)</span>
<a name="l03419"></a>03419 <span class="preprocessor"></span><span class="preprocessor">#define FLASH_OPTCR_nWRP_0                   ((uint32_t)0x00010000)</span>
<a name="l03420"></a>03420 <span class="preprocessor"></span><span class="preprocessor">#define FLASH_OPTCR_nWRP_1                   ((uint32_t)0x00020000)</span>
<a name="l03421"></a>03421 <span class="preprocessor"></span><span class="preprocessor">#define FLASH_OPTCR_nWRP_2                   ((uint32_t)0x00040000)</span>
<a name="l03422"></a>03422 <span class="preprocessor"></span><span class="preprocessor">#define FLASH_OPTCR_nWRP_3                   ((uint32_t)0x00080000)</span>
<a name="l03423"></a>03423 <span class="preprocessor"></span><span class="preprocessor">#define FLASH_OPTCR_nWRP_4                   ((uint32_t)0x00100000)</span>
<a name="l03424"></a>03424 <span class="preprocessor"></span><span class="preprocessor">#define FLASH_OPTCR_nWRP_5                   ((uint32_t)0x00200000)</span>
<a name="l03425"></a>03425 <span class="preprocessor"></span><span class="preprocessor">#define FLASH_OPTCR_nWRP_6                   ((uint32_t)0x00400000)</span>
<a name="l03426"></a>03426 <span class="preprocessor"></span><span class="preprocessor">#define FLASH_OPTCR_nWRP_7                   ((uint32_t)0x00800000)</span>
<a name="l03427"></a>03427 <span class="preprocessor"></span><span class="preprocessor">#define FLASH_OPTCR_nWRP_8                   ((uint32_t)0x01000000)</span>
<a name="l03428"></a>03428 <span class="preprocessor"></span><span class="preprocessor">#define FLASH_OPTCR_nWRP_9                   ((uint32_t)0x02000000)</span>
<a name="l03429"></a>03429 <span class="preprocessor"></span><span class="preprocessor">#define FLASH_OPTCR_nWRP_10                  ((uint32_t)0x04000000)</span>
<a name="l03430"></a>03430 <span class="preprocessor"></span><span class="preprocessor">#define FLASH_OPTCR_nWRP_11                  ((uint32_t)0x08000000)</span>
<a name="l03431"></a>03431 <span class="preprocessor"></span>
<a name="l03432"></a>03432 <span class="comment">/******************************************************************************/</span>
<a name="l03433"></a>03433 <span class="comment">/*                                                                            */</span>
<a name="l03434"></a>03434 <span class="comment">/*                       Flexible Static Memory Controller                    */</span>
<a name="l03435"></a>03435 <span class="comment">/*                                                                            */</span>
<a name="l03436"></a>03436 <span class="comment">/******************************************************************************/</span>
<a name="l03437"></a>03437 <span class="comment">/******************  Bit definition for FSMC_BCR1 register  *******************/</span>
<a name="l03438"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gad154cab86ce34cebfe1f76e5c2f78e61">03438</a> <span class="preprocessor">#define  FSMC_BCR1_MBKEN                     ((uint32_t)0x00000001)        </span>
<a name="l03439"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga28dd9f93d8687cdc08745df9fcc38e89">03439</a> <span class="preprocessor">#define  FSMC_BCR1_MUXEN                     ((uint32_t)0x00000002)        </span>
<a name="l03441"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga9bab7a47703902d187502ac765ebb05d">03441</a> <span class="preprocessor">#define  FSMC_BCR1_MTYP                      ((uint32_t)0x0000000C)        </span>
<a name="l03442"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga29b921567bd5a422c51f9a0f426ac3f6">03442</a> <span class="preprocessor">#define  FSMC_BCR1_MTYP_0                    ((uint32_t)0x00000004)        </span>
<a name="l03443"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga3fe2fd14b3c0d88aecfb9cf5b44995a0">03443</a> <span class="preprocessor">#define  FSMC_BCR1_MTYP_1                    ((uint32_t)0x00000008)        </span>
<a name="l03445"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaa12297787a0580fedbd5244f0caa0a76">03445</a> <span class="preprocessor">#define  FSMC_BCR1_MWID                      ((uint32_t)0x00000030)        </span>
<a name="l03446"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga1a6fe3b4b28a31c4bbf26a838695fd0c">03446</a> <span class="preprocessor">#define  FSMC_BCR1_MWID_0                    ((uint32_t)0x00000010)        </span>
<a name="l03447"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga65592a6a20efa6aed5b59fe1eba508d8">03447</a> <span class="preprocessor">#define  FSMC_BCR1_MWID_1                    ((uint32_t)0x00000020)        </span>
<a name="l03449"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga14aaca2a8bccab73c7726cf73ee9be16">03449</a> <span class="preprocessor">#define  FSMC_BCR1_FACCEN                    ((uint32_t)0x00000040)        </span>
<a name="l03450"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga94857a0177ae12f1172da65d8708ae97">03450</a> <span class="preprocessor">#define  FSMC_BCR1_BURSTEN                   ((uint32_t)0x00000100)        </span>
<a name="l03451"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga57dbc565fbc7d8ec20fda7ef0da30df4">03451</a> <span class="preprocessor">#define  FSMC_BCR1_WAITPOL                   ((uint32_t)0x00000200)        </span>
<a name="l03452"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gad215e95feee8339393bd93a2bcea11f1">03452</a> <span class="preprocessor">#define  FSMC_BCR1_WRAPMOD                   ((uint32_t)0x00000400)        </span>
<a name="l03453"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga141a337e3f1479e79d62b567ba685bcf">03453</a> <span class="preprocessor">#define  FSMC_BCR1_WAITCFG                   ((uint32_t)0x00000800)        </span>
<a name="l03454"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaa7349a91da7ba38277a068f4e8eea314">03454</a> <span class="preprocessor">#define  FSMC_BCR1_WREN                      ((uint32_t)0x00001000)        </span>
<a name="l03455"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gabe4611a02a4fa635b66d5b5e52328fc5">03455</a> <span class="preprocessor">#define  FSMC_BCR1_WAITEN                    ((uint32_t)0x00002000)        </span>
<a name="l03456"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga7936ff74a1cfba880a9b5bc943dc8661">03456</a> <span class="preprocessor">#define  FSMC_BCR1_EXTMOD                    ((uint32_t)0x00004000)        </span>
<a name="l03457"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaf5673d96c0fb27c7faed335e05ad41c1">03457</a> <span class="preprocessor">#define  FSMC_BCR1_ASYNCWAIT                 ((uint32_t)0x00008000)        </span>
<a name="l03458"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga015672f5aa2132a55e316f5b7a577174">03458</a> <span class="preprocessor">#define  FSMC_BCR1_CBURSTRW                  ((uint32_t)0x00080000)        </span>
<a name="l03460"></a>03460 <span class="preprocessor"></span><span class="comment">/******************  Bit definition for FSMC_BCR2 register  *******************/</span>
<a name="l03461"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gad9c99df3c6cebc68f6695ad7bc13f717">03461</a> <span class="preprocessor">#define  FSMC_BCR2_MBKEN                     ((uint32_t)0x00000001)        </span>
<a name="l03462"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga9f65c4348ab55c12695730bde8be8986">03462</a> <span class="preprocessor">#define  FSMC_BCR2_MUXEN                     ((uint32_t)0x00000002)        </span>
<a name="l03464"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gabdf82247710aaeff72fb37113bff3daf">03464</a> <span class="preprocessor">#define  FSMC_BCR2_MTYP                      ((uint32_t)0x0000000C)        </span>
<a name="l03465"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gac595e1e3045aad0b379367f47bf10a84">03465</a> <span class="preprocessor">#define  FSMC_BCR2_MTYP_0                    ((uint32_t)0x00000004)        </span>
<a name="l03466"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga8b9e5b00171ea739ba67a627a2484f47">03466</a> <span class="preprocessor">#define  FSMC_BCR2_MTYP_1                    ((uint32_t)0x00000008)        </span>
<a name="l03468"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga4099746e30f71a98ea71d1048a5d028a">03468</a> <span class="preprocessor">#define  FSMC_BCR2_MWID                      ((uint32_t)0x00000030)        </span>
<a name="l03469"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga8501d3ce728f6a074061294a9e5a54cf">03469</a> <span class="preprocessor">#define  FSMC_BCR2_MWID_0                    ((uint32_t)0x00000010)        </span>
<a name="l03470"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga74276c5828d545cf4b2db2d568c60627">03470</a> <span class="preprocessor">#define  FSMC_BCR2_MWID_1                    ((uint32_t)0x00000020)        </span>
<a name="l03472"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga7a4e1ad30533ab54b45987cab30d51a0">03472</a> <span class="preprocessor">#define  FSMC_BCR2_FACCEN                    ((uint32_t)0x00000040)        </span>
<a name="l03473"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga0d8202b9b40d3912a6294fe2a0e28ebf">03473</a> <span class="preprocessor">#define  FSMC_BCR2_BURSTEN                   ((uint32_t)0x00000100)        </span>
<a name="l03474"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaa0f59e7aa2664f9c767ce22bec369698">03474</a> <span class="preprocessor">#define  FSMC_BCR2_WAITPOL                   ((uint32_t)0x00000200)        </span>
<a name="l03475"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga9e93e4e902a636d4d75a1fd7e884afea">03475</a> <span class="preprocessor">#define  FSMC_BCR2_WRAPMOD                   ((uint32_t)0x00000400)        </span>
<a name="l03476"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga5141640b4dcb78a524740b681819f9f1">03476</a> <span class="preprocessor">#define  FSMC_BCR2_WAITCFG                   ((uint32_t)0x00000800)        </span>
<a name="l03477"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gad446f2fcb7909b80a8c1731141be5186">03477</a> <span class="preprocessor">#define  FSMC_BCR2_WREN                      ((uint32_t)0x00001000)        </span>
<a name="l03478"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gad015d2aa1c58b48681f35a4f92eaf7f7">03478</a> <span class="preprocessor">#define  FSMC_BCR2_WAITEN                    ((uint32_t)0x00002000)        </span>
<a name="l03479"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga76d3e5d899ba2399d3318da577d58ac6">03479</a> <span class="preprocessor">#define  FSMC_BCR2_EXTMOD                    ((uint32_t)0x00004000)        </span>
<a name="l03480"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gad45d1b552ba61ccbb1dc4ebfc556285a">03480</a> <span class="preprocessor">#define  FSMC_BCR2_ASYNCWAIT                 ((uint32_t)0x00008000)        </span>
<a name="l03481"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gae64b1874f1ab83a1d0224cb66e504dff">03481</a> <span class="preprocessor">#define  FSMC_BCR2_CBURSTRW                  ((uint32_t)0x00080000)        </span>
<a name="l03483"></a>03483 <span class="preprocessor"></span><span class="comment">/******************  Bit definition for FSMC_BCR3 register  *******************/</span>
<a name="l03484"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga0d7810ad338086a1ec9b15f339ed6f4d">03484</a> <span class="preprocessor">#define  FSMC_BCR3_MBKEN                     ((uint32_t)0x00000001)        </span>
<a name="l03485"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gadaae648c8591e7650cba828910638d3d">03485</a> <span class="preprocessor">#define  FSMC_BCR3_MUXEN                     ((uint32_t)0x00000002)        </span>
<a name="l03487"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga319fb6069b651eb947b4d0ba3c9f6196">03487</a> <span class="preprocessor">#define  FSMC_BCR3_MTYP                      ((uint32_t)0x0000000C)        </span>
<a name="l03488"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaf33b80510e653dd32de2ae1ec1a1dfb5">03488</a> <span class="preprocessor">#define  FSMC_BCR3_MTYP_0                    ((uint32_t)0x00000004)        </span>
<a name="l03489"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga2a038553e3a30df4b6e331cad504069b">03489</a> <span class="preprocessor">#define  FSMC_BCR3_MTYP_1                    ((uint32_t)0x00000008)        </span>
<a name="l03491"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga51097cfe8d4263a30d292e7e9dc73cd2">03491</a> <span class="preprocessor">#define  FSMC_BCR3_MWID                      ((uint32_t)0x00000030)        </span>
<a name="l03492"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga373b764c1a4104300eb587aa4510c1f1">03492</a> <span class="preprocessor">#define  FSMC_BCR3_MWID_0                    ((uint32_t)0x00000010)        </span>
<a name="l03493"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga43c7292c185269cc11d986f3ae0ceb24">03493</a> <span class="preprocessor">#define  FSMC_BCR3_MWID_1                    ((uint32_t)0x00000020)        </span>
<a name="l03495"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga380c39b95426ac9a18c70e3f56016c81">03495</a> <span class="preprocessor">#define  FSMC_BCR3_FACCEN                    ((uint32_t)0x00000040)        </span>
<a name="l03496"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gad9badf60f5caa010e041d66d40af596a">03496</a> <span class="preprocessor">#define  FSMC_BCR3_BURSTEN                   ((uint32_t)0x00000100)        </span>
<a name="l03497"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gabbca3d0aa315f3e9bc6bacf244bdb747">03497</a> <span class="preprocessor">#define  FSMC_BCR3_WAITPOL                   ((uint32_t)0x00000200)        </span>
<a name="l03498"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga44fc6e205695d39b63c0f5b18c3cd214">03498</a> <span class="preprocessor">#define  FSMC_BCR3_WRAPMOD                   ((uint32_t)0x00000400)        </span>
<a name="l03499"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gab845515c37adae28d0e1452596cca7ea">03499</a> <span class="preprocessor">#define  FSMC_BCR3_WAITCFG                   ((uint32_t)0x00000800)        </span>
<a name="l03500"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga22c9b0145aa62cafd915a4c7da1931b5">03500</a> <span class="preprocessor">#define  FSMC_BCR3_WREN                      ((uint32_t)0x00001000)        </span>
<a name="l03501"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga9665b36b791862c464f07ad49dea315c">03501</a> <span class="preprocessor">#define  FSMC_BCR3_WAITEN                    ((uint32_t)0x00002000)        </span>
<a name="l03502"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga6ab23550b17dca7ede57f8b5ef05f2e7">03502</a> <span class="preprocessor">#define  FSMC_BCR3_EXTMOD                    ((uint32_t)0x00004000)        </span>
<a name="l03503"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga9e16fb6b68a8adb7722871ccdd2d9a44">03503</a> <span class="preprocessor">#define  FSMC_BCR3_ASYNCWAIT                 ((uint32_t)0x00008000)        </span>
<a name="l03504"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga70c6da37696af84767f82efd0df3a7da">03504</a> <span class="preprocessor">#define  FSMC_BCR3_CBURSTRW                  ((uint32_t)0x00080000)        </span>
<a name="l03506"></a>03506 <span class="preprocessor"></span><span class="comment">/******************  Bit definition for FSMC_BCR4 register  *******************/</span>
<a name="l03507"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga9a1ea2c2967cda7ef1597c4fb1a9dd9a">03507</a> <span class="preprocessor">#define  FSMC_BCR4_MBKEN                     ((uint32_t)0x00000001)        </span>
<a name="l03508"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga92d644d34b59762d0b48f7784d3aed4b">03508</a> <span class="preprocessor">#define  FSMC_BCR4_MUXEN                     ((uint32_t)0x00000002)        </span>
<a name="l03510"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga1f9bf2c236b772e76174aff4388a1b6f">03510</a> <span class="preprocessor">#define  FSMC_BCR4_MTYP                      ((uint32_t)0x0000000C)        </span>
<a name="l03511"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga66d358ec27a34fe13131d852b950643e">03511</a> <span class="preprocessor">#define  FSMC_BCR4_MTYP_0                    ((uint32_t)0x00000004)        </span>
<a name="l03512"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaac5abffefdc124215182346aba701183">03512</a> <span class="preprocessor">#define  FSMC_BCR4_MTYP_1                    ((uint32_t)0x00000008)        </span>
<a name="l03514"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga5c4ce32ca454c42344cfe73f71abd274">03514</a> <span class="preprocessor">#define  FSMC_BCR4_MWID                      ((uint32_t)0x00000030)        </span>
<a name="l03515"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga1c8f397cfb1f07421abeaf3060f7a329">03515</a> <span class="preprocessor">#define  FSMC_BCR4_MWID_0                    ((uint32_t)0x00000010)        </span>
<a name="l03516"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaf5cd3a31190eb0cea8a72b55d8369970">03516</a> <span class="preprocessor">#define  FSMC_BCR4_MWID_1                    ((uint32_t)0x00000020)        </span>
<a name="l03518"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gabf769d7958a8c610ccca912600e61f30">03518</a> <span class="preprocessor">#define  FSMC_BCR4_FACCEN                    ((uint32_t)0x00000040)        </span>
<a name="l03519"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga2c6ffdcee5dc3de1402bd8b644d6ecf4">03519</a> <span class="preprocessor">#define  FSMC_BCR4_BURSTEN                   ((uint32_t)0x00000100)        </span>
<a name="l03520"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga485976f8857949064d060374031cad3d">03520</a> <span class="preprocessor">#define  FSMC_BCR4_WAITPOL                   ((uint32_t)0x00000200)        </span>
<a name="l03521"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaa35333cfffc35c7948ee0aa0e5672c3c">03521</a> <span class="preprocessor">#define  FSMC_BCR4_WRAPMOD                   ((uint32_t)0x00000400)        </span>
<a name="l03522"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga11c35ab0ee9ee23a5352218b4b84a258">03522</a> <span class="preprocessor">#define  FSMC_BCR4_WAITCFG                   ((uint32_t)0x00000800)        </span>
<a name="l03523"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gadf2eef4eb8e6bb99cace5145b6ad09ee">03523</a> <span class="preprocessor">#define  FSMC_BCR4_WREN                      ((uint32_t)0x00001000)        </span>
<a name="l03524"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga458727d27c2bc7cede05f6537bfc1bd8">03524</a> <span class="preprocessor">#define  FSMC_BCR4_WAITEN                    ((uint32_t)0x00002000)        </span>
<a name="l03525"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga6794966a05855913923294f5c2ab69ed">03525</a> <span class="preprocessor">#define  FSMC_BCR4_EXTMOD                    ((uint32_t)0x00004000)        </span>
<a name="l03526"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga158eeaca2258bc25beae918d01e01dd8">03526</a> <span class="preprocessor">#define  FSMC_BCR4_ASYNCWAIT                 ((uint32_t)0x00008000)        </span>
<a name="l03527"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga19293300b8230e38afa1c16c526b3f29">03527</a> <span class="preprocessor">#define  FSMC_BCR4_CBURSTRW                  ((uint32_t)0x00080000)        </span>
<a name="l03529"></a>03529 <span class="preprocessor"></span><span class="comment">/******************  Bit definition for FSMC_BTR1 register  ******************/</span>
<a name="l03530"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gab457e5d3a33d80db3ad070b1cf57669a">03530</a> <span class="preprocessor">#define  FSMC_BTR1_ADDSET                    ((uint32_t)0x0000000F)        </span>
<a name="l03531"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gae29ca17c63df62cc12c06e6cfa3429e3">03531</a> <span class="preprocessor">#define  FSMC_BTR1_ADDSET_0                  ((uint32_t)0x00000001)        </span>
<a name="l03532"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaefb98ce348ba665f122e44ddc0390b45">03532</a> <span class="preprocessor">#define  FSMC_BTR1_ADDSET_1                  ((uint32_t)0x00000002)        </span>
<a name="l03533"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaa5e5c5b00c91aca1cc266622d3f30bf0">03533</a> <span class="preprocessor">#define  FSMC_BTR1_ADDSET_2                  ((uint32_t)0x00000004)        </span>
<a name="l03534"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga2f0105afe671cd62730cf879072c80f3">03534</a> <span class="preprocessor">#define  FSMC_BTR1_ADDSET_3                  ((uint32_t)0x00000008)        </span>
<a name="l03536"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gadc4a3860c48a62ff0290622e1937072d">03536</a> <span class="preprocessor">#define  FSMC_BTR1_ADDHLD                    ((uint32_t)0x000000F0)        </span>
<a name="l03537"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga222a16d5a1a8deebaf39a96d94d3c3f0">03537</a> <span class="preprocessor">#define  FSMC_BTR1_ADDHLD_0                  ((uint32_t)0x00000010)        </span>
<a name="l03538"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga5ad1f9164644c4ff4c6ae5a655478abc">03538</a> <span class="preprocessor">#define  FSMC_BTR1_ADDHLD_1                  ((uint32_t)0x00000020)        </span>
<a name="l03539"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga3f9d68df0fd84b77342a565e9faad929">03539</a> <span class="preprocessor">#define  FSMC_BTR1_ADDHLD_2                  ((uint32_t)0x00000040)        </span>
<a name="l03540"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga6e88e45163e76f529b5a94937526f45c">03540</a> <span class="preprocessor">#define  FSMC_BTR1_ADDHLD_3                  ((uint32_t)0x00000080)        </span>
<a name="l03542"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gae39175370a991b500962fd084230e389">03542</a> <span class="preprocessor">#define  FSMC_BTR1_DATAST                    ((uint32_t)0x0000FF00)        </span>
<a name="l03543"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga4488a428f33d96263a00a30af42b849b">03543</a> <span class="preprocessor">#define  FSMC_BTR1_DATAST_0                  ((uint32_t)0x00000100)        </span>
<a name="l03544"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gad53bd6a1decfafdb420a37453b3b5545">03544</a> <span class="preprocessor">#define  FSMC_BTR1_DATAST_1                  ((uint32_t)0x00000200)        </span>
<a name="l03545"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gacce8f6cf5a9ba24943b3e762bde00aee">03545</a> <span class="preprocessor">#define  FSMC_BTR1_DATAST_2                  ((uint32_t)0x00000400)        </span>
<a name="l03546"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga99638cc2cbe0dead029c201e5f30c3a8">03546</a> <span class="preprocessor">#define  FSMC_BTR1_DATAST_3                  ((uint32_t)0x00000800)        </span>
<a name="l03548"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga7ec9346bbaf845f1dffe33c4a625c0ac">03548</a> <span class="preprocessor">#define  FSMC_BTR1_BUSTURN                   ((uint32_t)0x000F0000)        </span>
<a name="l03549"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga6c1578a85c4f2cef9e034c7b5da6d454">03549</a> <span class="preprocessor">#define  FSMC_BTR1_BUSTURN_0                 ((uint32_t)0x00010000)        </span>
<a name="l03550"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaf873cbfe4827496215eb08bb33ae4784">03550</a> <span class="preprocessor">#define  FSMC_BTR1_BUSTURN_1                 ((uint32_t)0x00020000)        </span>
<a name="l03551"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gad768d3ff0a5159e552663c9489b977f6">03551</a> <span class="preprocessor">#define  FSMC_BTR1_BUSTURN_2                 ((uint32_t)0x00040000)        </span>
<a name="l03552"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaf3ecfd25fb64efb3745ee96b2877a017">03552</a> <span class="preprocessor">#define  FSMC_BTR1_BUSTURN_3                 ((uint32_t)0x00080000)        </span>
<a name="l03554"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gac7c4dbd43df84559e30a9c332b265ad5">03554</a> <span class="preprocessor">#define  FSMC_BTR1_CLKDIV                    ((uint32_t)0x00F00000)        </span>
<a name="l03555"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gabe9c9e09de00afad666ace28c608032f">03555</a> <span class="preprocessor">#define  FSMC_BTR1_CLKDIV_0                  ((uint32_t)0x00100000)        </span>
<a name="l03556"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gafffebd7a0cf6e6d80b65804c2c50ce62">03556</a> <span class="preprocessor">#define  FSMC_BTR1_CLKDIV_1                  ((uint32_t)0x00200000)        </span>
<a name="l03557"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga43afa754305cc1a7ff3075cdd4309990">03557</a> <span class="preprocessor">#define  FSMC_BTR1_CLKDIV_2                  ((uint32_t)0x00400000)        </span>
<a name="l03558"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga68a146aec5d723a84945ae6da6c0692f">03558</a> <span class="preprocessor">#define  FSMC_BTR1_CLKDIV_3                  ((uint32_t)0x00800000)        </span>
<a name="l03560"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga4ef6dcccdb11a1b094966be0c019124b">03560</a> <span class="preprocessor">#define  FSMC_BTR1_DATLAT                    ((uint32_t)0x0F000000)        </span>
<a name="l03561"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gae2d832593697ba108d99a97e4fdfd159">03561</a> <span class="preprocessor">#define  FSMC_BTR1_DATLAT_0                  ((uint32_t)0x01000000)        </span>
<a name="l03562"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga2a7e4efc546c1c9d16c750a4542e1c55">03562</a> <span class="preprocessor">#define  FSMC_BTR1_DATLAT_1                  ((uint32_t)0x02000000)        </span>
<a name="l03563"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga22e7d41e0f94ab896c6eea199eb0aef1">03563</a> <span class="preprocessor">#define  FSMC_BTR1_DATLAT_2                  ((uint32_t)0x04000000)        </span>
<a name="l03564"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga8b42f22fc488e0ed0d06832118773123">03564</a> <span class="preprocessor">#define  FSMC_BTR1_DATLAT_3                  ((uint32_t)0x08000000)        </span>
<a name="l03566"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga027548b6b5971a2c56558932c956fa4c">03566</a> <span class="preprocessor">#define  FSMC_BTR1_ACCMOD                    ((uint32_t)0x30000000)        </span>
<a name="l03567"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaf77aa4936dc4f35d1b426d147c643c80">03567</a> <span class="preprocessor">#define  FSMC_BTR1_ACCMOD_0                  ((uint32_t)0x10000000)        </span>
<a name="l03568"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga7b336cf3ae23cfda19895927b63af558">03568</a> <span class="preprocessor">#define  FSMC_BTR1_ACCMOD_1                  ((uint32_t)0x20000000)        </span>
<a name="l03570"></a>03570 <span class="preprocessor"></span><span class="comment">/******************  Bit definition for FSMC_BTR2 register  *******************/</span>
<a name="l03571"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga23697810b99730ddf52834a5066c1ba5">03571</a> <span class="preprocessor">#define  FSMC_BTR2_ADDSET                    ((uint32_t)0x0000000F)        </span>
<a name="l03572"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga827398dc098f2d08bb77a04b2e7d6ba3">03572</a> <span class="preprocessor">#define  FSMC_BTR2_ADDSET_0                  ((uint32_t)0x00000001)        </span>
<a name="l03573"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga1b40f47f2db0db78de6fe2df58b5d591">03573</a> <span class="preprocessor">#define  FSMC_BTR2_ADDSET_1                  ((uint32_t)0x00000002)        </span>
<a name="l03574"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga558185a28aeedbb098890348a041a74d">03574</a> <span class="preprocessor">#define  FSMC_BTR2_ADDSET_2                  ((uint32_t)0x00000004)        </span>
<a name="l03575"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gadbd4d42459a990825b61962d9118cd7b">03575</a> <span class="preprocessor">#define  FSMC_BTR2_ADDSET_3                  ((uint32_t)0x00000008)        </span>
<a name="l03577"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gac37c974d0260ba1dbd1acaf6fceb425c">03577</a> <span class="preprocessor">#define  FSMC_BTR2_ADDHLD                    ((uint32_t)0x000000F0)        </span>
<a name="l03578"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gabbf56fc3a549d1e68d56e1587123bd27">03578</a> <span class="preprocessor">#define  FSMC_BTR2_ADDHLD_0                  ((uint32_t)0x00000010)        </span>
<a name="l03579"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga0b7d19f02444ce8b3286d44258c6caef">03579</a> <span class="preprocessor">#define  FSMC_BTR2_ADDHLD_1                  ((uint32_t)0x00000020)        </span>
<a name="l03580"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga7e9433e15e301d5d3f0dd6b73c9db2f7">03580</a> <span class="preprocessor">#define  FSMC_BTR2_ADDHLD_2                  ((uint32_t)0x00000040)        </span>
<a name="l03581"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gacc538e46145ed4947194f3ad63e211b7">03581</a> <span class="preprocessor">#define  FSMC_BTR2_ADDHLD_3                  ((uint32_t)0x00000080)        </span>
<a name="l03583"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gabe1d3fe096ea53ea073b78bd6ddbff58">03583</a> <span class="preprocessor">#define  FSMC_BTR2_DATAST                    ((uint32_t)0x0000FF00)        </span>
<a name="l03584"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaa066dab45a22ebd3a7102b92dcd251bd">03584</a> <span class="preprocessor">#define  FSMC_BTR2_DATAST_0                  ((uint32_t)0x00000100)        </span>
<a name="l03585"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga68c15ca5fdd13efb5499f0e86bd5bc88">03585</a> <span class="preprocessor">#define  FSMC_BTR2_DATAST_1                  ((uint32_t)0x00000200)        </span>
<a name="l03586"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga36cfe553d431ca6976f0d36c73045836">03586</a> <span class="preprocessor">#define  FSMC_BTR2_DATAST_2                  ((uint32_t)0x00000400)        </span>
<a name="l03587"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga874499b29d2b72a75265f16a2d8ed834">03587</a> <span class="preprocessor">#define  FSMC_BTR2_DATAST_3                  ((uint32_t)0x00000800)        </span>
<a name="l03589"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga5ae7c94522af51d2f96a0fa715dfa9b0">03589</a> <span class="preprocessor">#define  FSMC_BTR2_BUSTURN                   ((uint32_t)0x000F0000)        </span>
<a name="l03590"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga2617a99e5eab8b31ff168557f93852a3">03590</a> <span class="preprocessor">#define  FSMC_BTR2_BUSTURN_0                 ((uint32_t)0x00010000)        </span>
<a name="l03591"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga83871fa5cde9d72ec840d29d43aa2e57">03591</a> <span class="preprocessor">#define  FSMC_BTR2_BUSTURN_1                 ((uint32_t)0x00020000)        </span>
<a name="l03592"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gacada2902f8612df1e5ac6e224bcf8d3c">03592</a> <span class="preprocessor">#define  FSMC_BTR2_BUSTURN_2                 ((uint32_t)0x00040000)        </span>
<a name="l03593"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga66ad543195f36fdb3efdf7550381f982">03593</a> <span class="preprocessor">#define  FSMC_BTR2_BUSTURN_3                 ((uint32_t)0x00080000)        </span>
<a name="l03595"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga37fdb25c494cf314cb680f84c5e0a503">03595</a> <span class="preprocessor">#define  FSMC_BTR2_CLKDIV                    ((uint32_t)0x00F00000)        </span>
<a name="l03596"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga1ac8729c8ac330f6ade93a6a15a4ba70">03596</a> <span class="preprocessor">#define  FSMC_BTR2_CLKDIV_0                  ((uint32_t)0x00100000)        </span>
<a name="l03597"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga31920e8bf2d83ad3c2849f8e942bb6e4">03597</a> <span class="preprocessor">#define  FSMC_BTR2_CLKDIV_1                  ((uint32_t)0x00200000)        </span>
<a name="l03598"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaf5ba3172687049c687e3a38ec08d6c5a">03598</a> <span class="preprocessor">#define  FSMC_BTR2_CLKDIV_2                  ((uint32_t)0x00400000)        </span>
<a name="l03599"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga453c2a90dc3340596c9d34672cede6a0">03599</a> <span class="preprocessor">#define  FSMC_BTR2_CLKDIV_3                  ((uint32_t)0x00800000)        </span>
<a name="l03601"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gae3247db1653b31df0c34ab7898400bb5">03601</a> <span class="preprocessor">#define  FSMC_BTR2_DATLAT                    ((uint32_t)0x0F000000)        </span>
<a name="l03602"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga0510047c932d2833f6cbe0a4a5d7b9b5">03602</a> <span class="preprocessor">#define  FSMC_BTR2_DATLAT_0                  ((uint32_t)0x01000000)        </span>
<a name="l03603"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga4e1852b706b3c719c0eab8ef863b39e0">03603</a> <span class="preprocessor">#define  FSMC_BTR2_DATLAT_1                  ((uint32_t)0x02000000)        </span>
<a name="l03604"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga7ace24f50d1c51c978af55d47c13c0e9">03604</a> <span class="preprocessor">#define  FSMC_BTR2_DATLAT_2                  ((uint32_t)0x04000000)        </span>
<a name="l03605"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga99389b63c4dee3c54aa1de36a4119add">03605</a> <span class="preprocessor">#define  FSMC_BTR2_DATLAT_3                  ((uint32_t)0x08000000)        </span>
<a name="l03607"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga07b93600977cde6e31a9464f87606043">03607</a> <span class="preprocessor">#define  FSMC_BTR2_ACCMOD                    ((uint32_t)0x30000000)        </span>
<a name="l03608"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga9383d89d5e557a166f6b8290892b89b3">03608</a> <span class="preprocessor">#define  FSMC_BTR2_ACCMOD_0                  ((uint32_t)0x10000000)        </span>
<a name="l03609"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gad200e1dc2d1835e3dc0fa8f0483eb2c0">03609</a> <span class="preprocessor">#define  FSMC_BTR2_ACCMOD_1                  ((uint32_t)0x20000000)        </span>
<a name="l03611"></a>03611 <span class="preprocessor"></span><span class="comment">/*******************  Bit definition for FSMC_BTR3 register  *******************/</span>
<a name="l03612"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaf3e55daf436a25fadae7384611aa0f89">03612</a> <span class="preprocessor">#define  FSMC_BTR3_ADDSET                    ((uint32_t)0x0000000F)        </span>
<a name="l03613"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gab6a21211dd7a3445e944af0fe1a4b600">03613</a> <span class="preprocessor">#define  FSMC_BTR3_ADDSET_0                  ((uint32_t)0x00000001)        </span>
<a name="l03614"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga51c23d36fa8e7e38048d94830bf0f74f">03614</a> <span class="preprocessor">#define  FSMC_BTR3_ADDSET_1                  ((uint32_t)0x00000002)        </span>
<a name="l03615"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga93be4171cb7d0b66d8d4d12e61b07b88">03615</a> <span class="preprocessor">#define  FSMC_BTR3_ADDSET_2                  ((uint32_t)0x00000004)        </span>
<a name="l03616"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gab01cf0b1c88857669d10fee8d7ba4d85">03616</a> <span class="preprocessor">#define  FSMC_BTR3_ADDSET_3                  ((uint32_t)0x00000008)        </span>
<a name="l03618"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga7833ee760b2400e6fb483b1d83cbdff3">03618</a> <span class="preprocessor">#define  FSMC_BTR3_ADDHLD                    ((uint32_t)0x000000F0)        </span>
<a name="l03619"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gad417ccae1c4018d0ff5c76c942aeb2ca">03619</a> <span class="preprocessor">#define  FSMC_BTR3_ADDHLD_0                  ((uint32_t)0x00000010)        </span>
<a name="l03620"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga60d0ae6af13ef088367cef06c7f207d3">03620</a> <span class="preprocessor">#define  FSMC_BTR3_ADDHLD_1                  ((uint32_t)0x00000020)        </span>
<a name="l03621"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gac029aaed48e2a3e2eedf767fe0ce0b92">03621</a> <span class="preprocessor">#define  FSMC_BTR3_ADDHLD_2                  ((uint32_t)0x00000040)        </span>
<a name="l03622"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga5b6aab5907bc42e140ca5a4d60fcd64c">03622</a> <span class="preprocessor">#define  FSMC_BTR3_ADDHLD_3                  ((uint32_t)0x00000080)        </span>
<a name="l03624"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga1e9ac671a510ee06e86c41d7876ffe10">03624</a> <span class="preprocessor">#define  FSMC_BTR3_DATAST                    ((uint32_t)0x0000FF00)        </span>
<a name="l03625"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga65fe87d29c1a4ee0b08014ed8e0423e1">03625</a> <span class="preprocessor">#define  FSMC_BTR3_DATAST_0                  ((uint32_t)0x00000100)        </span>
<a name="l03626"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gad33e3df5c80255cb5e11ba427e9c224f">03626</a> <span class="preprocessor">#define  FSMC_BTR3_DATAST_1                  ((uint32_t)0x00000200)        </span>
<a name="l03627"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga4a31f070e41c6785ebc606d4f25d103a">03627</a> <span class="preprocessor">#define  FSMC_BTR3_DATAST_2                  ((uint32_t)0x00000400)        </span>
<a name="l03628"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gad220fbd264261a37eac09d4f6c0b79a2">03628</a> <span class="preprocessor">#define  FSMC_BTR3_DATAST_3                  ((uint32_t)0x00000800)        </span>
<a name="l03630"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gae8a3ad9f940c6942682d8d97b1eb0ca4">03630</a> <span class="preprocessor">#define  FSMC_BTR3_BUSTURN                   ((uint32_t)0x000F0000)        </span>
<a name="l03631"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga739f2db66e52626aa9a5ee02c11d7a34">03631</a> <span class="preprocessor">#define  FSMC_BTR3_BUSTURN_0                 ((uint32_t)0x00010000)        </span>
<a name="l03632"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga7e4c4102ea6e6cf2082e78168edfc18e">03632</a> <span class="preprocessor">#define  FSMC_BTR3_BUSTURN_1                 ((uint32_t)0x00020000)        </span>
<a name="l03633"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gad5eab2601ae3cd040bf44feb3e70c459">03633</a> <span class="preprocessor">#define  FSMC_BTR3_BUSTURN_2                 ((uint32_t)0x00040000)        </span>
<a name="l03634"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gacf61e23804e0fa3ca45f851ca98de371">03634</a> <span class="preprocessor">#define  FSMC_BTR3_BUSTURN_3                 ((uint32_t)0x00080000)        </span>
<a name="l03636"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga47a8d8e279c50995143ecf4124580703">03636</a> <span class="preprocessor">#define  FSMC_BTR3_CLKDIV                    ((uint32_t)0x00F00000)        </span>
<a name="l03637"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gadd9c93b0ee64856981394a63d6a3a964">03637</a> <span class="preprocessor">#define  FSMC_BTR3_CLKDIV_0                  ((uint32_t)0x00100000)        </span>
<a name="l03638"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga98fa7611b4ae197ab25cdf1cae9f8ee1">03638</a> <span class="preprocessor">#define  FSMC_BTR3_CLKDIV_1                  ((uint32_t)0x00200000)        </span>
<a name="l03639"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaf806c044b2a3d1417acc79907dcaef4b">03639</a> <span class="preprocessor">#define  FSMC_BTR3_CLKDIV_2                  ((uint32_t)0x00400000)        </span>
<a name="l03640"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaa9bf0683d046f9bcfb0d55a065ae69ab">03640</a> <span class="preprocessor">#define  FSMC_BTR3_CLKDIV_3                  ((uint32_t)0x00800000)        </span>
<a name="l03642"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaa88a80458ddd56b0dfa7cf3599b986dd">03642</a> <span class="preprocessor">#define  FSMC_BTR3_DATLAT                    ((uint32_t)0x0F000000)        </span>
<a name="l03643"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga655083fdb0e563b9a4d6ea589194ba02">03643</a> <span class="preprocessor">#define  FSMC_BTR3_DATLAT_0                  ((uint32_t)0x01000000)        </span>
<a name="l03644"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga486280713c8f07d7033bce4e74825130">03644</a> <span class="preprocessor">#define  FSMC_BTR3_DATLAT_1                  ((uint32_t)0x02000000)        </span>
<a name="l03645"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga8314e30c84dccd983de04fdeeb57c360">03645</a> <span class="preprocessor">#define  FSMC_BTR3_DATLAT_2                  ((uint32_t)0x04000000)        </span>
<a name="l03646"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gac7e7da5269a2dac164c9d1d01da2bc28">03646</a> <span class="preprocessor">#define  FSMC_BTR3_DATLAT_3                  ((uint32_t)0x08000000)        </span>
<a name="l03648"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga56c8f213e437ceed2140f2c16a0416cd">03648</a> <span class="preprocessor">#define  FSMC_BTR3_ACCMOD                    ((uint32_t)0x30000000)        </span>
<a name="l03649"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga4d50e71940995d42c5f9fadcb7cd61f2">03649</a> <span class="preprocessor">#define  FSMC_BTR3_ACCMOD_0                  ((uint32_t)0x10000000)        </span>
<a name="l03650"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gac8bbfd5e08b73d1c5de53ee0ff0ddb9a">03650</a> <span class="preprocessor">#define  FSMC_BTR3_ACCMOD_1                  ((uint32_t)0x20000000)        </span>
<a name="l03652"></a>03652 <span class="preprocessor"></span><span class="comment">/******************  Bit definition for FSMC_BTR4 register  *******************/</span>
<a name="l03653"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gab44cc2146b4cf6bc8f43292512fd8cf8">03653</a> <span class="preprocessor">#define  FSMC_BTR4_ADDSET                    ((uint32_t)0x0000000F)        </span>
<a name="l03654"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaa0ee1ab3716b0ab1a4e7b51234af7c63">03654</a> <span class="preprocessor">#define  FSMC_BTR4_ADDSET_0                  ((uint32_t)0x00000001)        </span>
<a name="l03655"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gacd427c001c5b17a3e083c81f6b228a50">03655</a> <span class="preprocessor">#define  FSMC_BTR4_ADDSET_1                  ((uint32_t)0x00000002)        </span>
<a name="l03656"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gae722fdaa69bfb7622aa80c82e3772949">03656</a> <span class="preprocessor">#define  FSMC_BTR4_ADDSET_2                  ((uint32_t)0x00000004)        </span>
<a name="l03657"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga0f8ab4a1c7fe6e7dc2b093add88c274e">03657</a> <span class="preprocessor">#define  FSMC_BTR4_ADDSET_3                  ((uint32_t)0x00000008)        </span>
<a name="l03659"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga1e52ae9a5d59507bdf9f4f9da19444ed">03659</a> <span class="preprocessor">#define  FSMC_BTR4_ADDHLD                    ((uint32_t)0x000000F0)        </span>
<a name="l03660"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gadf6200f13c3eed1e9646750897a987a2">03660</a> <span class="preprocessor">#define  FSMC_BTR4_ADDHLD_0                  ((uint32_t)0x00000010)        </span>
<a name="l03661"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga0803bc2ad60138e0eef53a53ca5bf537">03661</a> <span class="preprocessor">#define  FSMC_BTR4_ADDHLD_1                  ((uint32_t)0x00000020)        </span>
<a name="l03662"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga893711250b9d3ea2e5e48ca53d1e0147">03662</a> <span class="preprocessor">#define  FSMC_BTR4_ADDHLD_2                  ((uint32_t)0x00000040)        </span>
<a name="l03663"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga75c73d4bb0ddcac383ca610a604d95b3">03663</a> <span class="preprocessor">#define  FSMC_BTR4_ADDHLD_3                  ((uint32_t)0x00000080)        </span>
<a name="l03665"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga2c28625ee031527a29f7cb7db1bb97cf">03665</a> <span class="preprocessor">#define  FSMC_BTR4_DATAST                    ((uint32_t)0x0000FF00)        </span>
<a name="l03666"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gabdb0212604c6c58c9524adc7931e2897">03666</a> <span class="preprocessor">#define  FSMC_BTR4_DATAST_0                  ((uint32_t)0x00000100)        </span>
<a name="l03667"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga2353d753ca5532703b4f822b7d2a7382">03667</a> <span class="preprocessor">#define  FSMC_BTR4_DATAST_1                  ((uint32_t)0x00000200)        </span>
<a name="l03668"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga8d82a6f3fcf69d6b96968118db7b8216">03668</a> <span class="preprocessor">#define  FSMC_BTR4_DATAST_2                  ((uint32_t)0x00000400)        </span>
<a name="l03669"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga3e0860f92bb204c4b5902d3e34b8b30a">03669</a> <span class="preprocessor">#define  FSMC_BTR4_DATAST_3                  ((uint32_t)0x00000800)        </span>
<a name="l03671"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga207a9eedfc1b244c393be3c34ea60a15">03671</a> <span class="preprocessor">#define  FSMC_BTR4_BUSTURN                   ((uint32_t)0x000F0000)        </span>
<a name="l03672"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga4dec1fa50fca6639be7179d445aacfe4">03672</a> <span class="preprocessor">#define  FSMC_BTR4_BUSTURN_0                 ((uint32_t)0x00010000)        </span>
<a name="l03673"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gab1db211382068251dc5cfe44a175e639">03673</a> <span class="preprocessor">#define  FSMC_BTR4_BUSTURN_1                 ((uint32_t)0x00020000)        </span>
<a name="l03674"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaa5391a8c2a1e8cd6abb81fa5b2836464">03674</a> <span class="preprocessor">#define  FSMC_BTR4_BUSTURN_2                 ((uint32_t)0x00040000)        </span>
<a name="l03675"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gadbfd74790a1e25339151de440e3a93e5">03675</a> <span class="preprocessor">#define  FSMC_BTR4_BUSTURN_3                 ((uint32_t)0x00080000)        </span>
<a name="l03677"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga7ac39964e3792653e454538407b11504">03677</a> <span class="preprocessor">#define  FSMC_BTR4_CLKDIV                    ((uint32_t)0x00F00000)        </span>
<a name="l03678"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaacee394c98ac568fe1d6df61c887ed53">03678</a> <span class="preprocessor">#define  FSMC_BTR4_CLKDIV_0                  ((uint32_t)0x00100000)        </span>
<a name="l03679"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga9c7cd1d1a4954d494bd107400925f86f">03679</a> <span class="preprocessor">#define  FSMC_BTR4_CLKDIV_1                  ((uint32_t)0x00200000)        </span>
<a name="l03680"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga93b0ab3235ffacca24e6b285460c5dd3">03680</a> <span class="preprocessor">#define  FSMC_BTR4_CLKDIV_2                  ((uint32_t)0x00400000)        </span>
<a name="l03681"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga931463443390c5a706303e87a538d1ce">03681</a> <span class="preprocessor">#define  FSMC_BTR4_CLKDIV_3                  ((uint32_t)0x00800000)        </span>
<a name="l03683"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaa53cb7c299e794915d3aba803374adca">03683</a> <span class="preprocessor">#define  FSMC_BTR4_DATLAT                    ((uint32_t)0x0F000000)        </span>
<a name="l03684"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gad2315f17d1cd7dd9da1b0ee2f7e4ea29">03684</a> <span class="preprocessor">#define  FSMC_BTR4_DATLAT_0                  ((uint32_t)0x01000000)        </span>
<a name="l03685"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga808a7d758e6ca75c573d08ee92228745">03685</a> <span class="preprocessor">#define  FSMC_BTR4_DATLAT_1                  ((uint32_t)0x02000000)        </span>
<a name="l03686"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gac376a62779292d64bfac24d572b743e9">03686</a> <span class="preprocessor">#define  FSMC_BTR4_DATLAT_2                  ((uint32_t)0x04000000)        </span>
<a name="l03687"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gadfc558894dcb263451dbac13f48fffe1">03687</a> <span class="preprocessor">#define  FSMC_BTR4_DATLAT_3                  ((uint32_t)0x08000000)        </span>
<a name="l03689"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gabbf731d99007936586f9e15f17c3c771">03689</a> <span class="preprocessor">#define  FSMC_BTR4_ACCMOD                    ((uint32_t)0x30000000)        </span>
<a name="l03690"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga8e69759ab89b16573bafd2f6ded95bfb">03690</a> <span class="preprocessor">#define  FSMC_BTR4_ACCMOD_0                  ((uint32_t)0x10000000)        </span>
<a name="l03691"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga3e486b11f6af0f566f8843a5c95c6a6c">03691</a> <span class="preprocessor">#define  FSMC_BTR4_ACCMOD_1                  ((uint32_t)0x20000000)        </span>
<a name="l03693"></a>03693 <span class="preprocessor"></span><span class="comment">/******************  Bit definition for FSMC_BWTR1 register  ******************/</span>
<a name="l03694"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga4aa5ee153cb4bf79f0d4ae2c47f365c4">03694</a> <span class="preprocessor">#define  FSMC_BWTR1_ADDSET                   ((uint32_t)0x0000000F)        </span>
<a name="l03695"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaacb80aeedb6d0d9cb09e7b4d3ff8b541">03695</a> <span class="preprocessor">#define  FSMC_BWTR1_ADDSET_0                 ((uint32_t)0x00000001)        </span>
<a name="l03696"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga20dbbdff1e2f1d57727dabbc4b03c840">03696</a> <span class="preprocessor">#define  FSMC_BWTR1_ADDSET_1                 ((uint32_t)0x00000002)        </span>
<a name="l03697"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga411f0d164c26dda8132ff22856757470">03697</a> <span class="preprocessor">#define  FSMC_BWTR1_ADDSET_2                 ((uint32_t)0x00000004)        </span>
<a name="l03698"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga3e2bc67999e8d2b63771fa223ffa8e4d">03698</a> <span class="preprocessor">#define  FSMC_BWTR1_ADDSET_3                 ((uint32_t)0x00000008)        </span>
<a name="l03700"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gafa3d8ff62f87ab6aeb5170dd67de15cf">03700</a> <span class="preprocessor">#define  FSMC_BWTR1_ADDHLD                   ((uint32_t)0x000000F0)        </span>
<a name="l03701"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga1e24880c23375636d7504d42077a400a">03701</a> <span class="preprocessor">#define  FSMC_BWTR1_ADDHLD_0                 ((uint32_t)0x00000010)        </span>
<a name="l03702"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gafb90dec93198b1d3077feb5fe508f004">03702</a> <span class="preprocessor">#define  FSMC_BWTR1_ADDHLD_1                 ((uint32_t)0x00000020)        </span>
<a name="l03703"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga26ef7d6cd5ec547a349462e4f31963b6">03703</a> <span class="preprocessor">#define  FSMC_BWTR1_ADDHLD_2                 ((uint32_t)0x00000040)        </span>
<a name="l03704"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gac4a961ecd844e14a90d1b2f6c5d59196">03704</a> <span class="preprocessor">#define  FSMC_BWTR1_ADDHLD_3                 ((uint32_t)0x00000080)        </span>
<a name="l03706"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaee2641a6f415d03df324667662bd3dcf">03706</a> <span class="preprocessor">#define  FSMC_BWTR1_DATAST                   ((uint32_t)0x0000FF00)        </span>
<a name="l03707"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga162800452847dd98d27a4078370518b2">03707</a> <span class="preprocessor">#define  FSMC_BWTR1_DATAST_0                 ((uint32_t)0x00000100)        </span>
<a name="l03708"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga16476bfbbcb9726c1fbc593d3568a514">03708</a> <span class="preprocessor">#define  FSMC_BWTR1_DATAST_1                 ((uint32_t)0x00000200)        </span>
<a name="l03709"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga623de376d9f5189d73068d0865a5049e">03709</a> <span class="preprocessor">#define  FSMC_BWTR1_DATAST_2                 ((uint32_t)0x00000400)        </span>
<a name="l03710"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gade0627f53e3df25fdaa973db6159bd70">03710</a> <span class="preprocessor">#define  FSMC_BWTR1_DATAST_3                 ((uint32_t)0x00000800)        </span>
<a name="l03712"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gacab3c524b3e47327b24fa560feb93487">03712</a> <span class="preprocessor">#define  FSMC_BWTR1_CLKDIV                   ((uint32_t)0x00F00000)        </span>
<a name="l03713"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaa16b4376e693343cf65ab05808398b7f">03713</a> <span class="preprocessor">#define  FSMC_BWTR1_CLKDIV_0                 ((uint32_t)0x00100000)        </span>
<a name="l03714"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga632860254f0019e87c2e73c872d8d0c3">03714</a> <span class="preprocessor">#define  FSMC_BWTR1_CLKDIV_1                 ((uint32_t)0x00200000)        </span>
<a name="l03715"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga9debedb9d28dc78574eafc829cde91fe">03715</a> <span class="preprocessor">#define  FSMC_BWTR1_CLKDIV_2                 ((uint32_t)0x00400000)        </span>
<a name="l03716"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga67c483e37ed994b71337a0e0777c1290">03716</a> <span class="preprocessor">#define  FSMC_BWTR1_CLKDIV_3                 ((uint32_t)0x00800000)        </span>
<a name="l03718"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga5f05e337758cdb98cfc833e43bd6d674">03718</a> <span class="preprocessor">#define  FSMC_BWTR1_DATLAT                   ((uint32_t)0x0F000000)        </span>
<a name="l03719"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gadd6a7a7678ef3afbbed587cf318d1540">03719</a> <span class="preprocessor">#define  FSMC_BWTR1_DATLAT_0                 ((uint32_t)0x01000000)        </span>
<a name="l03720"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga515ba99da829728fa7128161786c933d">03720</a> <span class="preprocessor">#define  FSMC_BWTR1_DATLAT_1                 ((uint32_t)0x02000000)        </span>
<a name="l03721"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga13d22659082e66df3f0497057cf7dda5">03721</a> <span class="preprocessor">#define  FSMC_BWTR1_DATLAT_2                 ((uint32_t)0x04000000)        </span>
<a name="l03722"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga3af303f1131ff3de0894ec908de252c4">03722</a> <span class="preprocessor">#define  FSMC_BWTR1_DATLAT_3                 ((uint32_t)0x08000000)        </span>
<a name="l03724"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaa676b8e4f48602c27ea8edab61ce5db0">03724</a> <span class="preprocessor">#define  FSMC_BWTR1_ACCMOD                   ((uint32_t)0x30000000)        </span>
<a name="l03725"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gae87cae14e6bb4403b420fc9e4084d6e2">03725</a> <span class="preprocessor">#define  FSMC_BWTR1_ACCMOD_0                 ((uint32_t)0x10000000)        </span>
<a name="l03726"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gac0cddde5db2e0bb09f1c8938afd6ac98">03726</a> <span class="preprocessor">#define  FSMC_BWTR1_ACCMOD_1                 ((uint32_t)0x20000000)        </span>
<a name="l03728"></a>03728 <span class="preprocessor"></span><span class="comment">/******************  Bit definition for FSMC_BWTR2 register  ******************/</span>
<a name="l03729"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga7b6553bd9ad305aa42341e08b1736260">03729</a> <span class="preprocessor">#define  FSMC_BWTR2_ADDSET                   ((uint32_t)0x0000000F)        </span>
<a name="l03730"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga593fe1987e8c6052cdb992e629f1d059">03730</a> <span class="preprocessor">#define  FSMC_BWTR2_ADDSET_0                 ((uint32_t)0x00000001)        </span>
<a name="l03731"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga6dc23a2314a44b6ad9f293716f0c8a11">03731</a> <span class="preprocessor">#define  FSMC_BWTR2_ADDSET_1                 ((uint32_t)0x00000002)        </span>
<a name="l03732"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga1e9c799b36f45cad86a3f98d262baa6d">03732</a> <span class="preprocessor">#define  FSMC_BWTR2_ADDSET_2                 ((uint32_t)0x00000004)        </span>
<a name="l03733"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga95abc246eb528275d894346c0665e930">03733</a> <span class="preprocessor">#define  FSMC_BWTR2_ADDSET_3                 ((uint32_t)0x00000008)        </span>
<a name="l03735"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gae879db1879650f99b1c75635884bda17">03735</a> <span class="preprocessor">#define  FSMC_BWTR2_ADDHLD                   ((uint32_t)0x000000F0)        </span>
<a name="l03736"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaf5826c5d5c544cd59210c071358fb8e9">03736</a> <span class="preprocessor">#define  FSMC_BWTR2_ADDHLD_0                 ((uint32_t)0x00000010)        </span>
<a name="l03737"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga258acf47f7706a1cd0b0a914e63cbe17">03737</a> <span class="preprocessor">#define  FSMC_BWTR2_ADDHLD_1                 ((uint32_t)0x00000020)        </span>
<a name="l03738"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga39f1a9ccc80d1218935936539a000b84">03738</a> <span class="preprocessor">#define  FSMC_BWTR2_ADDHLD_2                 ((uint32_t)0x00000040)        </span>
<a name="l03739"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga81de376a21fc25a7e1c31db341dfcd3f">03739</a> <span class="preprocessor">#define  FSMC_BWTR2_ADDHLD_3                 ((uint32_t)0x00000080)        </span>
<a name="l03741"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gab280652524006fbb3820597112136f14">03741</a> <span class="preprocessor">#define  FSMC_BWTR2_DATAST                   ((uint32_t)0x0000FF00)        </span>
<a name="l03742"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga78a0f0466162848135313296ebf44890">03742</a> <span class="preprocessor">#define  FSMC_BWTR2_DATAST_0                 ((uint32_t)0x00000100)        </span>
<a name="l03743"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga51e43e17e99141c9009c779cc359323a">03743</a> <span class="preprocessor">#define  FSMC_BWTR2_DATAST_1                 ((uint32_t)0x00000200)        </span>
<a name="l03744"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga1f8791c2a33f740f905d45e3754e3353">03744</a> <span class="preprocessor">#define  FSMC_BWTR2_DATAST_2                 ((uint32_t)0x00000400)        </span>
<a name="l03745"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga8a2a5797dd14b5b89581c5fb08872fae">03745</a> <span class="preprocessor">#define  FSMC_BWTR2_DATAST_3                 ((uint32_t)0x00000800)        </span>
<a name="l03747"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaf62bb3c772353b551de22915814115b6">03747</a> <span class="preprocessor">#define  FSMC_BWTR2_CLKDIV                   ((uint32_t)0x00F00000)        </span>
<a name="l03748"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga7d5aaffe4b4c549b247c31dead5585c6">03748</a> <span class="preprocessor">#define  FSMC_BWTR2_CLKDIV_0                 ((uint32_t)0x00100000)        </span>
<a name="l03749"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga6caca8a04c9768a84bcd958656ea8209">03749</a> <span class="preprocessor">#define  FSMC_BWTR2_CLKDIV_1                 ((uint32_t)0x00200000)        </span>
<a name="l03750"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gae608705cf36abaf22e96e9c4c63d4363">03750</a> <span class="preprocessor">#define  FSMC_BWTR2_CLKDIV_2                 ((uint32_t)0x00400000)        </span>
<a name="l03751"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaf3cb607738f2c3aa4dae4990d0754f73">03751</a> <span class="preprocessor">#define  FSMC_BWTR2_CLKDIV_3                 ((uint32_t)0x00800000)        </span>
<a name="l03753"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga7f04b7ebcecadd4b515cac94159ea8d3">03753</a> <span class="preprocessor">#define  FSMC_BWTR2_DATLAT                   ((uint32_t)0x0F000000)        </span>
<a name="l03754"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaac5b453a7316f378f6bf222d5de5b515">03754</a> <span class="preprocessor">#define  FSMC_BWTR2_DATLAT_0                 ((uint32_t)0x01000000)        </span>
<a name="l03755"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga6f5e6363ecbd1c23b1f49a9cfb3301d2">03755</a> <span class="preprocessor">#define  FSMC_BWTR2_DATLAT_1                 ((uint32_t)0x02000000)        </span>
<a name="l03756"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaf028fc0c3148bf9075c09ad311afee65">03756</a> <span class="preprocessor">#define  FSMC_BWTR2_DATLAT_2                 ((uint32_t)0x04000000)        </span>
<a name="l03757"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga9984c8161469dd0922de2d8c4cd9dbe5">03757</a> <span class="preprocessor">#define  FSMC_BWTR2_DATLAT_3                 ((uint32_t)0x08000000)        </span>
<a name="l03759"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga320be3e2e266dc25bd02e10787b2ba0d">03759</a> <span class="preprocessor">#define  FSMC_BWTR2_ACCMOD                   ((uint32_t)0x30000000)        </span>
<a name="l03760"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaabe5419d99a7ad4d4eb761c82077d958">03760</a> <span class="preprocessor">#define  FSMC_BWTR2_ACCMOD_0                 ((uint32_t)0x10000000)        </span>
<a name="l03761"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gab6cdd284ad94abfef0f24fcb813b4558">03761</a> <span class="preprocessor">#define  FSMC_BWTR2_ACCMOD_1                 ((uint32_t)0x20000000)        </span>
<a name="l03763"></a>03763 <span class="preprocessor"></span><span class="comment">/******************  Bit definition for FSMC_BWTR3 register  ******************/</span>
<a name="l03764"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga455ba53d0f18173b0694d71757a084ff">03764</a> <span class="preprocessor">#define  FSMC_BWTR3_ADDSET                   ((uint32_t)0x0000000F)        </span>
<a name="l03765"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga9dddd5ba924b56867c9cb39484ef498d">03765</a> <span class="preprocessor">#define  FSMC_BWTR3_ADDSET_0                 ((uint32_t)0x00000001)        </span>
<a name="l03766"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gacd242d768da1f9ab4304e91e5dabb5a9">03766</a> <span class="preprocessor">#define  FSMC_BWTR3_ADDSET_1                 ((uint32_t)0x00000002)        </span>
<a name="l03767"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaef99967dc66814cf5d732365c40daebb">03767</a> <span class="preprocessor">#define  FSMC_BWTR3_ADDSET_2                 ((uint32_t)0x00000004)        </span>
<a name="l03768"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga471ebb2d47fb951340df6ba22b40a788">03768</a> <span class="preprocessor">#define  FSMC_BWTR3_ADDSET_3                 ((uint32_t)0x00000008)        </span>
<a name="l03770"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gae3d031a0d71677932a68639ba88bd13e">03770</a> <span class="preprocessor">#define  FSMC_BWTR3_ADDHLD                   ((uint32_t)0x000000F0)        </span>
<a name="l03771"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga5b3948c407a5a4be6a21cccad0a8d12d">03771</a> <span class="preprocessor">#define  FSMC_BWTR3_ADDHLD_0                 ((uint32_t)0x00000010)        </span>
<a name="l03772"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaea21d05228f7771c6306726af5da5a4a">03772</a> <span class="preprocessor">#define  FSMC_BWTR3_ADDHLD_1                 ((uint32_t)0x00000020)        </span>
<a name="l03773"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaa574b3a1efe581d195789dcc8bba01f8">03773</a> <span class="preprocessor">#define  FSMC_BWTR3_ADDHLD_2                 ((uint32_t)0x00000040)        </span>
<a name="l03774"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaae8216cf865785468af58dbce0002a7c">03774</a> <span class="preprocessor">#define  FSMC_BWTR3_ADDHLD_3                 ((uint32_t)0x00000080)        </span>
<a name="l03776"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gae93d9fee8a67491918526019b439a00f">03776</a> <span class="preprocessor">#define  FSMC_BWTR3_DATAST                   ((uint32_t)0x0000FF00)        </span>
<a name="l03777"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaf1ec40c6360faeb133cb224a6789bb51">03777</a> <span class="preprocessor">#define  FSMC_BWTR3_DATAST_0                 ((uint32_t)0x00000100)        </span>
<a name="l03778"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gacaf23316e44d731620f0cbde29ae9a93">03778</a> <span class="preprocessor">#define  FSMC_BWTR3_DATAST_1                 ((uint32_t)0x00000200)        </span>
<a name="l03779"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga31686e755ef0f98078d96c08891cf8f4">03779</a> <span class="preprocessor">#define  FSMC_BWTR3_DATAST_2                 ((uint32_t)0x00000400)        </span>
<a name="l03780"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga5a291f74abf021a7fe66ce8afd714c39">03780</a> <span class="preprocessor">#define  FSMC_BWTR3_DATAST_3                 ((uint32_t)0x00000800)        </span>
<a name="l03782"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga5a270daf60bba0a4a9de6607635b0264">03782</a> <span class="preprocessor">#define  FSMC_BWTR3_CLKDIV                   ((uint32_t)0x00F00000)        </span>
<a name="l03783"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gab0e2f5c1eb92f5dba7c2d76b6267805a">03783</a> <span class="preprocessor">#define  FSMC_BWTR3_CLKDIV_0                 ((uint32_t)0x00100000)        </span>
<a name="l03784"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gad909c7569c4740c823bf4b31f93d4edb">03784</a> <span class="preprocessor">#define  FSMC_BWTR3_CLKDIV_1                 ((uint32_t)0x00200000)        </span>
<a name="l03785"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gab17fdae6a3e63acc21280497e0761d15">03785</a> <span class="preprocessor">#define  FSMC_BWTR3_CLKDIV_2                 ((uint32_t)0x00400000)        </span>
<a name="l03786"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga56fbdeda5582325eb5eea0061209adc9">03786</a> <span class="preprocessor">#define  FSMC_BWTR3_CLKDIV_3                 ((uint32_t)0x00800000)        </span>
<a name="l03788"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga05b769f726e31038cfa6bf4897453088">03788</a> <span class="preprocessor">#define  FSMC_BWTR3_DATLAT                   ((uint32_t)0x0F000000)        </span>
<a name="l03789"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga900f347cf4b9debe88252ff1d453098e">03789</a> <span class="preprocessor">#define  FSMC_BWTR3_DATLAT_0                 ((uint32_t)0x01000000)        </span>
<a name="l03790"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gafb44640d0ccf25b8c8ec4b24b3600d26">03790</a> <span class="preprocessor">#define  FSMC_BWTR3_DATLAT_1                 ((uint32_t)0x02000000)        </span>
<a name="l03791"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga4a6405794f28617802ba7bd3586a5f50">03791</a> <span class="preprocessor">#define  FSMC_BWTR3_DATLAT_2                 ((uint32_t)0x04000000)        </span>
<a name="l03792"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga974cf9ed84e54c78ee995b02cc605706">03792</a> <span class="preprocessor">#define  FSMC_BWTR3_DATLAT_3                 ((uint32_t)0x08000000)        </span>
<a name="l03794"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaa32a792c0c93d854a90bfbc36fa1329b">03794</a> <span class="preprocessor">#define  FSMC_BWTR3_ACCMOD                   ((uint32_t)0x30000000)        </span>
<a name="l03795"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga64d4e414ea73b47e07364e1a121af6a4">03795</a> <span class="preprocessor">#define  FSMC_BWTR3_ACCMOD_0                 ((uint32_t)0x10000000)        </span>
<a name="l03796"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gada733b2bda718299345fd0191b25b49f">03796</a> <span class="preprocessor">#define  FSMC_BWTR3_ACCMOD_1                 ((uint32_t)0x20000000)        </span>
<a name="l03798"></a>03798 <span class="preprocessor"></span><span class="comment">/******************  Bit definition for FSMC_BWTR4 register  ******************/</span>
<a name="l03799"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaa8c3c14faf87768beced4e297edc7bfd">03799</a> <span class="preprocessor">#define  FSMC_BWTR4_ADDSET                   ((uint32_t)0x0000000F)        </span>
<a name="l03800"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga65ba73495f6192e409cc00f3e26e27e0">03800</a> <span class="preprocessor">#define  FSMC_BWTR4_ADDSET_0                 ((uint32_t)0x00000001)        </span>
<a name="l03801"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga3cc9fa3c1ceae0724f5005bb1e101775">03801</a> <span class="preprocessor">#define  FSMC_BWTR4_ADDSET_1                 ((uint32_t)0x00000002)        </span>
<a name="l03802"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gad2007941f4869504bfef23edbcc18bfa">03802</a> <span class="preprocessor">#define  FSMC_BWTR4_ADDSET_2                 ((uint32_t)0x00000004)        </span>
<a name="l03803"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gabcde23639f64241d95b02f5b950ef3cc">03803</a> <span class="preprocessor">#define  FSMC_BWTR4_ADDSET_3                 ((uint32_t)0x00000008)        </span>
<a name="l03805"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaafe1198e70d843c883260d354b7ce7b5">03805</a> <span class="preprocessor">#define  FSMC_BWTR4_ADDHLD                   ((uint32_t)0x000000F0)        </span>
<a name="l03806"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gac62786f538820baa3f0f8edb17ef1b74">03806</a> <span class="preprocessor">#define  FSMC_BWTR4_ADDHLD_0                 ((uint32_t)0x00000010)        </span>
<a name="l03807"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaa69aa2d9cafe8f952721c88083c8a94e">03807</a> <span class="preprocessor">#define  FSMC_BWTR4_ADDHLD_1                 ((uint32_t)0x00000020)        </span>
<a name="l03808"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga4c6d991498c385991b461832fb093399">03808</a> <span class="preprocessor">#define  FSMC_BWTR4_ADDHLD_2                 ((uint32_t)0x00000040)        </span>
<a name="l03809"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gac744bdeb5b9ae048b1fa1a07ce9ce9d1">03809</a> <span class="preprocessor">#define  FSMC_BWTR4_ADDHLD_3                 ((uint32_t)0x00000080)        </span>
<a name="l03811"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga6656c89aac87fc226c0e80f8f753abeb">03811</a> <span class="preprocessor">#define  FSMC_BWTR4_DATAST                   ((uint32_t)0x0000FF00)        </span>
<a name="l03812"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga5636aaec144530e1c46e819b62c95f09">03812</a> <span class="preprocessor">#define  FSMC_BWTR4_DATAST_0                 ((uint32_t)0x00000100)        </span>
<a name="l03813"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga19eb9fccff444a00caf75b9d20a143ed">03813</a> <span class="preprocessor">#define  FSMC_BWTR4_DATAST_1                 ((uint32_t)0x00000200)        </span>
<a name="l03814"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaa40f9fa60ddb69fdcdcdface743f2c26">03814</a> <span class="preprocessor">#define  FSMC_BWTR4_DATAST_2                 ((uint32_t)0x00000400)        </span>
<a name="l03815"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gafa173c5ff9a7d316cd67897f8e36dbf5">03815</a> <span class="preprocessor">#define  FSMC_BWTR4_DATAST_3                 ((uint32_t)0x00000800)        </span>
<a name="l03817"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gace3c57c780586c96ef5756d642c3bd01">03817</a> <span class="preprocessor">#define  FSMC_BWTR4_CLKDIV                   ((uint32_t)0x00F00000)        </span>
<a name="l03818"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga8eae837a65cdce995c6fc43afd196e76">03818</a> <span class="preprocessor">#define  FSMC_BWTR4_CLKDIV_0                 ((uint32_t)0x00100000)        </span>
<a name="l03819"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga265d50716e1b6ae2395f0da696b4d12a">03819</a> <span class="preprocessor">#define  FSMC_BWTR4_CLKDIV_1                 ((uint32_t)0x00200000)        </span>
<a name="l03820"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga095f121a1739bcc61e40f2fbb5e8b6a0">03820</a> <span class="preprocessor">#define  FSMC_BWTR4_CLKDIV_2                 ((uint32_t)0x00400000)        </span>
<a name="l03821"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga11d5deb7f2aed21baeb4df3015440bc2">03821</a> <span class="preprocessor">#define  FSMC_BWTR4_CLKDIV_3                 ((uint32_t)0x00800000)        </span>
<a name="l03823"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaa6f7e16866ecede5f4258c05d95f571b">03823</a> <span class="preprocessor">#define  FSMC_BWTR4_DATLAT                   ((uint32_t)0x0F000000)        </span>
<a name="l03824"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga9841723700d2b9611be2e7a7b0f19c33">03824</a> <span class="preprocessor">#define  FSMC_BWTR4_DATLAT_0                 ((uint32_t)0x01000000)        </span>
<a name="l03825"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gad628c523ceee80e41c02dd4502baee2c">03825</a> <span class="preprocessor">#define  FSMC_BWTR4_DATLAT_1                 ((uint32_t)0x02000000)        </span>
<a name="l03826"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gafee2951c0bea4329727767db1bb96a4f">03826</a> <span class="preprocessor">#define  FSMC_BWTR4_DATLAT_2                 ((uint32_t)0x04000000)        </span>
<a name="l03827"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga1020e605f8a52d9fd857d3b91d23bf7a">03827</a> <span class="preprocessor">#define  FSMC_BWTR4_DATLAT_3                 ((uint32_t)0x08000000)        </span>
<a name="l03829"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga1d13f46a945d5daf6ec339781d3926a9">03829</a> <span class="preprocessor">#define  FSMC_BWTR4_ACCMOD                   ((uint32_t)0x30000000)        </span>
<a name="l03830"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga5e30f51c68b4ac4f9efee2cd5a45943c">03830</a> <span class="preprocessor">#define  FSMC_BWTR4_ACCMOD_0                 ((uint32_t)0x10000000)        </span>
<a name="l03831"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaf7ba26fb09f035addbe1e4c3b0d093c9">03831</a> <span class="preprocessor">#define  FSMC_BWTR4_ACCMOD_1                 ((uint32_t)0x20000000)        </span>
<a name="l03833"></a>03833 <span class="preprocessor"></span><span class="comment">/******************  Bit definition for FSMC_PCR2 register  *******************/</span>
<a name="l03834"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga26f3ae80c9bbede6929c20004804476d">03834</a> <span class="preprocessor">#define  FSMC_PCR2_PWAITEN                   ((uint32_t)0x00000002)        </span>
<a name="l03835"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga2a2bfd8de14f8c726439ba8f494b38a1">03835</a> <span class="preprocessor">#define  FSMC_PCR2_PBKEN                     ((uint32_t)0x00000004)        </span>
<a name="l03836"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga175ab8f61bbc0bb5692fb62691db1ce3">03836</a> <span class="preprocessor">#define  FSMC_PCR2_PTYP                      ((uint32_t)0x00000008)        </span>
<a name="l03838"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga656155275dc1c2f690687d07717e017a">03838</a> <span class="preprocessor">#define  FSMC_PCR2_PWID                      ((uint32_t)0x00000030)        </span>
<a name="l03839"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gae36f67be67a473c318fa937246c6de17">03839</a> <span class="preprocessor">#define  FSMC_PCR2_PWID_0                    ((uint32_t)0x00000010)        </span>
<a name="l03840"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga6180d3899a37f7e518b1e4b8bf935baa">03840</a> <span class="preprocessor">#define  FSMC_PCR2_PWID_1                    ((uint32_t)0x00000020)        </span>
<a name="l03842"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gafa528d578aec8bc0f77a2550d4e48438">03842</a> <span class="preprocessor">#define  FSMC_PCR2_ECCEN                     ((uint32_t)0x00000040)        </span>
<a name="l03844"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaa4f2c6c5ed8cd459a0822c35ea9e6800">03844</a> <span class="preprocessor">#define  FSMC_PCR2_TCLR                      ((uint32_t)0x00001E00)        </span>
<a name="l03845"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga1edc7eec1b5a76a851175e5a7caa6c5c">03845</a> <span class="preprocessor">#define  FSMC_PCR2_TCLR_0                    ((uint32_t)0x00000200)        </span>
<a name="l03846"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaf8baae9949bd0f294a698721da24808f">03846</a> <span class="preprocessor">#define  FSMC_PCR2_TCLR_1                    ((uint32_t)0x00000400)        </span>
<a name="l03847"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga01ba36d067efffcfe5ecea3af1411675">03847</a> <span class="preprocessor">#define  FSMC_PCR2_TCLR_2                    ((uint32_t)0x00000800)        </span>
<a name="l03848"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga4999b81ed8783cca5f3b25500183ff9a">03848</a> <span class="preprocessor">#define  FSMC_PCR2_TCLR_3                    ((uint32_t)0x00001000)        </span>
<a name="l03850"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaa6513b62e23afdbadc4b25697378a0f2">03850</a> <span class="preprocessor">#define  FSMC_PCR2_TAR                       ((uint32_t)0x0001E000)        </span>
<a name="l03851"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gacd7e456c24f5978e8cb1078c633f0d23">03851</a> <span class="preprocessor">#define  FSMC_PCR2_TAR_0                     ((uint32_t)0x00002000)        </span>
<a name="l03852"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga8f0b2191750ab21af10f009e1a97ca13">03852</a> <span class="preprocessor">#define  FSMC_PCR2_TAR_1                     ((uint32_t)0x00004000)        </span>
<a name="l03853"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga3de27b9eb559156b7ed87407206b7a17">03853</a> <span class="preprocessor">#define  FSMC_PCR2_TAR_2                     ((uint32_t)0x00008000)        </span>
<a name="l03854"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga1c70f852bb8809e8ea4800a7dd616266">03854</a> <span class="preprocessor">#define  FSMC_PCR2_TAR_3                     ((uint32_t)0x00010000)        </span>
<a name="l03856"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaf2adbc7b4149193452b69bc55a968cd1">03856</a> <span class="preprocessor">#define  FSMC_PCR2_ECCPS                     ((uint32_t)0x000E0000)        </span>
<a name="l03857"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gae0e06e76b0dd7cc1f6b765b4c3ecfacb">03857</a> <span class="preprocessor">#define  FSMC_PCR2_ECCPS_0                   ((uint32_t)0x00020000)        </span>
<a name="l03858"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga8b947299d05921085b531f12db860f41">03858</a> <span class="preprocessor">#define  FSMC_PCR2_ECCPS_1                   ((uint32_t)0x00040000)        </span>
<a name="l03859"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga199db72eae8707aba0b22ff18bd8bcd0">03859</a> <span class="preprocessor">#define  FSMC_PCR2_ECCPS_2                   ((uint32_t)0x00080000)        </span>
<a name="l03861"></a>03861 <span class="preprocessor"></span><span class="comment">/******************  Bit definition for FSMC_PCR3 register  *******************/</span>
<a name="l03862"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaae3f15324eb8692ddf3f294f358b1d8c">03862</a> <span class="preprocessor">#define  FSMC_PCR3_PWAITEN                   ((uint32_t)0x00000002)        </span>
<a name="l03863"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaac1334587ebb2f313078aab2c2f76cf7">03863</a> <span class="preprocessor">#define  FSMC_PCR3_PBKEN                     ((uint32_t)0x00000004)        </span>
<a name="l03864"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gade562589d0572ba223d2f6df265fe5b8">03864</a> <span class="preprocessor">#define  FSMC_PCR3_PTYP                      ((uint32_t)0x00000008)        </span>
<a name="l03866"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gac6f9b4e4449f105aa9bd3630f0466b9f">03866</a> <span class="preprocessor">#define  FSMC_PCR3_PWID                      ((uint32_t)0x00000030)        </span>
<a name="l03867"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gae07191f4d5e3c3ec38b271b30cd1ee07">03867</a> <span class="preprocessor">#define  FSMC_PCR3_PWID_0                    ((uint32_t)0x00000010)        </span>
<a name="l03868"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaa8819a742324c0523f3dc6b8959bcdd5">03868</a> <span class="preprocessor">#define  FSMC_PCR3_PWID_1                    ((uint32_t)0x00000020)        </span>
<a name="l03870"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga723c4c8c3b97cd1ce18c3b5c888e5b4e">03870</a> <span class="preprocessor">#define  FSMC_PCR3_ECCEN                     ((uint32_t)0x00000040)        </span>
<a name="l03872"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga478e4371d8baf2a0b2675b3113edb071">03872</a> <span class="preprocessor">#define  FSMC_PCR3_TCLR                      ((uint32_t)0x00001E00)        </span>
<a name="l03873"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gadedb0d10b5b53656dc152b9264faffbd">03873</a> <span class="preprocessor">#define  FSMC_PCR3_TCLR_0                    ((uint32_t)0x00000200)        </span>
<a name="l03874"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gab5536285f03b1732aed999d20c0e25aa">03874</a> <span class="preprocessor">#define  FSMC_PCR3_TCLR_1                    ((uint32_t)0x00000400)        </span>
<a name="l03875"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gae7d40ba9c0f0da58948ee2cc546b634c">03875</a> <span class="preprocessor">#define  FSMC_PCR3_TCLR_2                    ((uint32_t)0x00000800)        </span>
<a name="l03876"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga63f96a640afa85d7521b05458f590a19">03876</a> <span class="preprocessor">#define  FSMC_PCR3_TCLR_3                    ((uint32_t)0x00001000)        </span>
<a name="l03878"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga199c4b0e690f0da0de46e372183da642">03878</a> <span class="preprocessor">#define  FSMC_PCR3_TAR                       ((uint32_t)0x0001E000)        </span>
<a name="l03879"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gada0f17bcc683a5a6249348a63004e225">03879</a> <span class="preprocessor">#define  FSMC_PCR3_TAR_0                     ((uint32_t)0x00002000)        </span>
<a name="l03880"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gad4afb373f6f1cb1bedd653d8ea1dca78">03880</a> <span class="preprocessor">#define  FSMC_PCR3_TAR_1                     ((uint32_t)0x00004000)        </span>
<a name="l03881"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga597698c6059f70f61310456e83353738">03881</a> <span class="preprocessor">#define  FSMC_PCR3_TAR_2                     ((uint32_t)0x00008000)        </span>
<a name="l03882"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga4bd7aaf7ffcad9f4477ac4f2927a0912">03882</a> <span class="preprocessor">#define  FSMC_PCR3_TAR_3                     ((uint32_t)0x00010000)        </span>
<a name="l03884"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaf8d92853ca6f97f72682c2f53f686998">03884</a> <span class="preprocessor">#define  FSMC_PCR3_ECCPS                     ((uint32_t)0x000E0000)        </span>
<a name="l03885"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga506daa911151e1b9de3ed2b5030d1a5a">03885</a> <span class="preprocessor">#define  FSMC_PCR3_ECCPS_0                   ((uint32_t)0x00020000)        </span>
<a name="l03886"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga6403c557bd93b5297fa7fbbf8dc49cc9">03886</a> <span class="preprocessor">#define  FSMC_PCR3_ECCPS_1                   ((uint32_t)0x00040000)        </span>
<a name="l03887"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaf041e921fb9af07e9c709d79bbfaec89">03887</a> <span class="preprocessor">#define  FSMC_PCR3_ECCPS_2                   ((uint32_t)0x00080000)        </span>
<a name="l03889"></a>03889 <span class="preprocessor"></span><span class="comment">/******************  Bit definition for FSMC_PCR4 register  *******************/</span>
<a name="l03890"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gab07ce7c785eb296a615b2c50415de21b">03890</a> <span class="preprocessor">#define  FSMC_PCR4_PWAITEN                   ((uint32_t)0x00000002)        </span>
<a name="l03891"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga2f4a72bae5da27f8da23c13a54fe9622">03891</a> <span class="preprocessor">#define  FSMC_PCR4_PBKEN                     ((uint32_t)0x00000004)        </span>
<a name="l03892"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gabe2d6f4e9bdef35436d521ebbdca5e40">03892</a> <span class="preprocessor">#define  FSMC_PCR4_PTYP                      ((uint32_t)0x00000008)        </span>
<a name="l03894"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga9486b2b7346570ecc5715f1d551c168a">03894</a> <span class="preprocessor">#define  FSMC_PCR4_PWID                      ((uint32_t)0x00000030)        </span>
<a name="l03895"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga0995cb320e6293ea435df275ce67359f">03895</a> <span class="preprocessor">#define  FSMC_PCR4_PWID_0                    ((uint32_t)0x00000010)        </span>
<a name="l03896"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga8b6be32b3844a299a2c92089e81e27e9">03896</a> <span class="preprocessor">#define  FSMC_PCR4_PWID_1                    ((uint32_t)0x00000020)        </span>
<a name="l03898"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga646509f8bebb0d662c730ed4cabe741f">03898</a> <span class="preprocessor">#define  FSMC_PCR4_ECCEN                     ((uint32_t)0x00000040)        </span>
<a name="l03900"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga7c7164974019263cacbc7dda2fc14126">03900</a> <span class="preprocessor">#define  FSMC_PCR4_TCLR                      ((uint32_t)0x00001E00)        </span>
<a name="l03901"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga0dd78ad0c755190a69b37ebac75a11dd">03901</a> <span class="preprocessor">#define  FSMC_PCR4_TCLR_0                    ((uint32_t)0x00000200)        </span>
<a name="l03902"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaf0ea2e2287999d3c7d6583aab492514d">03902</a> <span class="preprocessor">#define  FSMC_PCR4_TCLR_1                    ((uint32_t)0x00000400)        </span>
<a name="l03903"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga34dd56ee892fc187e105e4d820ce3b9a">03903</a> <span class="preprocessor">#define  FSMC_PCR4_TCLR_2                    ((uint32_t)0x00000800)        </span>
<a name="l03904"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga0eb8dc60a469cfa96b3b3b7fad25ac92">03904</a> <span class="preprocessor">#define  FSMC_PCR4_TCLR_3                    ((uint32_t)0x00001000)        </span>
<a name="l03906"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga0c583f305906f19b15ce3dc177fa21bd">03906</a> <span class="preprocessor">#define  FSMC_PCR4_TAR                       ((uint32_t)0x0001E000)        </span>
<a name="l03907"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga62fe4ede4c658b788596e8ea6f325c9f">03907</a> <span class="preprocessor">#define  FSMC_PCR4_TAR_0                     ((uint32_t)0x00002000)        </span>
<a name="l03908"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga2a9958cbf815ac97c3500a46aaf573f5">03908</a> <span class="preprocessor">#define  FSMC_PCR4_TAR_1                     ((uint32_t)0x00004000)        </span>
<a name="l03909"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga669e16ecd48c92f65bd66f2da63fe53f">03909</a> <span class="preprocessor">#define  FSMC_PCR4_TAR_2                     ((uint32_t)0x00008000)        </span>
<a name="l03910"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gad298ef64d36721696517ed0d4ac12d32">03910</a> <span class="preprocessor">#define  FSMC_PCR4_TAR_3                     ((uint32_t)0x00010000)        </span>
<a name="l03912"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga2308baba97f307b8beb6239702471038">03912</a> <span class="preprocessor">#define  FSMC_PCR4_ECCPS                     ((uint32_t)0x000E0000)        </span>
<a name="l03913"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga76514698225c0734c1e9be46b6dbd298">03913</a> <span class="preprocessor">#define  FSMC_PCR4_ECCPS_0                   ((uint32_t)0x00020000)        </span>
<a name="l03914"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga1c43076003bbf01f95765125e19ab94d">03914</a> <span class="preprocessor">#define  FSMC_PCR4_ECCPS_1                   ((uint32_t)0x00040000)        </span>
<a name="l03915"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gac4ba96304e6618d4eb7672cdc3bd8f01">03915</a> <span class="preprocessor">#define  FSMC_PCR4_ECCPS_2                   ((uint32_t)0x00080000)        </span>
<a name="l03917"></a>03917 <span class="preprocessor"></span><span class="comment">/*******************  Bit definition for FSMC_SR2 register  *******************/</span>
<a name="l03918"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga19f1b90b2da89b68aa754d0a89d60de9">03918</a> <span class="preprocessor">#define  FSMC_SR2_IRS                        ((uint8_t)0x01)               </span>
<a name="l03919"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga664d6e1440c12e76dfa34f716af85ed1">03919</a> <span class="preprocessor">#define  FSMC_SR2_ILS                        ((uint8_t)0x02)               </span>
<a name="l03920"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gad6492ad6afe175283d07de38978936dc">03920</a> <span class="preprocessor">#define  FSMC_SR2_IFS                        ((uint8_t)0x04)               </span>
<a name="l03921"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga3216bd665a118239e6ef0b58ec5e8a8e">03921</a> <span class="preprocessor">#define  FSMC_SR2_IREN                       ((uint8_t)0x08)               </span>
<a name="l03922"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga1e9df0edd35d0ad6a35ff3a3b045b47c">03922</a> <span class="preprocessor">#define  FSMC_SR2_ILEN                       ((uint8_t)0x10)               </span>
<a name="l03923"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga755c088c58b27f79108675f56ea9d196">03923</a> <span class="preprocessor">#define  FSMC_SR2_IFEN                       ((uint8_t)0x20)               </span>
<a name="l03924"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga6ae2e544a4a515303f49815cdbd5ebbb">03924</a> <span class="preprocessor">#define  FSMC_SR2_FEMPT                      ((uint8_t)0x40)               </span>
<a name="l03926"></a>03926 <span class="preprocessor"></span><span class="comment">/*******************  Bit definition for FSMC_SR3 register  *******************/</span>
<a name="l03927"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gad929e4a8c1fdb49ee6f690121336afea">03927</a> <span class="preprocessor">#define  FSMC_SR3_IRS                        ((uint8_t)0x01)               </span>
<a name="l03928"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga9803b4ab5b8cce213a80abc11c751d21">03928</a> <span class="preprocessor">#define  FSMC_SR3_ILS                        ((uint8_t)0x02)               </span>
<a name="l03929"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gafadff6b6f9e6430ada2f56bc9921dd7d">03929</a> <span class="preprocessor">#define  FSMC_SR3_IFS                        ((uint8_t)0x04)               </span>
<a name="l03930"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga12baad15533ecbc57db95ea4939bc782">03930</a> <span class="preprocessor">#define  FSMC_SR3_IREN                       ((uint8_t)0x08)               </span>
<a name="l03931"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga86ac8f1f9f99c81a26fb54b597b57f12">03931</a> <span class="preprocessor">#define  FSMC_SR3_ILEN                       ((uint8_t)0x10)               </span>
<a name="l03932"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaa7355e5368013759dbfabfec8b609ca8">03932</a> <span class="preprocessor">#define  FSMC_SR3_IFEN                       ((uint8_t)0x20)               </span>
<a name="l03933"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga230562cf231dc79cd9354933b39ae7de">03933</a> <span class="preprocessor">#define  FSMC_SR3_FEMPT                      ((uint8_t)0x40)               </span>
<a name="l03935"></a>03935 <span class="preprocessor"></span><span class="comment">/*******************  Bit definition for FSMC_SR4 register  *******************/</span>
<a name="l03936"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga163f7143d51b516af0d46b142222957f">03936</a> <span class="preprocessor">#define  FSMC_SR4_IRS                        ((uint8_t)0x01)               </span>
<a name="l03937"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga0e19feccd1553911d08be673c4af72ad">03937</a> <span class="preprocessor">#define  FSMC_SR4_ILS                        ((uint8_t)0x02)               </span>
<a name="l03938"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaf1e7d71b32a0b70d772fbdc85f7053fc">03938</a> <span class="preprocessor">#define  FSMC_SR4_IFS                        ((uint8_t)0x04)               </span>
<a name="l03939"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga6f5f17d22e07bb6674cbd68740b9708a">03939</a> <span class="preprocessor">#define  FSMC_SR4_IREN                       ((uint8_t)0x08)               </span>
<a name="l03940"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gac9b8d7c7b68723a4ef01843d547d95bc">03940</a> <span class="preprocessor">#define  FSMC_SR4_ILEN                       ((uint8_t)0x10)               </span>
<a name="l03941"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaf97394e42be634cb441204f6bfffb504">03941</a> <span class="preprocessor">#define  FSMC_SR4_IFEN                       ((uint8_t)0x20)               </span>
<a name="l03942"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaae7081cdf26e75bccfac1b6a29c04124">03942</a> <span class="preprocessor">#define  FSMC_SR4_FEMPT                      ((uint8_t)0x40)               </span>
<a name="l03944"></a>03944 <span class="preprocessor"></span><span class="comment">/******************  Bit definition for FSMC_PMEM2 register  ******************/</span>
<a name="l03945"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga50a34195ddb7ab7aebc2acac39b27536">03945</a> <span class="preprocessor">#define  FSMC_PMEM2_MEMSET2                  ((uint32_t)0x000000FF)        </span>
<a name="l03946"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga529858550113070878ce680da0a6bf7d">03946</a> <span class="preprocessor">#define  FSMC_PMEM2_MEMSET2_0                ((uint32_t)0x00000001)        </span>
<a name="l03947"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga28517c1f5aeded21b3f0326247b0bbe1">03947</a> <span class="preprocessor">#define  FSMC_PMEM2_MEMSET2_1                ((uint32_t)0x00000002)        </span>
<a name="l03948"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga1f59339df091ad8a00d75c32b335b711">03948</a> <span class="preprocessor">#define  FSMC_PMEM2_MEMSET2_2                ((uint32_t)0x00000004)        </span>
<a name="l03949"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga7715c089272c9709e8f94590b46be609">03949</a> <span class="preprocessor">#define  FSMC_PMEM2_MEMSET2_3                ((uint32_t)0x00000008)        </span>
<a name="l03950"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga31a0e44106c1ec87375054be15b1cb84">03950</a> <span class="preprocessor">#define  FSMC_PMEM2_MEMSET2_4                ((uint32_t)0x00000010)        </span>
<a name="l03951"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga221edf50060c5dad91de3c0b877fdbfc">03951</a> <span class="preprocessor">#define  FSMC_PMEM2_MEMSET2_5                ((uint32_t)0x00000020)        </span>
<a name="l03952"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga5dc6beefe3ea22a84dbc44fd30843778">03952</a> <span class="preprocessor">#define  FSMC_PMEM2_MEMSET2_6                ((uint32_t)0x00000040)        </span>
<a name="l03953"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gae14181cbd85100c2b3b104525c42ee6c">03953</a> <span class="preprocessor">#define  FSMC_PMEM2_MEMSET2_7                ((uint32_t)0x00000080)        </span>
<a name="l03955"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga7affee760cfe5d04a58bda9cd7fc5f72">03955</a> <span class="preprocessor">#define  FSMC_PMEM2_MEMWAIT2                 ((uint32_t)0x0000FF00)        </span>
<a name="l03956"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga7ee1c7f3347678dff204e6ac8c6eaf4f">03956</a> <span class="preprocessor">#define  FSMC_PMEM2_MEMWAIT2_0               ((uint32_t)0x00000100)        </span>
<a name="l03957"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga56de464fa3f895e75f0ec2ff3f9e1e1e">03957</a> <span class="preprocessor">#define  FSMC_PMEM2_MEMWAIT2_1               ((uint32_t)0x00000200)        </span>
<a name="l03958"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga922a823292054746923fb13b8f4c1b5c">03958</a> <span class="preprocessor">#define  FSMC_PMEM2_MEMWAIT2_2               ((uint32_t)0x00000400)        </span>
<a name="l03959"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga44f9c0141f457b0ef0ff42c1645d7337">03959</a> <span class="preprocessor">#define  FSMC_PMEM2_MEMWAIT2_3               ((uint32_t)0x00000800)        </span>
<a name="l03960"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga8d15645ffe422f3e35cc03efd93361cb">03960</a> <span class="preprocessor">#define  FSMC_PMEM2_MEMWAIT2_4               ((uint32_t)0x00001000)        </span>
<a name="l03961"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga640d5866b22b11924b7e4c9bfc608624">03961</a> <span class="preprocessor">#define  FSMC_PMEM2_MEMWAIT2_5               ((uint32_t)0x00002000)        </span>
<a name="l03962"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga51d69f501306eae03db719cb52065b3c">03962</a> <span class="preprocessor">#define  FSMC_PMEM2_MEMWAIT2_6               ((uint32_t)0x00004000)        </span>
<a name="l03963"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga127b0e01d15f1007cfa67247a99da26f">03963</a> <span class="preprocessor">#define  FSMC_PMEM2_MEMWAIT2_7               ((uint32_t)0x00008000)        </span>
<a name="l03965"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaad2c79ef9df8b619e93c15b506f4fd7d">03965</a> <span class="preprocessor">#define  FSMC_PMEM2_MEMHOLD2                 ((uint32_t)0x00FF0000)        </span>
<a name="l03966"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gadd16a720c69fcac1f6b798cf6f9bbb7e">03966</a> <span class="preprocessor">#define  FSMC_PMEM2_MEMHOLD2_0               ((uint32_t)0x00010000)        </span>
<a name="l03967"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga4630e2bdb842914d0f7b53d4ed610122">03967</a> <span class="preprocessor">#define  FSMC_PMEM2_MEMHOLD2_1               ((uint32_t)0x00020000)        </span>
<a name="l03968"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gacf699fd414971d0c52159c21652f5e58">03968</a> <span class="preprocessor">#define  FSMC_PMEM2_MEMHOLD2_2               ((uint32_t)0x00040000)        </span>
<a name="l03969"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gad3e1f50389b82f8737a12ef6d1683c4f">03969</a> <span class="preprocessor">#define  FSMC_PMEM2_MEMHOLD2_3               ((uint32_t)0x00080000)        </span>
<a name="l03970"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga00c7b1a8cbcbcbcc0495ebd7c877ca9e">03970</a> <span class="preprocessor">#define  FSMC_PMEM2_MEMHOLD2_4               ((uint32_t)0x00100000)        </span>
<a name="l03971"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga9cd7c5637824522c2bd0f2cd165ca218">03971</a> <span class="preprocessor">#define  FSMC_PMEM2_MEMHOLD2_5               ((uint32_t)0x00200000)        </span>
<a name="l03972"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga52ee3806d174025ab98d6c9148f17ae2">03972</a> <span class="preprocessor">#define  FSMC_PMEM2_MEMHOLD2_6               ((uint32_t)0x00400000)        </span>
<a name="l03973"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gad1afae5788b827aebc3df92c74754b38">03973</a> <span class="preprocessor">#define  FSMC_PMEM2_MEMHOLD2_7               ((uint32_t)0x00800000)        </span>
<a name="l03975"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga8a7783e155a688bf79e68ebf570421c4">03975</a> <span class="preprocessor">#define  FSMC_PMEM2_MEMHIZ2                  ((uint32_t)0xFF000000)        </span>
<a name="l03976"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga8bb51ecefa94c1ab3b91c7a14705b8c8">03976</a> <span class="preprocessor">#define  FSMC_PMEM2_MEMHIZ2_0                ((uint32_t)0x01000000)        </span>
<a name="l03977"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga4c0d8bf861d9918763b7391d4ad287b0">03977</a> <span class="preprocessor">#define  FSMC_PMEM2_MEMHIZ2_1                ((uint32_t)0x02000000)        </span>
<a name="l03978"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaebd6a4457fa0ac4f1b98fdc58bef9999">03978</a> <span class="preprocessor">#define  FSMC_PMEM2_MEMHIZ2_2                ((uint32_t)0x04000000)        </span>
<a name="l03979"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaded9a6b1b516fa2595988c84c5465f9b">03979</a> <span class="preprocessor">#define  FSMC_PMEM2_MEMHIZ2_3                ((uint32_t)0x08000000)        </span>
<a name="l03980"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gad9b1831fb25422c7a126a7d029223394">03980</a> <span class="preprocessor">#define  FSMC_PMEM2_MEMHIZ2_4                ((uint32_t)0x10000000)        </span>
<a name="l03981"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gae828a4dde56e15f78ab156feeb329af9">03981</a> <span class="preprocessor">#define  FSMC_PMEM2_MEMHIZ2_5                ((uint32_t)0x20000000)        </span>
<a name="l03982"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gacf5464a2e8aeec6eb06c58283168ef97">03982</a> <span class="preprocessor">#define  FSMC_PMEM2_MEMHIZ2_6                ((uint32_t)0x40000000)        </span>
<a name="l03983"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga3c5ca1880a516478e1b8f1142066c004">03983</a> <span class="preprocessor">#define  FSMC_PMEM2_MEMHIZ2_7                ((uint32_t)0x80000000)        </span>
<a name="l03985"></a>03985 <span class="preprocessor"></span><span class="comment">/******************  Bit definition for FSMC_PMEM3 register  ******************/</span>
<a name="l03986"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaf69ac574f9be3c11ada1e2dc4c3abe4f">03986</a> <span class="preprocessor">#define  FSMC_PMEM3_MEMSET3                  ((uint32_t)0x000000FF)        </span>
<a name="l03987"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaee68bc7ff3e4cf11c2ca826541858c6a">03987</a> <span class="preprocessor">#define  FSMC_PMEM3_MEMSET3_0                ((uint32_t)0x00000001)        </span>
<a name="l03988"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gafa10132605ec4a4be1ab48ee6b36080e">03988</a> <span class="preprocessor">#define  FSMC_PMEM3_MEMSET3_1                ((uint32_t)0x00000002)        </span>
<a name="l03989"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gacd867b06de7c7a49244b6a35570d2cd2">03989</a> <span class="preprocessor">#define  FSMC_PMEM3_MEMSET3_2                ((uint32_t)0x00000004)        </span>
<a name="l03990"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga292a8826723614aa2504a376f4a2e5d5">03990</a> <span class="preprocessor">#define  FSMC_PMEM3_MEMSET3_3                ((uint32_t)0x00000008)        </span>
<a name="l03991"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga98703fee6465ba580b052ef76f2c63f2">03991</a> <span class="preprocessor">#define  FSMC_PMEM3_MEMSET3_4                ((uint32_t)0x00000010)        </span>
<a name="l03992"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaaea28a64fc9a7e0df35826b4ec372361">03992</a> <span class="preprocessor">#define  FSMC_PMEM3_MEMSET3_5                ((uint32_t)0x00000020)        </span>
<a name="l03993"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaea51bbe866574be10bdc1d2d16bb9810">03993</a> <span class="preprocessor">#define  FSMC_PMEM3_MEMSET3_6                ((uint32_t)0x00000040)        </span>
<a name="l03994"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga702eeb8c3930ea564af728cc3bb9044b">03994</a> <span class="preprocessor">#define  FSMC_PMEM3_MEMSET3_7                ((uint32_t)0x00000080)        </span>
<a name="l03996"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga4243cb8b53a10143621872c0d0ed318b">03996</a> <span class="preprocessor">#define  FSMC_PMEM3_MEMWAIT3                 ((uint32_t)0x0000FF00)        </span>
<a name="l03997"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga30d8aad77f584d1c380b6d04d4984ac5">03997</a> <span class="preprocessor">#define  FSMC_PMEM3_MEMWAIT3_0               ((uint32_t)0x00000100)        </span>
<a name="l03998"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaacf4638838e3cf2dfa076ef795596967">03998</a> <span class="preprocessor">#define  FSMC_PMEM3_MEMWAIT3_1               ((uint32_t)0x00000200)        </span>
<a name="l03999"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaa1c65a1027062f3fff04dfdd24c33e64">03999</a> <span class="preprocessor">#define  FSMC_PMEM3_MEMWAIT3_2               ((uint32_t)0x00000400)        </span>
<a name="l04000"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gae23146168ddc8e06defd6e75390dde1d">04000</a> <span class="preprocessor">#define  FSMC_PMEM3_MEMWAIT3_3               ((uint32_t)0x00000800)        </span>
<a name="l04001"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga79640d63c03f94bd4f38859c46bad820">04001</a> <span class="preprocessor">#define  FSMC_PMEM3_MEMWAIT3_4               ((uint32_t)0x00001000)        </span>
<a name="l04002"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga8d36841fa1730bbbc825278cffd623f3">04002</a> <span class="preprocessor">#define  FSMC_PMEM3_MEMWAIT3_5               ((uint32_t)0x00002000)        </span>
<a name="l04003"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga2bd34f98ee23b7a58ac63cd195c00d70">04003</a> <span class="preprocessor">#define  FSMC_PMEM3_MEMWAIT3_6               ((uint32_t)0x00004000)        </span>
<a name="l04004"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga0f485579592b7fdf2e480523ee220418">04004</a> <span class="preprocessor">#define  FSMC_PMEM3_MEMWAIT3_7               ((uint32_t)0x00008000)        </span>
<a name="l04006"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gac8ef1e0f4db1e2792b0939f9058a149b">04006</a> <span class="preprocessor">#define  FSMC_PMEM3_MEMHOLD3                 ((uint32_t)0x00FF0000)        </span>
<a name="l04007"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaa1abd4698bb45c784b23b8d431eb90f1">04007</a> <span class="preprocessor">#define  FSMC_PMEM3_MEMHOLD3_0               ((uint32_t)0x00010000)        </span>
<a name="l04008"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga0a93e71d784bdb1cd115805feac42d6b">04008</a> <span class="preprocessor">#define  FSMC_PMEM3_MEMHOLD3_1               ((uint32_t)0x00020000)        </span>
<a name="l04009"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga20a5443b5236e71b8dfe0620abffbd68">04009</a> <span class="preprocessor">#define  FSMC_PMEM3_MEMHOLD3_2               ((uint32_t)0x00040000)        </span>
<a name="l04010"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga3b330eabb266b26cf6aa93b12bfe7b38">04010</a> <span class="preprocessor">#define  FSMC_PMEM3_MEMHOLD3_3               ((uint32_t)0x00080000)        </span>
<a name="l04011"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gac6d1864268bb87124d127d92e8db54dc">04011</a> <span class="preprocessor">#define  FSMC_PMEM3_MEMHOLD3_4               ((uint32_t)0x00100000)        </span>
<a name="l04012"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga8968569a91c0b5d6c456074ddfc98aa3">04012</a> <span class="preprocessor">#define  FSMC_PMEM3_MEMHOLD3_5               ((uint32_t)0x00200000)        </span>
<a name="l04013"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaf40967f9e19b41e2692b7fe1177b8629">04013</a> <span class="preprocessor">#define  FSMC_PMEM3_MEMHOLD3_6               ((uint32_t)0x00400000)        </span>
<a name="l04014"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaf0da29e1e300e47aebb0bd47bf5f0563">04014</a> <span class="preprocessor">#define  FSMC_PMEM3_MEMHOLD3_7               ((uint32_t)0x00800000)        </span>
<a name="l04016"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga3a77d54c66589f233792d30fc83e7f12">04016</a> <span class="preprocessor">#define  FSMC_PMEM3_MEMHIZ3                  ((uint32_t)0xFF000000)        </span>
<a name="l04017"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga2d8453ab8a7488ff13c681154bfd293c">04017</a> <span class="preprocessor">#define  FSMC_PMEM3_MEMHIZ3_0                ((uint32_t)0x01000000)        </span>
<a name="l04018"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaf023951ad4fd31a691cc26fc3c27ec46">04018</a> <span class="preprocessor">#define  FSMC_PMEM3_MEMHIZ3_1                ((uint32_t)0x02000000)        </span>
<a name="l04019"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaaf8d790834161e0224c878cd8eab190e">04019</a> <span class="preprocessor">#define  FSMC_PMEM3_MEMHIZ3_2                ((uint32_t)0x04000000)        </span>
<a name="l04020"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga26daeb039123824e2de5fdd64cb3a1ff">04020</a> <span class="preprocessor">#define  FSMC_PMEM3_MEMHIZ3_3                ((uint32_t)0x08000000)        </span>
<a name="l04021"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gafd06d96e44933ce665b2af8c2a4098e4">04021</a> <span class="preprocessor">#define  FSMC_PMEM3_MEMHIZ3_4                ((uint32_t)0x10000000)        </span>
<a name="l04022"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaef1254b2e2251da2b30aa297d1d0a1f8">04022</a> <span class="preprocessor">#define  FSMC_PMEM3_MEMHIZ3_5                ((uint32_t)0x20000000)        </span>
<a name="l04023"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaf33c72c5ab0747d587a801835cf1a897">04023</a> <span class="preprocessor">#define  FSMC_PMEM3_MEMHIZ3_6                ((uint32_t)0x40000000)        </span>
<a name="l04024"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaa7304d0d28edd32a70be474e656fbf8e">04024</a> <span class="preprocessor">#define  FSMC_PMEM3_MEMHIZ3_7                ((uint32_t)0x80000000)        </span>
<a name="l04026"></a>04026 <span class="preprocessor"></span><span class="comment">/******************  Bit definition for FSMC_PMEM4 register  ******************/</span>
<a name="l04027"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga3b5cb5385ce2cef772ee4493c25617aa">04027</a> <span class="preprocessor">#define  FSMC_PMEM4_MEMSET4                  ((uint32_t)0x000000FF)        </span>
<a name="l04028"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga6df1a1190522593b71da113c7ea8cfab">04028</a> <span class="preprocessor">#define  FSMC_PMEM4_MEMSET4_0                ((uint32_t)0x00000001)        </span>
<a name="l04029"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga6fa76a9c077f40e973df8fe6903c69c4">04029</a> <span class="preprocessor">#define  FSMC_PMEM4_MEMSET4_1                ((uint32_t)0x00000002)        </span>
<a name="l04030"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga03ddc1ecb61313593976bf70aec06e9f">04030</a> <span class="preprocessor">#define  FSMC_PMEM4_MEMSET4_2                ((uint32_t)0x00000004)        </span>
<a name="l04031"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga4280253a6049c7739c6b70a6d7940998">04031</a> <span class="preprocessor">#define  FSMC_PMEM4_MEMSET4_3                ((uint32_t)0x00000008)        </span>
<a name="l04032"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga153d7b557dc40b797f93bf5593808279">04032</a> <span class="preprocessor">#define  FSMC_PMEM4_MEMSET4_4                ((uint32_t)0x00000010)        </span>
<a name="l04033"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gabc8fc6eadc2e952227c121b6d6114834">04033</a> <span class="preprocessor">#define  FSMC_PMEM4_MEMSET4_5                ((uint32_t)0x00000020)        </span>
<a name="l04034"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaecce633b6da6db82000f1d39dc23bb3b">04034</a> <span class="preprocessor">#define  FSMC_PMEM4_MEMSET4_6                ((uint32_t)0x00000040)        </span>
<a name="l04035"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga04c68698ff6f47551244ae5a26893059">04035</a> <span class="preprocessor">#define  FSMC_PMEM4_MEMSET4_7                ((uint32_t)0x00000080)        </span>
<a name="l04037"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga9673f81abf15ad70d09520db9ddfc58d">04037</a> <span class="preprocessor">#define  FSMC_PMEM4_MEMWAIT4                 ((uint32_t)0x0000FF00)        </span>
<a name="l04038"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga9c88b294c963e5be76da4bf3048af411">04038</a> <span class="preprocessor">#define  FSMC_PMEM4_MEMWAIT4_0               ((uint32_t)0x00000100)        </span>
<a name="l04039"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga24d45891fa0a503d81f68f62f5fd18e5">04039</a> <span class="preprocessor">#define  FSMC_PMEM4_MEMWAIT4_1               ((uint32_t)0x00000200)        </span>
<a name="l04040"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaf1fa35a7722b6339a7cef85b5be2280d">04040</a> <span class="preprocessor">#define  FSMC_PMEM4_MEMWAIT4_2               ((uint32_t)0x00000400)        </span>
<a name="l04041"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga929f7f1066e3f2d69c72126615d06cb0">04041</a> <span class="preprocessor">#define  FSMC_PMEM4_MEMWAIT4_3               ((uint32_t)0x00000800)        </span>
<a name="l04042"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga5282e3d9205f778b67ef00c27beb2918">04042</a> <span class="preprocessor">#define  FSMC_PMEM4_MEMWAIT4_4               ((uint32_t)0x00001000)        </span>
<a name="l04043"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga1eed44a0b89a9f14b08c4ab2578ca5cc">04043</a> <span class="preprocessor">#define  FSMC_PMEM4_MEMWAIT4_5               ((uint32_t)0x00002000)        </span>
<a name="l04044"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gab2429913d3b7993dfda75413f0a72bf4">04044</a> <span class="preprocessor">#define  FSMC_PMEM4_MEMWAIT4_6               ((uint32_t)0x00004000)        </span>
<a name="l04045"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga247eb296ad16d1c7f2ebea0ca85619f9">04045</a> <span class="preprocessor">#define  FSMC_PMEM4_MEMWAIT4_7               ((uint32_t)0x00008000)        </span>
<a name="l04047"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga5028f0c2a642b7faedf602f0b2c0d64c">04047</a> <span class="preprocessor">#define  FSMC_PMEM4_MEMHOLD4                 ((uint32_t)0x00FF0000)        </span>
<a name="l04048"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaf07eef15a372886fda3182f49e2e912e">04048</a> <span class="preprocessor">#define  FSMC_PMEM4_MEMHOLD4_0               ((uint32_t)0x00010000)        </span>
<a name="l04049"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaa05a691ca81b6fe6df07adb1c5142597">04049</a> <span class="preprocessor">#define  FSMC_PMEM4_MEMHOLD4_1               ((uint32_t)0x00020000)        </span>
<a name="l04050"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaafd4f50c33f4ec69e878983fb6065c73">04050</a> <span class="preprocessor">#define  FSMC_PMEM4_MEMHOLD4_2               ((uint32_t)0x00040000)        </span>
<a name="l04051"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gac3cf67d6699d41fc042aed2be6d6aef0">04051</a> <span class="preprocessor">#define  FSMC_PMEM4_MEMHOLD4_3               ((uint32_t)0x00080000)        </span>
<a name="l04052"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga963acb8aef1a1e3f7f369421a3f9bfd9">04052</a> <span class="preprocessor">#define  FSMC_PMEM4_MEMHOLD4_4               ((uint32_t)0x00100000)        </span>
<a name="l04053"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gac3ca8c6eb5fde2be7d38bde8aedb5522">04053</a> <span class="preprocessor">#define  FSMC_PMEM4_MEMHOLD4_5               ((uint32_t)0x00200000)        </span>
<a name="l04054"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gae0352f9aa02c4037d690b516d7385d27">04054</a> <span class="preprocessor">#define  FSMC_PMEM4_MEMHOLD4_6               ((uint32_t)0x00400000)        </span>
<a name="l04055"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga880aa86c933687f7565b7ab79776923e">04055</a> <span class="preprocessor">#define  FSMC_PMEM4_MEMHOLD4_7               ((uint32_t)0x00800000)        </span>
<a name="l04057"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga6b194500112e61e5dd41ded843bb08c6">04057</a> <span class="preprocessor">#define  FSMC_PMEM4_MEMHIZ4                  ((uint32_t)0xFF000000)        </span>
<a name="l04058"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga9298e847d13d24cbe87a3c477af9f02c">04058</a> <span class="preprocessor">#define  FSMC_PMEM4_MEMHIZ4_0                ((uint32_t)0x01000000)        </span>
<a name="l04059"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga591eb0822bbb91c4ba12f80d35424c4c">04059</a> <span class="preprocessor">#define  FSMC_PMEM4_MEMHIZ4_1                ((uint32_t)0x02000000)        </span>
<a name="l04060"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga6db858408154b3694bb1fdc995f7e069">04060</a> <span class="preprocessor">#define  FSMC_PMEM4_MEMHIZ4_2                ((uint32_t)0x04000000)        </span>
<a name="l04061"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga0e38ef7ec628928bea867de00af9b206">04061</a> <span class="preprocessor">#define  FSMC_PMEM4_MEMHIZ4_3                ((uint32_t)0x08000000)        </span>
<a name="l04062"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga81a86c24f41bd5363793953df972d941">04062</a> <span class="preprocessor">#define  FSMC_PMEM4_MEMHIZ4_4                ((uint32_t)0x10000000)        </span>
<a name="l04063"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga08a6ec2df1aa20cfcfacaed7e60417a0">04063</a> <span class="preprocessor">#define  FSMC_PMEM4_MEMHIZ4_5                ((uint32_t)0x20000000)        </span>
<a name="l04064"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga443fff9e0a661cce0d3fe96886eceb0b">04064</a> <span class="preprocessor">#define  FSMC_PMEM4_MEMHIZ4_6                ((uint32_t)0x40000000)        </span>
<a name="l04065"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga90cf92af2475f9f7cadbb9553225260d">04065</a> <span class="preprocessor">#define  FSMC_PMEM4_MEMHIZ4_7                ((uint32_t)0x80000000)        </span>
<a name="l04067"></a>04067 <span class="preprocessor"></span><span class="comment">/******************  Bit definition for FSMC_PATT2 register  ******************/</span>
<a name="l04068"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaab6cd1418de73ee3b214be589912e45f">04068</a> <span class="preprocessor">#define  FSMC_PATT2_ATTSET2                  ((uint32_t)0x000000FF)        </span>
<a name="l04069"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaab4718770edfb1b9b96df7410a58f79b">04069</a> <span class="preprocessor">#define  FSMC_PATT2_ATTSET2_0                ((uint32_t)0x00000001)        </span>
<a name="l04070"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga4cde8c8360b22a3fb63615b4274653c9">04070</a> <span class="preprocessor">#define  FSMC_PATT2_ATTSET2_1                ((uint32_t)0x00000002)        </span>
<a name="l04071"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gae80034b8760da9dd1faaf7e326b6002a">04071</a> <span class="preprocessor">#define  FSMC_PATT2_ATTSET2_2                ((uint32_t)0x00000004)        </span>
<a name="l04072"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga11924ff951b3e939d2d20807901a82bf">04072</a> <span class="preprocessor">#define  FSMC_PATT2_ATTSET2_3                ((uint32_t)0x00000008)        </span>
<a name="l04073"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gad1b81efbb998d5e86685075396fd83b0">04073</a> <span class="preprocessor">#define  FSMC_PATT2_ATTSET2_4                ((uint32_t)0x00000010)        </span>
<a name="l04074"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga3e89896b03049ad636484b44c7ecd670">04074</a> <span class="preprocessor">#define  FSMC_PATT2_ATTSET2_5                ((uint32_t)0x00000020)        </span>
<a name="l04075"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gac751391f5acb1f3229ca65a3424d316d">04075</a> <span class="preprocessor">#define  FSMC_PATT2_ATTSET2_6                ((uint32_t)0x00000040)        </span>
<a name="l04076"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gabb0f3115642332e5aef5cfa1b6b719d8">04076</a> <span class="preprocessor">#define  FSMC_PATT2_ATTSET2_7                ((uint32_t)0x00000080)        </span>
<a name="l04078"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga6fda97184969b04e909ac97d31da48e6">04078</a> <span class="preprocessor">#define  FSMC_PATT2_ATTWAIT2                 ((uint32_t)0x0000FF00)        </span>
<a name="l04079"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaf43a2874230fbe9b87f9495a736b9363">04079</a> <span class="preprocessor">#define  FSMC_PATT2_ATTWAIT2_0               ((uint32_t)0x00000100)        </span>
<a name="l04080"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaad30fbb45343ced8deb9bbc062dba46b">04080</a> <span class="preprocessor">#define  FSMC_PATT2_ATTWAIT2_1               ((uint32_t)0x00000200)        </span>
<a name="l04081"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gae78c7794f66cd2063464ab2e6ef2bd07">04081</a> <span class="preprocessor">#define  FSMC_PATT2_ATTWAIT2_2               ((uint32_t)0x00000400)        </span>
<a name="l04082"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga82c2de9009c75560a342122937b25853">04082</a> <span class="preprocessor">#define  FSMC_PATT2_ATTWAIT2_3               ((uint32_t)0x00000800)        </span>
<a name="l04083"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gae80b6a2fc197435f6b50b4ba035fb5fe">04083</a> <span class="preprocessor">#define  FSMC_PATT2_ATTWAIT2_4               ((uint32_t)0x00001000)        </span>
<a name="l04084"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gac924773c5fcbee73186600247618d10b">04084</a> <span class="preprocessor">#define  FSMC_PATT2_ATTWAIT2_5               ((uint32_t)0x00002000)        </span>
<a name="l04085"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga70b22c0b9a32e473f0eb56952ba58d95">04085</a> <span class="preprocessor">#define  FSMC_PATT2_ATTWAIT2_6               ((uint32_t)0x00004000)        </span>
<a name="l04086"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga2ade8feb15ddcef159ccf3ff55fb0c24">04086</a> <span class="preprocessor">#define  FSMC_PATT2_ATTWAIT2_7               ((uint32_t)0x00008000)        </span>
<a name="l04088"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gad007c3c6fbef432a5e6bb08bd6e0b1ce">04088</a> <span class="preprocessor">#define  FSMC_PATT2_ATTHOLD2                 ((uint32_t)0x00FF0000)        </span>
<a name="l04089"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga5b5e19eb38592e84b9c0f3f57df51892">04089</a> <span class="preprocessor">#define  FSMC_PATT2_ATTHOLD2_0               ((uint32_t)0x00010000)        </span>
<a name="l04090"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga13dface112bf1300689a4f00ba31abac">04090</a> <span class="preprocessor">#define  FSMC_PATT2_ATTHOLD2_1               ((uint32_t)0x00020000)        </span>
<a name="l04091"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaea0e1b34ac27f20c85db0f96eaeff994">04091</a> <span class="preprocessor">#define  FSMC_PATT2_ATTHOLD2_2               ((uint32_t)0x00040000)        </span>
<a name="l04092"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga1582860673c5e72f9441095d5af7b8ad">04092</a> <span class="preprocessor">#define  FSMC_PATT2_ATTHOLD2_3               ((uint32_t)0x00080000)        </span>
<a name="l04093"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gacdd679f3b80617291639cafcdd8f77d1">04093</a> <span class="preprocessor">#define  FSMC_PATT2_ATTHOLD2_4               ((uint32_t)0x00100000)        </span>
<a name="l04094"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga34e89cd935ec26279bc9876d9dd07b07">04094</a> <span class="preprocessor">#define  FSMC_PATT2_ATTHOLD2_5               ((uint32_t)0x00200000)        </span>
<a name="l04095"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga12c42d6d5746ef8d763d36b04f6e4644">04095</a> <span class="preprocessor">#define  FSMC_PATT2_ATTHOLD2_6               ((uint32_t)0x00400000)        </span>
<a name="l04096"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga93558ba1372a3709316b4734160b3874">04096</a> <span class="preprocessor">#define  FSMC_PATT2_ATTHOLD2_7               ((uint32_t)0x00800000)        </span>
<a name="l04098"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gae2726cd505612675158551fd9eed763f">04098</a> <span class="preprocessor">#define  FSMC_PATT2_ATTHIZ2                  ((uint32_t)0xFF000000)        </span>
<a name="l04099"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gae1ff9b8faa8372116ca931826d18a9c7">04099</a> <span class="preprocessor">#define  FSMC_PATT2_ATTHIZ2_0                ((uint32_t)0x01000000)        </span>
<a name="l04100"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaac4081b55783073164985488c9d4d6b8">04100</a> <span class="preprocessor">#define  FSMC_PATT2_ATTHIZ2_1                ((uint32_t)0x02000000)        </span>
<a name="l04101"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaa3cc10b4217452bae11c69ed9f6f1844">04101</a> <span class="preprocessor">#define  FSMC_PATT2_ATTHIZ2_2                ((uint32_t)0x04000000)        </span>
<a name="l04102"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga93e2929a1bcde578f374bbebaa9482d1">04102</a> <span class="preprocessor">#define  FSMC_PATT2_ATTHIZ2_3                ((uint32_t)0x08000000)        </span>
<a name="l04103"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gac536419b5ef258fa3f9140387e2f134f">04103</a> <span class="preprocessor">#define  FSMC_PATT2_ATTHIZ2_4                ((uint32_t)0x10000000)        </span>
<a name="l04104"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga5deab3153671ff06832dd651372f9ca7">04104</a> <span class="preprocessor">#define  FSMC_PATT2_ATTHIZ2_5                ((uint32_t)0x20000000)        </span>
<a name="l04105"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga047723a357976aca5bdf6575327986d2">04105</a> <span class="preprocessor">#define  FSMC_PATT2_ATTHIZ2_6                ((uint32_t)0x40000000)        </span>
<a name="l04106"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga859a5af02e12a11e7548085e9e186547">04106</a> <span class="preprocessor">#define  FSMC_PATT2_ATTHIZ2_7                ((uint32_t)0x80000000)        </span>
<a name="l04108"></a>04108 <span class="preprocessor"></span><span class="comment">/******************  Bit definition for FSMC_PATT3 register  ******************/</span>
<a name="l04109"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gae0487c57e948411f16c3a35927e60dd5">04109</a> <span class="preprocessor">#define  FSMC_PATT3_ATTSET3                  ((uint32_t)0x000000FF)        </span>
<a name="l04110"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga0e68a5b1bb5996422eac084d586359d4">04110</a> <span class="preprocessor">#define  FSMC_PATT3_ATTSET3_0                ((uint32_t)0x00000001)        </span>
<a name="l04111"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga2d8bd09ad36ab8cae67f87cb930ea428">04111</a> <span class="preprocessor">#define  FSMC_PATT3_ATTSET3_1                ((uint32_t)0x00000002)        </span>
<a name="l04112"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga29b9389601899ce2731c612ad05d9a96">04112</a> <span class="preprocessor">#define  FSMC_PATT3_ATTSET3_2                ((uint32_t)0x00000004)        </span>
<a name="l04113"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga97893656a7b65ec5420382de0b264a11">04113</a> <span class="preprocessor">#define  FSMC_PATT3_ATTSET3_3                ((uint32_t)0x00000008)        </span>
<a name="l04114"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga9a6993a1cc304b9300bdc365c2827d43">04114</a> <span class="preprocessor">#define  FSMC_PATT3_ATTSET3_4                ((uint32_t)0x00000010)        </span>
<a name="l04115"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga8cf65f61ce823183c3866607cab6bd09">04115</a> <span class="preprocessor">#define  FSMC_PATT3_ATTSET3_5                ((uint32_t)0x00000020)        </span>
<a name="l04116"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gab2d5a3dd16094a6279766692694aa16b">04116</a> <span class="preprocessor">#define  FSMC_PATT3_ATTSET3_6                ((uint32_t)0x00000040)        </span>
<a name="l04117"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga7668853b7956cdb13fd73ed10faf4526">04117</a> <span class="preprocessor">#define  FSMC_PATT3_ATTSET3_7                ((uint32_t)0x00000080)        </span>
<a name="l04119"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gad8aaf4c77a663cab07ac6c365a271599">04119</a> <span class="preprocessor">#define  FSMC_PATT3_ATTWAIT3                 ((uint32_t)0x0000FF00)        </span>
<a name="l04120"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gac5c5500a07e7885de5c372c55f147836">04120</a> <span class="preprocessor">#define  FSMC_PATT3_ATTWAIT3_0               ((uint32_t)0x00000100)        </span>
<a name="l04121"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaddddbd0a403b2aeefcfdb28a7da56bf0">04121</a> <span class="preprocessor">#define  FSMC_PATT3_ATTWAIT3_1               ((uint32_t)0x00000200)        </span>
<a name="l04122"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gac34cbe7e282e1074e6c4b9645e48db2f">04122</a> <span class="preprocessor">#define  FSMC_PATT3_ATTWAIT3_2               ((uint32_t)0x00000400)        </span>
<a name="l04123"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga771f2a5acde98a9760eb8a1338f416a3">04123</a> <span class="preprocessor">#define  FSMC_PATT3_ATTWAIT3_3               ((uint32_t)0x00000800)        </span>
<a name="l04124"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga1bcc944836a379b2b878d5129ff94ddb">04124</a> <span class="preprocessor">#define  FSMC_PATT3_ATTWAIT3_4               ((uint32_t)0x00001000)        </span>
<a name="l04125"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gacf722482193ca6a1bf90f17af567e019">04125</a> <span class="preprocessor">#define  FSMC_PATT3_ATTWAIT3_5               ((uint32_t)0x00002000)        </span>
<a name="l04126"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gac2cc3ce135f309f7574f0c3d1a0ffe88">04126</a> <span class="preprocessor">#define  FSMC_PATT3_ATTWAIT3_6               ((uint32_t)0x00004000)        </span>
<a name="l04127"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaa66342cc1db5dcad99153b5a2f22140e">04127</a> <span class="preprocessor">#define  FSMC_PATT3_ATTWAIT3_7               ((uint32_t)0x00008000)        </span>
<a name="l04129"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gab3a2e634d0f5e3c9716c0910e1efda60">04129</a> <span class="preprocessor">#define  FSMC_PATT3_ATTHOLD3                 ((uint32_t)0x00FF0000)        </span>
<a name="l04130"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gad34a9f1b84d670c4132c56fa30ca26f0">04130</a> <span class="preprocessor">#define  FSMC_PATT3_ATTHOLD3_0               ((uint32_t)0x00010000)        </span>
<a name="l04131"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga5b2ed392d654694fc330c6721bed5728">04131</a> <span class="preprocessor">#define  FSMC_PATT3_ATTHOLD3_1               ((uint32_t)0x00020000)        </span>
<a name="l04132"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga679d3ea50788981dac810ec62bc372f0">04132</a> <span class="preprocessor">#define  FSMC_PATT3_ATTHOLD3_2               ((uint32_t)0x00040000)        </span>
<a name="l04133"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga75d74cf52f238826e87d3a3c27b52acc">04133</a> <span class="preprocessor">#define  FSMC_PATT3_ATTHOLD3_3               ((uint32_t)0x00080000)        </span>
<a name="l04134"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaa8d656d40279e1655a6682dcc2762e92">04134</a> <span class="preprocessor">#define  FSMC_PATT3_ATTHOLD3_4               ((uint32_t)0x00100000)        </span>
<a name="l04135"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gafee75f2fcf37e20e983732f258f85371">04135</a> <span class="preprocessor">#define  FSMC_PATT3_ATTHOLD3_5               ((uint32_t)0x00200000)        </span>
<a name="l04136"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga777b93e1e3c802ede605644d3ff3bba7">04136</a> <span class="preprocessor">#define  FSMC_PATT3_ATTHOLD3_6               ((uint32_t)0x00400000)        </span>
<a name="l04137"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga39acada8d54a7a14d3838d042397bd74">04137</a> <span class="preprocessor">#define  FSMC_PATT3_ATTHOLD3_7               ((uint32_t)0x00800000)        </span>
<a name="l04139"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaea9d34b131aa7db353eef060ca37788c">04139</a> <span class="preprocessor">#define  FSMC_PATT3_ATTHIZ3                  ((uint32_t)0xFF000000)        </span>
<a name="l04140"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga5bc6736af23f6f033568e0085cd19964">04140</a> <span class="preprocessor">#define  FSMC_PATT3_ATTHIZ3_0                ((uint32_t)0x01000000)        </span>
<a name="l04141"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga41270d0ae8670f39b886b49e47e8195b">04141</a> <span class="preprocessor">#define  FSMC_PATT3_ATTHIZ3_1                ((uint32_t)0x02000000)        </span>
<a name="l04142"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga988ec453492aafacf205895c5398caf2">04142</a> <span class="preprocessor">#define  FSMC_PATT3_ATTHIZ3_2                ((uint32_t)0x04000000)        </span>
<a name="l04143"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga48885375147c060687bbccc6a234ce39">04143</a> <span class="preprocessor">#define  FSMC_PATT3_ATTHIZ3_3                ((uint32_t)0x08000000)        </span>
<a name="l04144"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga5ea193881223470d7b6a6ca3e3474a84">04144</a> <span class="preprocessor">#define  FSMC_PATT3_ATTHIZ3_4                ((uint32_t)0x10000000)        </span>
<a name="l04145"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga7ab1f4cb68cfb8717d2b29e3a84987b1">04145</a> <span class="preprocessor">#define  FSMC_PATT3_ATTHIZ3_5                ((uint32_t)0x20000000)        </span>
<a name="l04146"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga44fd348b342ec248b821123f3310f475">04146</a> <span class="preprocessor">#define  FSMC_PATT3_ATTHIZ3_6                ((uint32_t)0x40000000)        </span>
<a name="l04147"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga0ff1a3acc9bbab229000d48845ea1863">04147</a> <span class="preprocessor">#define  FSMC_PATT3_ATTHIZ3_7                ((uint32_t)0x80000000)        </span>
<a name="l04149"></a>04149 <span class="preprocessor"></span><span class="comment">/******************  Bit definition for FSMC_PATT4 register  ******************/</span>
<a name="l04150"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga7f4d8fb0d47b4a3fddf55c2532dd3159">04150</a> <span class="preprocessor">#define  FSMC_PATT4_ATTSET4                  ((uint32_t)0x000000FF)        </span>
<a name="l04151"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga1dac8bcf03610eb2d43b557f4d81532a">04151</a> <span class="preprocessor">#define  FSMC_PATT4_ATTSET4_0                ((uint32_t)0x00000001)        </span>
<a name="l04152"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaac2576c2a95871cbf9babd0778372571">04152</a> <span class="preprocessor">#define  FSMC_PATT4_ATTSET4_1                ((uint32_t)0x00000002)        </span>
<a name="l04153"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga88e760bbe9714ac07f381de3af0abc36">04153</a> <span class="preprocessor">#define  FSMC_PATT4_ATTSET4_2                ((uint32_t)0x00000004)        </span>
<a name="l04154"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga4b472fd4848733a921998f0305b5bc02">04154</a> <span class="preprocessor">#define  FSMC_PATT4_ATTSET4_3                ((uint32_t)0x00000008)        </span>
<a name="l04155"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gae7d0c69190a0d78fedc875c3dc6b9037">04155</a> <span class="preprocessor">#define  FSMC_PATT4_ATTSET4_4                ((uint32_t)0x00000010)        </span>
<a name="l04156"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga168c6f16be9721a5ea0e31230bd1939b">04156</a> <span class="preprocessor">#define  FSMC_PATT4_ATTSET4_5                ((uint32_t)0x00000020)        </span>
<a name="l04157"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga72fe744c036b2acc4fff8733ac48b0ae">04157</a> <span class="preprocessor">#define  FSMC_PATT4_ATTSET4_6                ((uint32_t)0x00000040)        </span>
<a name="l04158"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga4529b17de7cb4eeeff25496620978adc">04158</a> <span class="preprocessor">#define  FSMC_PATT4_ATTSET4_7                ((uint32_t)0x00000080)        </span>
<a name="l04160"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga01edeaedc31867997a188fa89cab2ec0">04160</a> <span class="preprocessor">#define  FSMC_PATT4_ATTWAIT4                 ((uint32_t)0x0000FF00)        </span>
<a name="l04161"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga5da7db34cd23f3126f224a0b845a66a8">04161</a> <span class="preprocessor">#define  FSMC_PATT4_ATTWAIT4_0               ((uint32_t)0x00000100)        </span>
<a name="l04162"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga14644aa2ed55afe2094015d74843a994">04162</a> <span class="preprocessor">#define  FSMC_PATT4_ATTWAIT4_1               ((uint32_t)0x00000200)        </span>
<a name="l04163"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaf1023d5ae8fab70e7fdfbaff4ed46657">04163</a> <span class="preprocessor">#define  FSMC_PATT4_ATTWAIT4_2               ((uint32_t)0x00000400)        </span>
<a name="l04164"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga906c9684ffcd8f0f9222cbfd0e21885a">04164</a> <span class="preprocessor">#define  FSMC_PATT4_ATTWAIT4_3               ((uint32_t)0x00000800)        </span>
<a name="l04165"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gae8d341a7448f645a2f849e591515f020">04165</a> <span class="preprocessor">#define  FSMC_PATT4_ATTWAIT4_4               ((uint32_t)0x00001000)        </span>
<a name="l04166"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaf278272c5fdaa8fa7c84e1c095690632">04166</a> <span class="preprocessor">#define  FSMC_PATT4_ATTWAIT4_5               ((uint32_t)0x00002000)        </span>
<a name="l04167"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga3126347e126717a761af0b6e44b9d72d">04167</a> <span class="preprocessor">#define  FSMC_PATT4_ATTWAIT4_6               ((uint32_t)0x00004000)        </span>
<a name="l04168"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga34afb78710ca450ac7065f0bc263075c">04168</a> <span class="preprocessor">#define  FSMC_PATT4_ATTWAIT4_7               ((uint32_t)0x00008000)        </span>
<a name="l04170"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga0bf06c395d55c775b4fbe202bac517a6">04170</a> <span class="preprocessor">#define  FSMC_PATT4_ATTHOLD4                 ((uint32_t)0x00FF0000)        </span>
<a name="l04171"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gad5c97b102bd1f2b61dcfb793c0d61d66">04171</a> <span class="preprocessor">#define  FSMC_PATT4_ATTHOLD4_0               ((uint32_t)0x00010000)        </span>
<a name="l04172"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga738c8d87ebcdff68725a54ff7f39675d">04172</a> <span class="preprocessor">#define  FSMC_PATT4_ATTHOLD4_1               ((uint32_t)0x00020000)        </span>
<a name="l04173"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga6d9610198e4710ca394e3aeb32aa229f">04173</a> <span class="preprocessor">#define  FSMC_PATT4_ATTHOLD4_2               ((uint32_t)0x00040000)        </span>
<a name="l04174"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gadd14059e9f658f37b3a1f18786395717">04174</a> <span class="preprocessor">#define  FSMC_PATT4_ATTHOLD4_3               ((uint32_t)0x00080000)        </span>
<a name="l04175"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga7a39fa40e2d4990097e31b47ad85283a">04175</a> <span class="preprocessor">#define  FSMC_PATT4_ATTHOLD4_4               ((uint32_t)0x00100000)        </span>
<a name="l04176"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga239e412f20305d58416f10a79e253a87">04176</a> <span class="preprocessor">#define  FSMC_PATT4_ATTHOLD4_5               ((uint32_t)0x00200000)        </span>
<a name="l04177"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaff1aac62acdf71077ee4a9e8e9e6d2d6">04177</a> <span class="preprocessor">#define  FSMC_PATT4_ATTHOLD4_6               ((uint32_t)0x00400000)        </span>
<a name="l04178"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga836fd2ad42b0c9f6d0eb651589d04123">04178</a> <span class="preprocessor">#define  FSMC_PATT4_ATTHOLD4_7               ((uint32_t)0x00800000)        </span>
<a name="l04180"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga35948e4e9e5ce9d674e9e70ca2aeafe3">04180</a> <span class="preprocessor">#define  FSMC_PATT4_ATTHIZ4                  ((uint32_t)0xFF000000)        </span>
<a name="l04181"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga5b746d7b655f6379af4dd4d5ba842492">04181</a> <span class="preprocessor">#define  FSMC_PATT4_ATTHIZ4_0                ((uint32_t)0x01000000)        </span>
<a name="l04182"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gac2dd87929111fc0c888dd7c311f8eba3">04182</a> <span class="preprocessor">#define  FSMC_PATT4_ATTHIZ4_1                ((uint32_t)0x02000000)        </span>
<a name="l04183"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga353c0709e22a06998f05b908a597f525">04183</a> <span class="preprocessor">#define  FSMC_PATT4_ATTHIZ4_2                ((uint32_t)0x04000000)        </span>
<a name="l04184"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaa777a5d42ac1e36044d7b18ffdd61a21">04184</a> <span class="preprocessor">#define  FSMC_PATT4_ATTHIZ4_3                ((uint32_t)0x08000000)        </span>
<a name="l04185"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga65c1778d08bfe2a40961f6acf023b9d4">04185</a> <span class="preprocessor">#define  FSMC_PATT4_ATTHIZ4_4                ((uint32_t)0x10000000)        </span>
<a name="l04186"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaadb7001986c9a4c28052b46657ad7a7e">04186</a> <span class="preprocessor">#define  FSMC_PATT4_ATTHIZ4_5                ((uint32_t)0x20000000)        </span>
<a name="l04187"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaa11a8d896354bd1c6645ac096db8e065">04187</a> <span class="preprocessor">#define  FSMC_PATT4_ATTHIZ4_6                ((uint32_t)0x40000000)        </span>
<a name="l04188"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga1a054f48705ec3fef0686c576f414f29">04188</a> <span class="preprocessor">#define  FSMC_PATT4_ATTHIZ4_7                ((uint32_t)0x80000000)        </span>
<a name="l04190"></a>04190 <span class="preprocessor"></span><span class="comment">/******************  Bit definition for FSMC_PIO4 register  *******************/</span>
<a name="l04191"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaf14b77f09f496a1325b5384eef54dd4a">04191</a> <span class="preprocessor">#define  FSMC_PIO4_IOSET4                    ((uint32_t)0x000000FF)        </span>
<a name="l04192"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga29c07a816f3065ae0c9287b6e3e0e967">04192</a> <span class="preprocessor">#define  FSMC_PIO4_IOSET4_0                  ((uint32_t)0x00000001)        </span>
<a name="l04193"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gac31898a52e172935f354819c50d3ef8d">04193</a> <span class="preprocessor">#define  FSMC_PIO4_IOSET4_1                  ((uint32_t)0x00000002)        </span>
<a name="l04194"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaf35797347825725faef495c676269927">04194</a> <span class="preprocessor">#define  FSMC_PIO4_IOSET4_2                  ((uint32_t)0x00000004)        </span>
<a name="l04195"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gae45109e3dcc3c3a15efd13eddffdd8c9">04195</a> <span class="preprocessor">#define  FSMC_PIO4_IOSET4_3                  ((uint32_t)0x00000008)        </span>
<a name="l04196"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga349e3a58f832fbc9de16955521355c29">04196</a> <span class="preprocessor">#define  FSMC_PIO4_IOSET4_4                  ((uint32_t)0x00000010)        </span>
<a name="l04197"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaf3304545838a6e20742b0203e0cb023a">04197</a> <span class="preprocessor">#define  FSMC_PIO4_IOSET4_5                  ((uint32_t)0x00000020)        </span>
<a name="l04198"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga800ab779078734ca86eedb6c9e77bc57">04198</a> <span class="preprocessor">#define  FSMC_PIO4_IOSET4_6                  ((uint32_t)0x00000040)        </span>
<a name="l04199"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga7e29b066726c486c6503d417d18904b1">04199</a> <span class="preprocessor">#define  FSMC_PIO4_IOSET4_7                  ((uint32_t)0x00000080)        </span>
<a name="l04201"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga035a0645caab3851714123302dd0af1c">04201</a> <span class="preprocessor">#define  FSMC_PIO4_IOWAIT4                   ((uint32_t)0x0000FF00)        </span>
<a name="l04202"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gafb868a5bf3d33997c782f296440cabf7">04202</a> <span class="preprocessor">#define  FSMC_PIO4_IOWAIT4_0                 ((uint32_t)0x00000100)        </span>
<a name="l04203"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaaa48c96fedf31c6ab444828d60e471da">04203</a> <span class="preprocessor">#define  FSMC_PIO4_IOWAIT4_1                 ((uint32_t)0x00000200)        </span>
<a name="l04204"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga342e42235a123ea11544b1a230b07a75">04204</a> <span class="preprocessor">#define  FSMC_PIO4_IOWAIT4_2                 ((uint32_t)0x00000400)        </span>
<a name="l04205"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga9c012d7c41f51516580766d6ac36d82f">04205</a> <span class="preprocessor">#define  FSMC_PIO4_IOWAIT4_3                 ((uint32_t)0x00000800)        </span>
<a name="l04206"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga5331b528505a31a2b39deca7a5ddba02">04206</a> <span class="preprocessor">#define  FSMC_PIO4_IOWAIT4_4                 ((uint32_t)0x00001000)        </span>
<a name="l04207"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaabbfbc377efde5170ac484795a0a4215">04207</a> <span class="preprocessor">#define  FSMC_PIO4_IOWAIT4_5                 ((uint32_t)0x00002000)        </span>
<a name="l04208"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga0be64ff24a6ccb7eef471ad2ad0e283b">04208</a> <span class="preprocessor">#define  FSMC_PIO4_IOWAIT4_6                 ((uint32_t)0x00004000)        </span>
<a name="l04209"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga3e3fc1b8cfa57116c0521cafd7e733cc">04209</a> <span class="preprocessor">#define  FSMC_PIO4_IOWAIT4_7                 ((uint32_t)0x00008000)        </span>
<a name="l04211"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gab55064df0d9fab8a072da6baa7b85878">04211</a> <span class="preprocessor">#define  FSMC_PIO4_IOHOLD4                   ((uint32_t)0x00FF0000)        </span>
<a name="l04212"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gadc1a288b385fcf83bfa95da479d387a4">04212</a> <span class="preprocessor">#define  FSMC_PIO4_IOHOLD4_0                 ((uint32_t)0x00010000)        </span>
<a name="l04213"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga402d7221ee27ce71d1b8bb18539d8307">04213</a> <span class="preprocessor">#define  FSMC_PIO4_IOHOLD4_1                 ((uint32_t)0x00020000)        </span>
<a name="l04214"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga274c5b835ec95c97c4f1c6ebbf72a096">04214</a> <span class="preprocessor">#define  FSMC_PIO4_IOHOLD4_2                 ((uint32_t)0x00040000)        </span>
<a name="l04215"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga519b9b4ae5b136769278eb98eb10c3a6">04215</a> <span class="preprocessor">#define  FSMC_PIO4_IOHOLD4_3                 ((uint32_t)0x00080000)        </span>
<a name="l04216"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gab2d013be2823d9ea9b81f8f76331c11d">04216</a> <span class="preprocessor">#define  FSMC_PIO4_IOHOLD4_4                 ((uint32_t)0x00100000)        </span>
<a name="l04217"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga5a14c965f1ff993e0976aaefe638e2f6">04217</a> <span class="preprocessor">#define  FSMC_PIO4_IOHOLD4_5                 ((uint32_t)0x00200000)        </span>
<a name="l04218"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga49411f21445032ad8eaca19e89d204bc">04218</a> <span class="preprocessor">#define  FSMC_PIO4_IOHOLD4_6                 ((uint32_t)0x00400000)        </span>
<a name="l04219"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga323dcc3be986d57d14b794cca0038953">04219</a> <span class="preprocessor">#define  FSMC_PIO4_IOHOLD4_7                 ((uint32_t)0x00800000)        </span>
<a name="l04221"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga4cce93379430df64fd697ad772bc477d">04221</a> <span class="preprocessor">#define  FSMC_PIO4_IOHIZ4                    ((uint32_t)0xFF000000)        </span>
<a name="l04222"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaaf3b5c59e3eb4e259ddb722b1e536e5c">04222</a> <span class="preprocessor">#define  FSMC_PIO4_IOHIZ4_0                  ((uint32_t)0x01000000)        </span>
<a name="l04223"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga3e8c66264d4ec7b69de613cb528cfee2">04223</a> <span class="preprocessor">#define  FSMC_PIO4_IOHIZ4_1                  ((uint32_t)0x02000000)        </span>
<a name="l04224"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gab943b8acd274a8892e691ffab36a6a21">04224</a> <span class="preprocessor">#define  FSMC_PIO4_IOHIZ4_2                  ((uint32_t)0x04000000)        </span>
<a name="l04225"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga4184c40fd57a850605ac12c73553b6ba">04225</a> <span class="preprocessor">#define  FSMC_PIO4_IOHIZ4_3                  ((uint32_t)0x08000000)        </span>
<a name="l04226"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga9f966bdf26f7fa0f52076438219df7ee">04226</a> <span class="preprocessor">#define  FSMC_PIO4_IOHIZ4_4                  ((uint32_t)0x10000000)        </span>
<a name="l04227"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga9ba68883e73a331543a2990a76d1e91a">04227</a> <span class="preprocessor">#define  FSMC_PIO4_IOHIZ4_5                  ((uint32_t)0x20000000)        </span>
<a name="l04228"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga8b2c084a1dfbf7fb7bd922faa48bad8a">04228</a> <span class="preprocessor">#define  FSMC_PIO4_IOHIZ4_6                  ((uint32_t)0x40000000)        </span>
<a name="l04229"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gabc8aef29e6eaecd3ff2c13bae143b8b4">04229</a> <span class="preprocessor">#define  FSMC_PIO4_IOHIZ4_7                  ((uint32_t)0x80000000)        </span>
<a name="l04231"></a>04231 <span class="preprocessor"></span><span class="comment">/******************  Bit definition for FSMC_ECCR2 register  ******************/</span>
<a name="l04232"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga43da355ad2eb7d974488a02921b1b2ba">04232</a> <span class="preprocessor">#define  FSMC_ECCR2_ECC2                     ((uint32_t)0xFFFFFFFF)        </span>
<a name="l04234"></a>04234 <span class="preprocessor"></span><span class="comment">/******************  Bit definition for FSMC_ECCR3 register  ******************/</span>
<a name="l04235"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga798b288a17d84edc99ff1f5f81cf70be">04235</a> <span class="preprocessor">#define  FSMC_ECCR3_ECC3                     ((uint32_t)0xFFFFFFFF)        </span>
<a name="l04237"></a>04237 <span class="preprocessor"></span><span class="comment">/******************************************************************************/</span>
<a name="l04238"></a>04238 <span class="comment">/*                                                                            */</span>
<a name="l04239"></a>04239 <span class="comment">/*                            General Purpose I/O                             */</span>
<a name="l04240"></a>04240 <span class="comment">/*                                                                            */</span>
<a name="l04241"></a>04241 <span class="comment">/******************************************************************************/</span>
<a name="l04242"></a>04242 <span class="comment">/******************  Bits definition for GPIO_MODER register  *****************/</span>
<a name="l04243"></a>04243 <span class="preprocessor">#define GPIO_MODER_MODER0                    ((uint32_t)0x00000003)</span>
<a name="l04244"></a>04244 <span class="preprocessor"></span><span class="preprocessor">#define GPIO_MODER_MODER0_0                  ((uint32_t)0x00000001)</span>
<a name="l04245"></a>04245 <span class="preprocessor"></span><span class="preprocessor">#define GPIO_MODER_MODER0_1                  ((uint32_t)0x00000002)</span>
<a name="l04246"></a>04246 <span class="preprocessor"></span>
<a name="l04247"></a>04247 <span class="preprocessor">#define GPIO_MODER_MODER1                    ((uint32_t)0x0000000C)</span>
<a name="l04248"></a>04248 <span class="preprocessor"></span><span class="preprocessor">#define GPIO_MODER_MODER1_0                  ((uint32_t)0x00000004)</span>
<a name="l04249"></a>04249 <span class="preprocessor"></span><span class="preprocessor">#define GPIO_MODER_MODER1_1                  ((uint32_t)0x00000008)</span>
<a name="l04250"></a>04250 <span class="preprocessor"></span>
<a name="l04251"></a>04251 <span class="preprocessor">#define GPIO_MODER_MODER2                    ((uint32_t)0x00000030)</span>
<a name="l04252"></a>04252 <span class="preprocessor"></span><span class="preprocessor">#define GPIO_MODER_MODER2_0                  ((uint32_t)0x00000010)</span>
<a name="l04253"></a>04253 <span class="preprocessor"></span><span class="preprocessor">#define GPIO_MODER_MODER2_1                  ((uint32_t)0x00000020)</span>
<a name="l04254"></a>04254 <span class="preprocessor"></span>
<a name="l04255"></a>04255 <span class="preprocessor">#define GPIO_MODER_MODER3                    ((uint32_t)0x000000C0)</span>
<a name="l04256"></a>04256 <span class="preprocessor"></span><span class="preprocessor">#define GPIO_MODER_MODER3_0                  ((uint32_t)0x00000040)</span>
<a name="l04257"></a>04257 <span class="preprocessor"></span><span class="preprocessor">#define GPIO_MODER_MODER3_1                  ((uint32_t)0x00000080)</span>
<a name="l04258"></a>04258 <span class="preprocessor"></span>
<a name="l04259"></a>04259 <span class="preprocessor">#define GPIO_MODER_MODER4                    ((uint32_t)0x00000300)</span>
<a name="l04260"></a>04260 <span class="preprocessor"></span><span class="preprocessor">#define GPIO_MODER_MODER4_0                  ((uint32_t)0x00000100)</span>
<a name="l04261"></a>04261 <span class="preprocessor"></span><span class="preprocessor">#define GPIO_MODER_MODER4_1                  ((uint32_t)0x00000200)</span>
<a name="l04262"></a>04262 <span class="preprocessor"></span>
<a name="l04263"></a>04263 <span class="preprocessor">#define GPIO_MODER_MODER5                    ((uint32_t)0x00000C00)</span>
<a name="l04264"></a>04264 <span class="preprocessor"></span><span class="preprocessor">#define GPIO_MODER_MODER5_0                  ((uint32_t)0x00000400)</span>
<a name="l04265"></a>04265 <span class="preprocessor"></span><span class="preprocessor">#define GPIO_MODER_MODER5_1                  ((uint32_t)0x00000800)</span>
<a name="l04266"></a>04266 <span class="preprocessor"></span>
<a name="l04267"></a>04267 <span class="preprocessor">#define GPIO_MODER_MODER6                    ((uint32_t)0x00003000)</span>
<a name="l04268"></a>04268 <span class="preprocessor"></span><span class="preprocessor">#define GPIO_MODER_MODER6_0                  ((uint32_t)0x00001000)</span>
<a name="l04269"></a>04269 <span class="preprocessor"></span><span class="preprocessor">#define GPIO_MODER_MODER6_1                  ((uint32_t)0x00002000)</span>
<a name="l04270"></a>04270 <span class="preprocessor"></span>
<a name="l04271"></a>04271 <span class="preprocessor">#define GPIO_MODER_MODER7                    ((uint32_t)0x0000C000)</span>
<a name="l04272"></a>04272 <span class="preprocessor"></span><span class="preprocessor">#define GPIO_MODER_MODER7_0                  ((uint32_t)0x00004000)</span>
<a name="l04273"></a>04273 <span class="preprocessor"></span><span class="preprocessor">#define GPIO_MODER_MODER7_1                  ((uint32_t)0x00008000)</span>
<a name="l04274"></a>04274 <span class="preprocessor"></span>
<a name="l04275"></a>04275 <span class="preprocessor">#define GPIO_MODER_MODER8                    ((uint32_t)0x00030000)</span>
<a name="l04276"></a>04276 <span class="preprocessor"></span><span class="preprocessor">#define GPIO_MODER_MODER8_0                  ((uint32_t)0x00010000)</span>
<a name="l04277"></a>04277 <span class="preprocessor"></span><span class="preprocessor">#define GPIO_MODER_MODER8_1                  ((uint32_t)0x00020000)</span>
<a name="l04278"></a>04278 <span class="preprocessor"></span>
<a name="l04279"></a>04279 <span class="preprocessor">#define GPIO_MODER_MODER9                    ((uint32_t)0x000C0000)</span>
<a name="l04280"></a>04280 <span class="preprocessor"></span><span class="preprocessor">#define GPIO_MODER_MODER9_0                  ((uint32_t)0x00040000)</span>
<a name="l04281"></a>04281 <span class="preprocessor"></span><span class="preprocessor">#define GPIO_MODER_MODER9_1                  ((uint32_t)0x00080000)</span>
<a name="l04282"></a>04282 <span class="preprocessor"></span>
<a name="l04283"></a>04283 <span class="preprocessor">#define GPIO_MODER_MODER10                   ((uint32_t)0x00300000)</span>
<a name="l04284"></a>04284 <span class="preprocessor"></span><span class="preprocessor">#define GPIO_MODER_MODER10_0                 ((uint32_t)0x00100000)</span>
<a name="l04285"></a>04285 <span class="preprocessor"></span><span class="preprocessor">#define GPIO_MODER_MODER10_1                 ((uint32_t)0x00200000)</span>
<a name="l04286"></a>04286 <span class="preprocessor"></span>
<a name="l04287"></a>04287 <span class="preprocessor">#define GPIO_MODER_MODER11                   ((uint32_t)0x00C00000)</span>
<a name="l04288"></a>04288 <span class="preprocessor"></span><span class="preprocessor">#define GPIO_MODER_MODER11_0                 ((uint32_t)0x00400000)</span>
<a name="l04289"></a>04289 <span class="preprocessor"></span><span class="preprocessor">#define GPIO_MODER_MODER11_1                 ((uint32_t)0x00800000)</span>
<a name="l04290"></a>04290 <span class="preprocessor"></span>
<a name="l04291"></a>04291 <span class="preprocessor">#define GPIO_MODER_MODER12                   ((uint32_t)0x03000000)</span>
<a name="l04292"></a>04292 <span class="preprocessor"></span><span class="preprocessor">#define GPIO_MODER_MODER12_0                 ((uint32_t)0x01000000)</span>
<a name="l04293"></a>04293 <span class="preprocessor"></span><span class="preprocessor">#define GPIO_MODER_MODER12_1                 ((uint32_t)0x02000000)</span>
<a name="l04294"></a>04294 <span class="preprocessor"></span>
<a name="l04295"></a>04295 <span class="preprocessor">#define GPIO_MODER_MODER13                   ((uint32_t)0x0C000000)</span>
<a name="l04296"></a>04296 <span class="preprocessor"></span><span class="preprocessor">#define GPIO_MODER_MODER13_0                 ((uint32_t)0x04000000)</span>
<a name="l04297"></a>04297 <span class="preprocessor"></span><span class="preprocessor">#define GPIO_MODER_MODER13_1                 ((uint32_t)0x08000000)</span>
<a name="l04298"></a>04298 <span class="preprocessor"></span>
<a name="l04299"></a>04299 <span class="preprocessor">#define GPIO_MODER_MODER14                   ((uint32_t)0x30000000)</span>
<a name="l04300"></a>04300 <span class="preprocessor"></span><span class="preprocessor">#define GPIO_MODER_MODER14_0                 ((uint32_t)0x10000000)</span>
<a name="l04301"></a>04301 <span class="preprocessor"></span><span class="preprocessor">#define GPIO_MODER_MODER14_1                 ((uint32_t)0x20000000)</span>
<a name="l04302"></a>04302 <span class="preprocessor"></span>
<a name="l04303"></a>04303 <span class="preprocessor">#define GPIO_MODER_MODER15                   ((uint32_t)0xC0000000)</span>
<a name="l04304"></a>04304 <span class="preprocessor"></span><span class="preprocessor">#define GPIO_MODER_MODER15_0                 ((uint32_t)0x40000000)</span>
<a name="l04305"></a>04305 <span class="preprocessor"></span><span class="preprocessor">#define GPIO_MODER_MODER15_1                 ((uint32_t)0x80000000)</span>
<a name="l04306"></a>04306 <span class="preprocessor"></span>
<a name="l04307"></a>04307 <span class="comment">/******************  Bits definition for GPIO_OTYPER register  ****************/</span>
<a name="l04308"></a>04308 <span class="preprocessor">#define GPIO_OTYPER_OT_0                     ((uint32_t)0x00000001)</span>
<a name="l04309"></a>04309 <span class="preprocessor"></span><span class="preprocessor">#define GPIO_OTYPER_OT_1                     ((uint32_t)0x00000002)</span>
<a name="l04310"></a>04310 <span class="preprocessor"></span><span class="preprocessor">#define GPIO_OTYPER_OT_2                     ((uint32_t)0x00000004)</span>
<a name="l04311"></a>04311 <span class="preprocessor"></span><span class="preprocessor">#define GPIO_OTYPER_OT_3                     ((uint32_t)0x00000008)</span>
<a name="l04312"></a>04312 <span class="preprocessor"></span><span class="preprocessor">#define GPIO_OTYPER_OT_4                     ((uint32_t)0x00000010)</span>
<a name="l04313"></a>04313 <span class="preprocessor"></span><span class="preprocessor">#define GPIO_OTYPER_OT_5                     ((uint32_t)0x00000020)</span>
<a name="l04314"></a>04314 <span class="preprocessor"></span><span class="preprocessor">#define GPIO_OTYPER_OT_6                     ((uint32_t)0x00000040)</span>
<a name="l04315"></a>04315 <span class="preprocessor"></span><span class="preprocessor">#define GPIO_OTYPER_OT_7                     ((uint32_t)0x00000080)</span>
<a name="l04316"></a>04316 <span class="preprocessor"></span><span class="preprocessor">#define GPIO_OTYPER_OT_8                     ((uint32_t)0x00000100)</span>
<a name="l04317"></a>04317 <span class="preprocessor"></span><span class="preprocessor">#define GPIO_OTYPER_OT_9                     ((uint32_t)0x00000200)</span>
<a name="l04318"></a>04318 <span class="preprocessor"></span><span class="preprocessor">#define GPIO_OTYPER_OT_10                    ((uint32_t)0x00000400)</span>
<a name="l04319"></a>04319 <span class="preprocessor"></span><span class="preprocessor">#define GPIO_OTYPER_OT_11                    ((uint32_t)0x00000800)</span>
<a name="l04320"></a>04320 <span class="preprocessor"></span><span class="preprocessor">#define GPIO_OTYPER_OT_12                    ((uint32_t)0x00001000)</span>
<a name="l04321"></a>04321 <span class="preprocessor"></span><span class="preprocessor">#define GPIO_OTYPER_OT_13                    ((uint32_t)0x00002000)</span>
<a name="l04322"></a>04322 <span class="preprocessor"></span><span class="preprocessor">#define GPIO_OTYPER_OT_14                    ((uint32_t)0x00004000)</span>
<a name="l04323"></a>04323 <span class="preprocessor"></span><span class="preprocessor">#define GPIO_OTYPER_OT_15                    ((uint32_t)0x00008000)</span>
<a name="l04324"></a>04324 <span class="preprocessor"></span>
<a name="l04325"></a>04325 <span class="comment">/******************  Bits definition for GPIO_OSPEEDR register  ***************/</span>
<a name="l04326"></a>04326 <span class="preprocessor">#define GPIO_OSPEEDER_OSPEEDR0               ((uint32_t)0x00000003)</span>
<a name="l04327"></a>04327 <span class="preprocessor"></span><span class="preprocessor">#define GPIO_OSPEEDER_OSPEEDR0_0             ((uint32_t)0x00000001)</span>
<a name="l04328"></a>04328 <span class="preprocessor"></span><span class="preprocessor">#define GPIO_OSPEEDER_OSPEEDR0_1             ((uint32_t)0x00000002)</span>
<a name="l04329"></a>04329 <span class="preprocessor"></span>
<a name="l04330"></a>04330 <span class="preprocessor">#define GPIO_OSPEEDER_OSPEEDR1               ((uint32_t)0x0000000C)</span>
<a name="l04331"></a>04331 <span class="preprocessor"></span><span class="preprocessor">#define GPIO_OSPEEDER_OSPEEDR1_0             ((uint32_t)0x00000004)</span>
<a name="l04332"></a>04332 <span class="preprocessor"></span><span class="preprocessor">#define GPIO_OSPEEDER_OSPEEDR1_1             ((uint32_t)0x00000008)</span>
<a name="l04333"></a>04333 <span class="preprocessor"></span>
<a name="l04334"></a>04334 <span class="preprocessor">#define GPIO_OSPEEDER_OSPEEDR2               ((uint32_t)0x00000030)</span>
<a name="l04335"></a>04335 <span class="preprocessor"></span><span class="preprocessor">#define GPIO_OSPEEDER_OSPEEDR2_0             ((uint32_t)0x00000010)</span>
<a name="l04336"></a>04336 <span class="preprocessor"></span><span class="preprocessor">#define GPIO_OSPEEDER_OSPEEDR2_1             ((uint32_t)0x00000020)</span>
<a name="l04337"></a>04337 <span class="preprocessor"></span>
<a name="l04338"></a>04338 <span class="preprocessor">#define GPIO_OSPEEDER_OSPEEDR3               ((uint32_t)0x000000C0)</span>
<a name="l04339"></a>04339 <span class="preprocessor"></span><span class="preprocessor">#define GPIO_OSPEEDER_OSPEEDR3_0             ((uint32_t)0x00000040)</span>
<a name="l04340"></a>04340 <span class="preprocessor"></span><span class="preprocessor">#define GPIO_OSPEEDER_OSPEEDR3_1             ((uint32_t)0x00000080)</span>
<a name="l04341"></a>04341 <span class="preprocessor"></span>
<a name="l04342"></a>04342 <span class="preprocessor">#define GPIO_OSPEEDER_OSPEEDR4               ((uint32_t)0x00000300)</span>
<a name="l04343"></a>04343 <span class="preprocessor"></span><span class="preprocessor">#define GPIO_OSPEEDER_OSPEEDR4_0             ((uint32_t)0x00000100)</span>
<a name="l04344"></a>04344 <span class="preprocessor"></span><span class="preprocessor">#define GPIO_OSPEEDER_OSPEEDR4_1             ((uint32_t)0x00000200)</span>
<a name="l04345"></a>04345 <span class="preprocessor"></span>
<a name="l04346"></a>04346 <span class="preprocessor">#define GPIO_OSPEEDER_OSPEEDR5               ((uint32_t)0x00000C00)</span>
<a name="l04347"></a>04347 <span class="preprocessor"></span><span class="preprocessor">#define GPIO_OSPEEDER_OSPEEDR5_0             ((uint32_t)0x00000400)</span>
<a name="l04348"></a>04348 <span class="preprocessor"></span><span class="preprocessor">#define GPIO_OSPEEDER_OSPEEDR5_1             ((uint32_t)0x00000800)</span>
<a name="l04349"></a>04349 <span class="preprocessor"></span>
<a name="l04350"></a>04350 <span class="preprocessor">#define GPIO_OSPEEDER_OSPEEDR6               ((uint32_t)0x00003000)</span>
<a name="l04351"></a>04351 <span class="preprocessor"></span><span class="preprocessor">#define GPIO_OSPEEDER_OSPEEDR6_0             ((uint32_t)0x00001000)</span>
<a name="l04352"></a>04352 <span class="preprocessor"></span><span class="preprocessor">#define GPIO_OSPEEDER_OSPEEDR6_1             ((uint32_t)0x00002000)</span>
<a name="l04353"></a>04353 <span class="preprocessor"></span>
<a name="l04354"></a>04354 <span class="preprocessor">#define GPIO_OSPEEDER_OSPEEDR7               ((uint32_t)0x0000C000)</span>
<a name="l04355"></a>04355 <span class="preprocessor"></span><span class="preprocessor">#define GPIO_OSPEEDER_OSPEEDR7_0             ((uint32_t)0x00004000)</span>
<a name="l04356"></a>04356 <span class="preprocessor"></span><span class="preprocessor">#define GPIO_OSPEEDER_OSPEEDR7_1             ((uint32_t)0x00008000)</span>
<a name="l04357"></a>04357 <span class="preprocessor"></span>
<a name="l04358"></a>04358 <span class="preprocessor">#define GPIO_OSPEEDER_OSPEEDR8               ((uint32_t)0x00030000)</span>
<a name="l04359"></a>04359 <span class="preprocessor"></span><span class="preprocessor">#define GPIO_OSPEEDER_OSPEEDR8_0             ((uint32_t)0x00010000)</span>
<a name="l04360"></a>04360 <span class="preprocessor"></span><span class="preprocessor">#define GPIO_OSPEEDER_OSPEEDR8_1             ((uint32_t)0x00020000)</span>
<a name="l04361"></a>04361 <span class="preprocessor"></span>
<a name="l04362"></a>04362 <span class="preprocessor">#define GPIO_OSPEEDER_OSPEEDR9               ((uint32_t)0x000C0000)</span>
<a name="l04363"></a>04363 <span class="preprocessor"></span><span class="preprocessor">#define GPIO_OSPEEDER_OSPEEDR9_0             ((uint32_t)0x00040000)</span>
<a name="l04364"></a>04364 <span class="preprocessor"></span><span class="preprocessor">#define GPIO_OSPEEDER_OSPEEDR9_1             ((uint32_t)0x00080000)</span>
<a name="l04365"></a>04365 <span class="preprocessor"></span>
<a name="l04366"></a>04366 <span class="preprocessor">#define GPIO_OSPEEDER_OSPEEDR10              ((uint32_t)0x00300000)</span>
<a name="l04367"></a>04367 <span class="preprocessor"></span><span class="preprocessor">#define GPIO_OSPEEDER_OSPEEDR10_0            ((uint32_t)0x00100000)</span>
<a name="l04368"></a>04368 <span class="preprocessor"></span><span class="preprocessor">#define GPIO_OSPEEDER_OSPEEDR10_1            ((uint32_t)0x00200000)</span>
<a name="l04369"></a>04369 <span class="preprocessor"></span>
<a name="l04370"></a>04370 <span class="preprocessor">#define GPIO_OSPEEDER_OSPEEDR11              ((uint32_t)0x00C00000)</span>
<a name="l04371"></a>04371 <span class="preprocessor"></span><span class="preprocessor">#define GPIO_OSPEEDER_OSPEEDR11_0            ((uint32_t)0x00400000)</span>
<a name="l04372"></a>04372 <span class="preprocessor"></span><span class="preprocessor">#define GPIO_OSPEEDER_OSPEEDR11_1            ((uint32_t)0x00800000)</span>
<a name="l04373"></a>04373 <span class="preprocessor"></span>
<a name="l04374"></a>04374 <span class="preprocessor">#define GPIO_OSPEEDER_OSPEEDR12              ((uint32_t)0x03000000)</span>
<a name="l04375"></a>04375 <span class="preprocessor"></span><span class="preprocessor">#define GPIO_OSPEEDER_OSPEEDR12_0            ((uint32_t)0x01000000)</span>
<a name="l04376"></a>04376 <span class="preprocessor"></span><span class="preprocessor">#define GPIO_OSPEEDER_OSPEEDR12_1            ((uint32_t)0x02000000)</span>
<a name="l04377"></a>04377 <span class="preprocessor"></span>
<a name="l04378"></a>04378 <span class="preprocessor">#define GPIO_OSPEEDER_OSPEEDR13              ((uint32_t)0x0C000000)</span>
<a name="l04379"></a>04379 <span class="preprocessor"></span><span class="preprocessor">#define GPIO_OSPEEDER_OSPEEDR13_0            ((uint32_t)0x04000000)</span>
<a name="l04380"></a>04380 <span class="preprocessor"></span><span class="preprocessor">#define GPIO_OSPEEDER_OSPEEDR13_1            ((uint32_t)0x08000000)</span>
<a name="l04381"></a>04381 <span class="preprocessor"></span>
<a name="l04382"></a>04382 <span class="preprocessor">#define GPIO_OSPEEDER_OSPEEDR14              ((uint32_t)0x30000000)</span>
<a name="l04383"></a>04383 <span class="preprocessor"></span><span class="preprocessor">#define GPIO_OSPEEDER_OSPEEDR14_0            ((uint32_t)0x10000000)</span>
<a name="l04384"></a>04384 <span class="preprocessor"></span><span class="preprocessor">#define GPIO_OSPEEDER_OSPEEDR14_1            ((uint32_t)0x20000000)</span>
<a name="l04385"></a>04385 <span class="preprocessor"></span>
<a name="l04386"></a>04386 <span class="preprocessor">#define GPIO_OSPEEDER_OSPEEDR15              ((uint32_t)0xC0000000)</span>
<a name="l04387"></a>04387 <span class="preprocessor"></span><span class="preprocessor">#define GPIO_OSPEEDER_OSPEEDR15_0            ((uint32_t)0x40000000)</span>
<a name="l04388"></a>04388 <span class="preprocessor"></span><span class="preprocessor">#define GPIO_OSPEEDER_OSPEEDR15_1            ((uint32_t)0x80000000)</span>
<a name="l04389"></a>04389 <span class="preprocessor"></span>
<a name="l04390"></a>04390 <span class="comment">/******************  Bits definition for GPIO_PUPDR register  *****************/</span>
<a name="l04391"></a>04391 <span class="preprocessor">#define GPIO_PUPDR_PUPDR0                    ((uint32_t)0x00000003)</span>
<a name="l04392"></a>04392 <span class="preprocessor"></span><span class="preprocessor">#define GPIO_PUPDR_PUPDR0_0                  ((uint32_t)0x00000001)</span>
<a name="l04393"></a>04393 <span class="preprocessor"></span><span class="preprocessor">#define GPIO_PUPDR_PUPDR0_1                  ((uint32_t)0x00000002)</span>
<a name="l04394"></a>04394 <span class="preprocessor"></span>
<a name="l04395"></a>04395 <span class="preprocessor">#define GPIO_PUPDR_PUPDR1                    ((uint32_t)0x0000000C)</span>
<a name="l04396"></a>04396 <span class="preprocessor"></span><span class="preprocessor">#define GPIO_PUPDR_PUPDR1_0                  ((uint32_t)0x00000004)</span>
<a name="l04397"></a>04397 <span class="preprocessor"></span><span class="preprocessor">#define GPIO_PUPDR_PUPDR1_1                  ((uint32_t)0x00000008)</span>
<a name="l04398"></a>04398 <span class="preprocessor"></span>
<a name="l04399"></a>04399 <span class="preprocessor">#define GPIO_PUPDR_PUPDR2                    ((uint32_t)0x00000030)</span>
<a name="l04400"></a>04400 <span class="preprocessor"></span><span class="preprocessor">#define GPIO_PUPDR_PUPDR2_0                  ((uint32_t)0x00000010)</span>
<a name="l04401"></a>04401 <span class="preprocessor"></span><span class="preprocessor">#define GPIO_PUPDR_PUPDR2_1                  ((uint32_t)0x00000020)</span>
<a name="l04402"></a>04402 <span class="preprocessor"></span>
<a name="l04403"></a>04403 <span class="preprocessor">#define GPIO_PUPDR_PUPDR3                    ((uint32_t)0x000000C0)</span>
<a name="l04404"></a>04404 <span class="preprocessor"></span><span class="preprocessor">#define GPIO_PUPDR_PUPDR3_0                  ((uint32_t)0x00000040)</span>
<a name="l04405"></a>04405 <span class="preprocessor"></span><span class="preprocessor">#define GPIO_PUPDR_PUPDR3_1                  ((uint32_t)0x00000080)</span>
<a name="l04406"></a>04406 <span class="preprocessor"></span>
<a name="l04407"></a>04407 <span class="preprocessor">#define GPIO_PUPDR_PUPDR4                    ((uint32_t)0x00000300)</span>
<a name="l04408"></a>04408 <span class="preprocessor"></span><span class="preprocessor">#define GPIO_PUPDR_PUPDR4_0                  ((uint32_t)0x00000100)</span>
<a name="l04409"></a>04409 <span class="preprocessor"></span><span class="preprocessor">#define GPIO_PUPDR_PUPDR4_1                  ((uint32_t)0x00000200)</span>
<a name="l04410"></a>04410 <span class="preprocessor"></span>
<a name="l04411"></a>04411 <span class="preprocessor">#define GPIO_PUPDR_PUPDR5                    ((uint32_t)0x00000C00)</span>
<a name="l04412"></a>04412 <span class="preprocessor"></span><span class="preprocessor">#define GPIO_PUPDR_PUPDR5_0                  ((uint32_t)0x00000400)</span>
<a name="l04413"></a>04413 <span class="preprocessor"></span><span class="preprocessor">#define GPIO_PUPDR_PUPDR5_1                  ((uint32_t)0x00000800)</span>
<a name="l04414"></a>04414 <span class="preprocessor"></span>
<a name="l04415"></a>04415 <span class="preprocessor">#define GPIO_PUPDR_PUPDR6                    ((uint32_t)0x00003000)</span>
<a name="l04416"></a>04416 <span class="preprocessor"></span><span class="preprocessor">#define GPIO_PUPDR_PUPDR6_0                  ((uint32_t)0x00001000)</span>
<a name="l04417"></a>04417 <span class="preprocessor"></span><span class="preprocessor">#define GPIO_PUPDR_PUPDR6_1                  ((uint32_t)0x00002000)</span>
<a name="l04418"></a>04418 <span class="preprocessor"></span>
<a name="l04419"></a>04419 <span class="preprocessor">#define GPIO_PUPDR_PUPDR7                    ((uint32_t)0x0000C000)</span>
<a name="l04420"></a>04420 <span class="preprocessor"></span><span class="preprocessor">#define GPIO_PUPDR_PUPDR7_0                  ((uint32_t)0x00004000)</span>
<a name="l04421"></a>04421 <span class="preprocessor"></span><span class="preprocessor">#define GPIO_PUPDR_PUPDR7_1                  ((uint32_t)0x00008000)</span>
<a name="l04422"></a>04422 <span class="preprocessor"></span>
<a name="l04423"></a>04423 <span class="preprocessor">#define GPIO_PUPDR_PUPDR8                    ((uint32_t)0x00030000)</span>
<a name="l04424"></a>04424 <span class="preprocessor"></span><span class="preprocessor">#define GPIO_PUPDR_PUPDR8_0                  ((uint32_t)0x00010000)</span>
<a name="l04425"></a>04425 <span class="preprocessor"></span><span class="preprocessor">#define GPIO_PUPDR_PUPDR8_1                  ((uint32_t)0x00020000)</span>
<a name="l04426"></a>04426 <span class="preprocessor"></span>
<a name="l04427"></a>04427 <span class="preprocessor">#define GPIO_PUPDR_PUPDR9                    ((uint32_t)0x000C0000)</span>
<a name="l04428"></a>04428 <span class="preprocessor"></span><span class="preprocessor">#define GPIO_PUPDR_PUPDR9_0                  ((uint32_t)0x00040000)</span>
<a name="l04429"></a>04429 <span class="preprocessor"></span><span class="preprocessor">#define GPIO_PUPDR_PUPDR9_1                  ((uint32_t)0x00080000)</span>
<a name="l04430"></a>04430 <span class="preprocessor"></span>
<a name="l04431"></a>04431 <span class="preprocessor">#define GPIO_PUPDR_PUPDR10                   ((uint32_t)0x00300000)</span>
<a name="l04432"></a>04432 <span class="preprocessor"></span><span class="preprocessor">#define GPIO_PUPDR_PUPDR10_0                 ((uint32_t)0x00100000)</span>
<a name="l04433"></a>04433 <span class="preprocessor"></span><span class="preprocessor">#define GPIO_PUPDR_PUPDR10_1                 ((uint32_t)0x00200000)</span>
<a name="l04434"></a>04434 <span class="preprocessor"></span>
<a name="l04435"></a>04435 <span class="preprocessor">#define GPIO_PUPDR_PUPDR11                   ((uint32_t)0x00C00000)</span>
<a name="l04436"></a>04436 <span class="preprocessor"></span><span class="preprocessor">#define GPIO_PUPDR_PUPDR11_0                 ((uint32_t)0x00400000)</span>
<a name="l04437"></a>04437 <span class="preprocessor"></span><span class="preprocessor">#define GPIO_PUPDR_PUPDR11_1                 ((uint32_t)0x00800000)</span>
<a name="l04438"></a>04438 <span class="preprocessor"></span>
<a name="l04439"></a>04439 <span class="preprocessor">#define GPIO_PUPDR_PUPDR12                   ((uint32_t)0x03000000)</span>
<a name="l04440"></a>04440 <span class="preprocessor"></span><span class="preprocessor">#define GPIO_PUPDR_PUPDR12_0                 ((uint32_t)0x01000000)</span>
<a name="l04441"></a>04441 <span class="preprocessor"></span><span class="preprocessor">#define GPIO_PUPDR_PUPDR12_1                 ((uint32_t)0x02000000)</span>
<a name="l04442"></a>04442 <span class="preprocessor"></span>
<a name="l04443"></a>04443 <span class="preprocessor">#define GPIO_PUPDR_PUPDR13                   ((uint32_t)0x0C000000)</span>
<a name="l04444"></a>04444 <span class="preprocessor"></span><span class="preprocessor">#define GPIO_PUPDR_PUPDR13_0                 ((uint32_t)0x04000000)</span>
<a name="l04445"></a>04445 <span class="preprocessor"></span><span class="preprocessor">#define GPIO_PUPDR_PUPDR13_1                 ((uint32_t)0x08000000)</span>
<a name="l04446"></a>04446 <span class="preprocessor"></span>
<a name="l04447"></a>04447 <span class="preprocessor">#define GPIO_PUPDR_PUPDR14                   ((uint32_t)0x30000000)</span>
<a name="l04448"></a>04448 <span class="preprocessor"></span><span class="preprocessor">#define GPIO_PUPDR_PUPDR14_0                 ((uint32_t)0x10000000)</span>
<a name="l04449"></a>04449 <span class="preprocessor"></span><span class="preprocessor">#define GPIO_PUPDR_PUPDR14_1                 ((uint32_t)0x20000000)</span>
<a name="l04450"></a>04450 <span class="preprocessor"></span>
<a name="l04451"></a>04451 <span class="preprocessor">#define GPIO_PUPDR_PUPDR15                   ((uint32_t)0xC0000000)</span>
<a name="l04452"></a>04452 <span class="preprocessor"></span><span class="preprocessor">#define GPIO_PUPDR_PUPDR15_0                 ((uint32_t)0x40000000)</span>
<a name="l04453"></a>04453 <span class="preprocessor"></span><span class="preprocessor">#define GPIO_PUPDR_PUPDR15_1                 ((uint32_t)0x80000000)</span>
<a name="l04454"></a>04454 <span class="preprocessor"></span>
<a name="l04455"></a>04455 <span class="comment">/******************  Bits definition for GPIO_IDR register  *******************/</span>
<a name="l04456"></a>04456 <span class="preprocessor">#define GPIO_IDR_IDR_0                       ((uint32_t)0x00000001)</span>
<a name="l04457"></a>04457 <span class="preprocessor"></span><span class="preprocessor">#define GPIO_IDR_IDR_1                       ((uint32_t)0x00000002)</span>
<a name="l04458"></a>04458 <span class="preprocessor"></span><span class="preprocessor">#define GPIO_IDR_IDR_2                       ((uint32_t)0x00000004)</span>
<a name="l04459"></a>04459 <span class="preprocessor"></span><span class="preprocessor">#define GPIO_IDR_IDR_3                       ((uint32_t)0x00000008)</span>
<a name="l04460"></a>04460 <span class="preprocessor"></span><span class="preprocessor">#define GPIO_IDR_IDR_4                       ((uint32_t)0x00000010)</span>
<a name="l04461"></a>04461 <span class="preprocessor"></span><span class="preprocessor">#define GPIO_IDR_IDR_5                       ((uint32_t)0x00000020)</span>
<a name="l04462"></a>04462 <span class="preprocessor"></span><span class="preprocessor">#define GPIO_IDR_IDR_6                       ((uint32_t)0x00000040)</span>
<a name="l04463"></a>04463 <span class="preprocessor"></span><span class="preprocessor">#define GPIO_IDR_IDR_7                       ((uint32_t)0x00000080)</span>
<a name="l04464"></a>04464 <span class="preprocessor"></span><span class="preprocessor">#define GPIO_IDR_IDR_8                       ((uint32_t)0x00000100)</span>
<a name="l04465"></a>04465 <span class="preprocessor"></span><span class="preprocessor">#define GPIO_IDR_IDR_9                       ((uint32_t)0x00000200)</span>
<a name="l04466"></a>04466 <span class="preprocessor"></span><span class="preprocessor">#define GPIO_IDR_IDR_10                      ((uint32_t)0x00000400)</span>
<a name="l04467"></a>04467 <span class="preprocessor"></span><span class="preprocessor">#define GPIO_IDR_IDR_11                      ((uint32_t)0x00000800)</span>
<a name="l04468"></a>04468 <span class="preprocessor"></span><span class="preprocessor">#define GPIO_IDR_IDR_12                      ((uint32_t)0x00001000)</span>
<a name="l04469"></a>04469 <span class="preprocessor"></span><span class="preprocessor">#define GPIO_IDR_IDR_13                      ((uint32_t)0x00002000)</span>
<a name="l04470"></a>04470 <span class="preprocessor"></span><span class="preprocessor">#define GPIO_IDR_IDR_14                      ((uint32_t)0x00004000)</span>
<a name="l04471"></a>04471 <span class="preprocessor"></span><span class="preprocessor">#define GPIO_IDR_IDR_15                      ((uint32_t)0x00008000)</span>
<a name="l04472"></a>04472 <span class="preprocessor"></span><span class="comment">/* Old GPIO_IDR register bits definition, maintained for legacy purpose */</span>
<a name="l04473"></a>04473 <span class="preprocessor">#define GPIO_OTYPER_IDR_0                    GPIO_IDR_IDR_0</span>
<a name="l04474"></a>04474 <span class="preprocessor"></span><span class="preprocessor">#define GPIO_OTYPER_IDR_1                    GPIO_IDR_IDR_1</span>
<a name="l04475"></a>04475 <span class="preprocessor"></span><span class="preprocessor">#define GPIO_OTYPER_IDR_2                    GPIO_IDR_IDR_2</span>
<a name="l04476"></a>04476 <span class="preprocessor"></span><span class="preprocessor">#define GPIO_OTYPER_IDR_3                    GPIO_IDR_IDR_3</span>
<a name="l04477"></a>04477 <span class="preprocessor"></span><span class="preprocessor">#define GPIO_OTYPER_IDR_4                    GPIO_IDR_IDR_4</span>
<a name="l04478"></a>04478 <span class="preprocessor"></span><span class="preprocessor">#define GPIO_OTYPER_IDR_5                    GPIO_IDR_IDR_5</span>
<a name="l04479"></a>04479 <span class="preprocessor"></span><span class="preprocessor">#define GPIO_OTYPER_IDR_6                    GPIO_IDR_IDR_6</span>
<a name="l04480"></a>04480 <span class="preprocessor"></span><span class="preprocessor">#define GPIO_OTYPER_IDR_7                    GPIO_IDR_IDR_7</span>
<a name="l04481"></a>04481 <span class="preprocessor"></span><span class="preprocessor">#define GPIO_OTYPER_IDR_8                    GPIO_IDR_IDR_8</span>
<a name="l04482"></a>04482 <span class="preprocessor"></span><span class="preprocessor">#define GPIO_OTYPER_IDR_9                    GPIO_IDR_IDR_9</span>
<a name="l04483"></a>04483 <span class="preprocessor"></span><span class="preprocessor">#define GPIO_OTYPER_IDR_10                   GPIO_IDR_IDR_10</span>
<a name="l04484"></a>04484 <span class="preprocessor"></span><span class="preprocessor">#define GPIO_OTYPER_IDR_11                   GPIO_IDR_IDR_11</span>
<a name="l04485"></a>04485 <span class="preprocessor"></span><span class="preprocessor">#define GPIO_OTYPER_IDR_12                   GPIO_IDR_IDR_12</span>
<a name="l04486"></a>04486 <span class="preprocessor"></span><span class="preprocessor">#define GPIO_OTYPER_IDR_13                   GPIO_IDR_IDR_13</span>
<a name="l04487"></a>04487 <span class="preprocessor"></span><span class="preprocessor">#define GPIO_OTYPER_IDR_14                   GPIO_IDR_IDR_14</span>
<a name="l04488"></a>04488 <span class="preprocessor"></span><span class="preprocessor">#define GPIO_OTYPER_IDR_15                   GPIO_IDR_IDR_15</span>
<a name="l04489"></a>04489 <span class="preprocessor"></span>
<a name="l04490"></a>04490 <span class="comment">/******************  Bits definition for GPIO_ODR register  *******************/</span>
<a name="l04491"></a>04491 <span class="preprocessor">#define GPIO_ODR_ODR_0                       ((uint32_t)0x00000001)</span>
<a name="l04492"></a>04492 <span class="preprocessor"></span><span class="preprocessor">#define GPIO_ODR_ODR_1                       ((uint32_t)0x00000002)</span>
<a name="l04493"></a>04493 <span class="preprocessor"></span><span class="preprocessor">#define GPIO_ODR_ODR_2                       ((uint32_t)0x00000004)</span>
<a name="l04494"></a>04494 <span class="preprocessor"></span><span class="preprocessor">#define GPIO_ODR_ODR_3                       ((uint32_t)0x00000008)</span>
<a name="l04495"></a>04495 <span class="preprocessor"></span><span class="preprocessor">#define GPIO_ODR_ODR_4                       ((uint32_t)0x00000010)</span>
<a name="l04496"></a>04496 <span class="preprocessor"></span><span class="preprocessor">#define GPIO_ODR_ODR_5                       ((uint32_t)0x00000020)</span>
<a name="l04497"></a>04497 <span class="preprocessor"></span><span class="preprocessor">#define GPIO_ODR_ODR_6                       ((uint32_t)0x00000040)</span>
<a name="l04498"></a>04498 <span class="preprocessor"></span><span class="preprocessor">#define GPIO_ODR_ODR_7                       ((uint32_t)0x00000080)</span>
<a name="l04499"></a>04499 <span class="preprocessor"></span><span class="preprocessor">#define GPIO_ODR_ODR_8                       ((uint32_t)0x00000100)</span>
<a name="l04500"></a>04500 <span class="preprocessor"></span><span class="preprocessor">#define GPIO_ODR_ODR_9                       ((uint32_t)0x00000200)</span>
<a name="l04501"></a>04501 <span class="preprocessor"></span><span class="preprocessor">#define GPIO_ODR_ODR_10                      ((uint32_t)0x00000400)</span>
<a name="l04502"></a>04502 <span class="preprocessor"></span><span class="preprocessor">#define GPIO_ODR_ODR_11                      ((uint32_t)0x00000800)</span>
<a name="l04503"></a>04503 <span class="preprocessor"></span><span class="preprocessor">#define GPIO_ODR_ODR_12                      ((uint32_t)0x00001000)</span>
<a name="l04504"></a>04504 <span class="preprocessor"></span><span class="preprocessor">#define GPIO_ODR_ODR_13                      ((uint32_t)0x00002000)</span>
<a name="l04505"></a>04505 <span class="preprocessor"></span><span class="preprocessor">#define GPIO_ODR_ODR_14                      ((uint32_t)0x00004000)</span>
<a name="l04506"></a>04506 <span class="preprocessor"></span><span class="preprocessor">#define GPIO_ODR_ODR_15                      ((uint32_t)0x00008000)</span>
<a name="l04507"></a>04507 <span class="preprocessor"></span><span class="comment">/* Old GPIO_ODR register bits definition, maintained for legacy purpose */</span>
<a name="l04508"></a>04508 <span class="preprocessor">#define GPIO_OTYPER_ODR_0                    GPIO_ODR_ODR_0</span>
<a name="l04509"></a>04509 <span class="preprocessor"></span><span class="preprocessor">#define GPIO_OTYPER_ODR_1                    GPIO_ODR_ODR_1</span>
<a name="l04510"></a>04510 <span class="preprocessor"></span><span class="preprocessor">#define GPIO_OTYPER_ODR_2                    GPIO_ODR_ODR_2</span>
<a name="l04511"></a>04511 <span class="preprocessor"></span><span class="preprocessor">#define GPIO_OTYPER_ODR_3                    GPIO_ODR_ODR_3</span>
<a name="l04512"></a>04512 <span class="preprocessor"></span><span class="preprocessor">#define GPIO_OTYPER_ODR_4                    GPIO_ODR_ODR_4</span>
<a name="l04513"></a>04513 <span class="preprocessor"></span><span class="preprocessor">#define GPIO_OTYPER_ODR_5                    GPIO_ODR_ODR_5</span>
<a name="l04514"></a>04514 <span class="preprocessor"></span><span class="preprocessor">#define GPIO_OTYPER_ODR_6                    GPIO_ODR_ODR_6</span>
<a name="l04515"></a>04515 <span class="preprocessor"></span><span class="preprocessor">#define GPIO_OTYPER_ODR_7                    GPIO_ODR_ODR_7</span>
<a name="l04516"></a>04516 <span class="preprocessor"></span><span class="preprocessor">#define GPIO_OTYPER_ODR_8                    GPIO_ODR_ODR_8</span>
<a name="l04517"></a>04517 <span class="preprocessor"></span><span class="preprocessor">#define GPIO_OTYPER_ODR_9                    GPIO_ODR_ODR_9</span>
<a name="l04518"></a>04518 <span class="preprocessor"></span><span class="preprocessor">#define GPIO_OTYPER_ODR_10                   GPIO_ODR_ODR_10</span>
<a name="l04519"></a>04519 <span class="preprocessor"></span><span class="preprocessor">#define GPIO_OTYPER_ODR_11                   GPIO_ODR_ODR_11</span>
<a name="l04520"></a>04520 <span class="preprocessor"></span><span class="preprocessor">#define GPIO_OTYPER_ODR_12                   GPIO_ODR_ODR_12</span>
<a name="l04521"></a>04521 <span class="preprocessor"></span><span class="preprocessor">#define GPIO_OTYPER_ODR_13                   GPIO_ODR_ODR_13</span>
<a name="l04522"></a>04522 <span class="preprocessor"></span><span class="preprocessor">#define GPIO_OTYPER_ODR_14                   GPIO_ODR_ODR_14</span>
<a name="l04523"></a>04523 <span class="preprocessor"></span><span class="preprocessor">#define GPIO_OTYPER_ODR_15                   GPIO_ODR_ODR_15</span>
<a name="l04524"></a>04524 <span class="preprocessor"></span>
<a name="l04525"></a>04525 <span class="comment">/******************  Bits definition for GPIO_BSRR register  ******************/</span>
<a name="l04526"></a>04526 <span class="preprocessor">#define GPIO_BSRR_BS_0                       ((uint32_t)0x00000001)</span>
<a name="l04527"></a>04527 <span class="preprocessor"></span><span class="preprocessor">#define GPIO_BSRR_BS_1                       ((uint32_t)0x00000002)</span>
<a name="l04528"></a>04528 <span class="preprocessor"></span><span class="preprocessor">#define GPIO_BSRR_BS_2                       ((uint32_t)0x00000004)</span>
<a name="l04529"></a>04529 <span class="preprocessor"></span><span class="preprocessor">#define GPIO_BSRR_BS_3                       ((uint32_t)0x00000008)</span>
<a name="l04530"></a>04530 <span class="preprocessor"></span><span class="preprocessor">#define GPIO_BSRR_BS_4                       ((uint32_t)0x00000010)</span>
<a name="l04531"></a>04531 <span class="preprocessor"></span><span class="preprocessor">#define GPIO_BSRR_BS_5                       ((uint32_t)0x00000020)</span>
<a name="l04532"></a>04532 <span class="preprocessor"></span><span class="preprocessor">#define GPIO_BSRR_BS_6                       ((uint32_t)0x00000040)</span>
<a name="l04533"></a>04533 <span class="preprocessor"></span><span class="preprocessor">#define GPIO_BSRR_BS_7                       ((uint32_t)0x00000080)</span>
<a name="l04534"></a>04534 <span class="preprocessor"></span><span class="preprocessor">#define GPIO_BSRR_BS_8                       ((uint32_t)0x00000100)</span>
<a name="l04535"></a>04535 <span class="preprocessor"></span><span class="preprocessor">#define GPIO_BSRR_BS_9                       ((uint32_t)0x00000200)</span>
<a name="l04536"></a>04536 <span class="preprocessor"></span><span class="preprocessor">#define GPIO_BSRR_BS_10                      ((uint32_t)0x00000400)</span>
<a name="l04537"></a>04537 <span class="preprocessor"></span><span class="preprocessor">#define GPIO_BSRR_BS_11                      ((uint32_t)0x00000800)</span>
<a name="l04538"></a>04538 <span class="preprocessor"></span><span class="preprocessor">#define GPIO_BSRR_BS_12                      ((uint32_t)0x00001000)</span>
<a name="l04539"></a>04539 <span class="preprocessor"></span><span class="preprocessor">#define GPIO_BSRR_BS_13                      ((uint32_t)0x00002000)</span>
<a name="l04540"></a>04540 <span class="preprocessor"></span><span class="preprocessor">#define GPIO_BSRR_BS_14                      ((uint32_t)0x00004000)</span>
<a name="l04541"></a>04541 <span class="preprocessor"></span><span class="preprocessor">#define GPIO_BSRR_BS_15                      ((uint32_t)0x00008000)</span>
<a name="l04542"></a>04542 <span class="preprocessor"></span><span class="preprocessor">#define GPIO_BSRR_BR_0                       ((uint32_t)0x00010000)</span>
<a name="l04543"></a>04543 <span class="preprocessor"></span><span class="preprocessor">#define GPIO_BSRR_BR_1                       ((uint32_t)0x00020000)</span>
<a name="l04544"></a>04544 <span class="preprocessor"></span><span class="preprocessor">#define GPIO_BSRR_BR_2                       ((uint32_t)0x00040000)</span>
<a name="l04545"></a>04545 <span class="preprocessor"></span><span class="preprocessor">#define GPIO_BSRR_BR_3                       ((uint32_t)0x00080000)</span>
<a name="l04546"></a>04546 <span class="preprocessor"></span><span class="preprocessor">#define GPIO_BSRR_BR_4                       ((uint32_t)0x00100000)</span>
<a name="l04547"></a>04547 <span class="preprocessor"></span><span class="preprocessor">#define GPIO_BSRR_BR_5                       ((uint32_t)0x00200000)</span>
<a name="l04548"></a>04548 <span class="preprocessor"></span><span class="preprocessor">#define GPIO_BSRR_BR_6                       ((uint32_t)0x00400000)</span>
<a name="l04549"></a>04549 <span class="preprocessor"></span><span class="preprocessor">#define GPIO_BSRR_BR_7                       ((uint32_t)0x00800000)</span>
<a name="l04550"></a>04550 <span class="preprocessor"></span><span class="preprocessor">#define GPIO_BSRR_BR_8                       ((uint32_t)0x01000000)</span>
<a name="l04551"></a>04551 <span class="preprocessor"></span><span class="preprocessor">#define GPIO_BSRR_BR_9                       ((uint32_t)0x02000000)</span>
<a name="l04552"></a>04552 <span class="preprocessor"></span><span class="preprocessor">#define GPIO_BSRR_BR_10                      ((uint32_t)0x04000000)</span>
<a name="l04553"></a>04553 <span class="preprocessor"></span><span class="preprocessor">#define GPIO_BSRR_BR_11                      ((uint32_t)0x08000000)</span>
<a name="l04554"></a>04554 <span class="preprocessor"></span><span class="preprocessor">#define GPIO_BSRR_BR_12                      ((uint32_t)0x10000000)</span>
<a name="l04555"></a>04555 <span class="preprocessor"></span><span class="preprocessor">#define GPIO_BSRR_BR_13                      ((uint32_t)0x20000000)</span>
<a name="l04556"></a>04556 <span class="preprocessor"></span><span class="preprocessor">#define GPIO_BSRR_BR_14                      ((uint32_t)0x40000000)</span>
<a name="l04557"></a>04557 <span class="preprocessor"></span><span class="preprocessor">#define GPIO_BSRR_BR_15                      ((uint32_t)0x80000000)</span>
<a name="l04558"></a>04558 <span class="preprocessor"></span>
<a name="l04559"></a>04559 <span class="comment">/******************************************************************************/</span>
<a name="l04560"></a>04560 <span class="comment">/*                                                                            */</span>
<a name="l04561"></a>04561 <span class="comment">/*                                    HASH                                    */</span>
<a name="l04562"></a>04562 <span class="comment">/*                                                                            */</span>
<a name="l04563"></a>04563 <span class="comment">/******************************************************************************/</span>
<a name="l04564"></a>04564 <span class="comment">/******************  Bits definition for HASH_CR register  ********************/</span>
<a name="l04565"></a>04565 <span class="preprocessor">#define HASH_CR_INIT                         ((uint32_t)0x00000004)</span>
<a name="l04566"></a>04566 <span class="preprocessor"></span><span class="preprocessor">#define HASH_CR_DMAE                         ((uint32_t)0x00000008)</span>
<a name="l04567"></a>04567 <span class="preprocessor"></span><span class="preprocessor">#define HASH_CR_DATATYPE                     ((uint32_t)0x00000030)</span>
<a name="l04568"></a>04568 <span class="preprocessor"></span><span class="preprocessor">#define HASH_CR_DATATYPE_0                   ((uint32_t)0x00000010)</span>
<a name="l04569"></a>04569 <span class="preprocessor"></span><span class="preprocessor">#define HASH_CR_DATATYPE_1                   ((uint32_t)0x00000020)</span>
<a name="l04570"></a>04570 <span class="preprocessor"></span><span class="preprocessor">#define HASH_CR_MODE                         ((uint32_t)0x00000040)</span>
<a name="l04571"></a>04571 <span class="preprocessor"></span><span class="preprocessor">#define HASH_CR_ALGO                         ((uint32_t)0x00000080)</span>
<a name="l04572"></a>04572 <span class="preprocessor"></span><span class="preprocessor">#define HASH_CR_NBW                          ((uint32_t)0x00000F00)</span>
<a name="l04573"></a>04573 <span class="preprocessor"></span><span class="preprocessor">#define HASH_CR_NBW_0                        ((uint32_t)0x00000100)</span>
<a name="l04574"></a>04574 <span class="preprocessor"></span><span class="preprocessor">#define HASH_CR_NBW_1                        ((uint32_t)0x00000200)</span>
<a name="l04575"></a>04575 <span class="preprocessor"></span><span class="preprocessor">#define HASH_CR_NBW_2                        ((uint32_t)0x00000400)</span>
<a name="l04576"></a>04576 <span class="preprocessor"></span><span class="preprocessor">#define HASH_CR_NBW_3                        ((uint32_t)0x00000800)</span>
<a name="l04577"></a>04577 <span class="preprocessor"></span><span class="preprocessor">#define HASH_CR_DINNE                        ((uint32_t)0x00001000)</span>
<a name="l04578"></a>04578 <span class="preprocessor"></span><span class="preprocessor">#define HASH_CR_LKEY                         ((uint32_t)0x00010000)</span>
<a name="l04579"></a>04579 <span class="preprocessor"></span>
<a name="l04580"></a>04580 <span class="comment">/******************  Bits definition for HASH_STR register  *******************/</span>
<a name="l04581"></a>04581 <span class="preprocessor">#define HASH_STR_NBW                         ((uint32_t)0x0000001F)</span>
<a name="l04582"></a>04582 <span class="preprocessor"></span><span class="preprocessor">#define HASH_STR_NBW_0                       ((uint32_t)0x00000001)</span>
<a name="l04583"></a>04583 <span class="preprocessor"></span><span class="preprocessor">#define HASH_STR_NBW_1                       ((uint32_t)0x00000002)</span>
<a name="l04584"></a>04584 <span class="preprocessor"></span><span class="preprocessor">#define HASH_STR_NBW_2                       ((uint32_t)0x00000004)</span>
<a name="l04585"></a>04585 <span class="preprocessor"></span><span class="preprocessor">#define HASH_STR_NBW_3                       ((uint32_t)0x00000008)</span>
<a name="l04586"></a>04586 <span class="preprocessor"></span><span class="preprocessor">#define HASH_STR_NBW_4                       ((uint32_t)0x00000010)</span>
<a name="l04587"></a>04587 <span class="preprocessor"></span><span class="preprocessor">#define HASH_STR_DCAL                        ((uint32_t)0x00000100)</span>
<a name="l04588"></a>04588 <span class="preprocessor"></span>
<a name="l04589"></a>04589 <span class="comment">/******************  Bits definition for HASH_IMR register  *******************/</span>
<a name="l04590"></a>04590 <span class="preprocessor">#define HASH_IMR_DINIM                       ((uint32_t)0x00000001)</span>
<a name="l04591"></a>04591 <span class="preprocessor"></span><span class="preprocessor">#define HASH_IMR_DCIM                        ((uint32_t)0x00000002)</span>
<a name="l04592"></a>04592 <span class="preprocessor"></span>
<a name="l04593"></a>04593 <span class="comment">/******************  Bits definition for HASH_SR register  ********************/</span>
<a name="l04594"></a>04594 <span class="preprocessor">#define HASH_SR_DINIS                        ((uint32_t)0x00000001)</span>
<a name="l04595"></a>04595 <span class="preprocessor"></span><span class="preprocessor">#define HASH_SR_DCIS                         ((uint32_t)0x00000002)</span>
<a name="l04596"></a>04596 <span class="preprocessor"></span><span class="preprocessor">#define HASH_SR_DMAS                         ((uint32_t)0x00000004)</span>
<a name="l04597"></a>04597 <span class="preprocessor"></span><span class="preprocessor">#define HASH_SR_BUSY                         ((uint32_t)0x00000008)</span>
<a name="l04598"></a>04598 <span class="preprocessor"></span>
<a name="l04599"></a>04599 <span class="comment">/******************************************************************************/</span>
<a name="l04600"></a>04600 <span class="comment">/*                                                                            */</span>
<a name="l04601"></a>04601 <span class="comment">/*                      Inter-integrated Circuit Interface                    */</span>
<a name="l04602"></a>04602 <span class="comment">/*                                                                            */</span>
<a name="l04603"></a>04603 <span class="comment">/******************************************************************************/</span>
<a name="l04604"></a>04604 <span class="comment">/*******************  Bit definition for I2C_CR1 register  ********************/</span>
<a name="l04605"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga953b0d38414808db79da116842ed3262">04605</a> <span class="preprocessor">#define  I2C_CR1_PE                          ((uint16_t)0x0001)            </span>
<a name="l04606"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga4cfee7b020a49bd037fa7cf27c796abc">04606</a> <span class="preprocessor">#define  I2C_CR1_SMBUS                       ((uint16_t)0x0002)            </span>
<a name="l04607"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga001198ff898802888edf58f56d5371c9">04607</a> <span class="preprocessor">#define  I2C_CR1_SMBTYPE                     ((uint16_t)0x0008)            </span>
<a name="l04608"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga4598185d9092edfbf943464bcbb342ac">04608</a> <span class="preprocessor">#define  I2C_CR1_ENARP                       ((uint16_t)0x0010)            </span>
<a name="l04609"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga40d2eb849f9d55e6298035b61e84ca42">04609</a> <span class="preprocessor">#define  I2C_CR1_ENPEC                       ((uint16_t)0x0020)            </span>
<a name="l04610"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga1d8c219193b11f8507d7b85831d14912">04610</a> <span class="preprocessor">#define  I2C_CR1_ENGC                        ((uint16_t)0x0040)            </span>
<a name="l04611"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga197aaca79f64e832af3a0a0864c2a08c">04611</a> <span class="preprocessor">#define  I2C_CR1_NOSTRETCH                   ((uint16_t)0x0080)            </span>
<a name="l04612"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga2ca7f18dd5bc1130dbefae4ff8736143">04612</a> <span class="preprocessor">#define  I2C_CR1_START                       ((uint16_t)0x0100)            </span>
<a name="l04613"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gace70293f3dfa24d448b600fc58e45223">04613</a> <span class="preprocessor">#define  I2C_CR1_STOP                        ((uint16_t)0x0200)            </span>
<a name="l04614"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaf933b105259a4bc46a957576adb8d96d">04614</a> <span class="preprocessor">#define  I2C_CR1_ACK                         ((uint16_t)0x0400)            </span>
<a name="l04615"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga34721958229a5983f2e95dfeaa8e55c3">04615</a> <span class="preprocessor">#define  I2C_CR1_POS                         ((uint16_t)0x0800)            </span>
<a name="l04616"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gab4d0119253d93a106b5ca704e5020c12">04616</a> <span class="preprocessor">#define  I2C_CR1_PEC                         ((uint16_t)0x1000)            </span>
<a name="l04617"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga56729ccf93c5d9f5b5b05002e3a2323c">04617</a> <span class="preprocessor">#define  I2C_CR1_ALERT                       ((uint16_t)0x2000)            </span>
<a name="l04618"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga8dc661ef13da02e5bcb943f2003d576d">04618</a> <span class="preprocessor">#define  I2C_CR1_SWRST                       ((uint16_t)0x8000)            </span>
<a name="l04620"></a>04620 <span class="preprocessor"></span><span class="comment">/*******************  Bit definition for I2C_CR2 register  ********************/</span>
<a name="l04621"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga293fbe15ed5fd1fc95915bd6437859e7">04621</a> <span class="preprocessor">#define  I2C_CR2_FREQ                        ((uint16_t)0x003F)            </span>
<a name="l04622"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga09d944f5260f40a0eb714d41859e0d23">04622</a> <span class="preprocessor">#define  I2C_CR2_FREQ_0                      ((uint16_t)0x0001)            </span>
<a name="l04623"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga25ab0ef2a7795e3326900b277479d89c">04623</a> <span class="preprocessor">#define  I2C_CR2_FREQ_1                      ((uint16_t)0x0002)            </span>
<a name="l04624"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga657af5a02534cc900cbddc260319d845">04624</a> <span class="preprocessor">#define  I2C_CR2_FREQ_2                      ((uint16_t)0x0004)            </span>
<a name="l04625"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga655214f8327fd1322998c9d8bffe308d">04625</a> <span class="preprocessor">#define  I2C_CR2_FREQ_3                      ((uint16_t)0x0008)            </span>
<a name="l04626"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga3382a7262743bc824985af7339449386">04626</a> <span class="preprocessor">#define  I2C_CR2_FREQ_4                      ((uint16_t)0x0010)            </span>
<a name="l04627"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gad3b1a2b777fcf158c9e4264485682a20">04627</a> <span class="preprocessor">#define  I2C_CR2_FREQ_5                      ((uint16_t)0x0020)            </span>
<a name="l04629"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga6f14ae48e4609c2b3645211234cba974">04629</a> <span class="preprocessor">#define  I2C_CR2_ITERREN                     ((uint16_t)0x0100)            </span>
<a name="l04630"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga3b1ebaf8173090ec469b055b98e585d2">04630</a> <span class="preprocessor">#define  I2C_CR2_ITEVTEN                     ((uint16_t)0x0200)            </span>
<a name="l04631"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga2efbe5d96ed0ce447a45a62e8317a68a">04631</a> <span class="preprocessor">#define  I2C_CR2_ITBUFEN                     ((uint16_t)0x0400)            </span>
<a name="l04632"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gadb81d5c91486b873bd0bf279a4ffcf69">04632</a> <span class="preprocessor">#define  I2C_CR2_DMAEN                       ((uint16_t)0x0800)            </span>
<a name="l04633"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga6a0955008cbabbb6b726ba0b4f8da609">04633</a> <span class="preprocessor">#define  I2C_CR2_LAST                        ((uint16_t)0x1000)            </span>
<a name="l04635"></a>04635 <span class="preprocessor"></span><span class="comment">/*******************  Bit definition for I2C_OAR1 register  *******************/</span>
<a name="l04636"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga8250616a993a5f2bb04cd0f116005864">04636</a> <span class="preprocessor">#define  I2C_OAR1_ADD1_7                     ((uint16_t)0x00FE)            </span>
<a name="l04637"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gab8141dcd63a8429a64d488cc78ef3ec1">04637</a> <span class="preprocessor">#define  I2C_OAR1_ADD8_9                     ((uint16_t)0x0300)            </span>
<a name="l04639"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga8b7c20c81f79d17921718412b8fca6d7">04639</a> <span class="preprocessor">#define  I2C_OAR1_ADD0                       ((uint16_t)0x0001)            </span>
<a name="l04640"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga499a61f0013c5c6fe38b848901f58769">04640</a> <span class="preprocessor">#define  I2C_OAR1_ADD1                       ((uint16_t)0x0002)            </span>
<a name="l04641"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gab44a263e36a7f34d922ff124aebd99c3">04641</a> <span class="preprocessor">#define  I2C_OAR1_ADD2                       ((uint16_t)0x0004)            </span>
<a name="l04642"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga9584dca3b1b414a63cf7ba75e557155b">04642</a> <span class="preprocessor">#define  I2C_OAR1_ADD3                       ((uint16_t)0x0008)            </span>
<a name="l04643"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga110b915b907f4bf29ff03da1f077bd97">04643</a> <span class="preprocessor">#define  I2C_OAR1_ADD4                       ((uint16_t)0x0010)            </span>
<a name="l04644"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga0856dee2657cf0a04d79084da86988ca">04644</a> <span class="preprocessor">#define  I2C_OAR1_ADD5                       ((uint16_t)0x0020)            </span>
<a name="l04645"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga5507af6154f60125dadc4654f57776ca">04645</a> <span class="preprocessor">#define  I2C_OAR1_ADD6                       ((uint16_t)0x0040)            </span>
<a name="l04646"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaca710515f0aac5abdac02a630e09097c">04646</a> <span class="preprocessor">#define  I2C_OAR1_ADD7                       ((uint16_t)0x0080)            </span>
<a name="l04647"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gab945eba8b842a253cc64cce722537264">04647</a> <span class="preprocessor">#define  I2C_OAR1_ADD8                       ((uint16_t)0x0100)            </span>
<a name="l04648"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga10cf2dfc6b1ed55413be06acca413430">04648</a> <span class="preprocessor">#define  I2C_OAR1_ADD9                       ((uint16_t)0x0200)            </span>
<a name="l04650"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga7d8df80cd27313c896e887aae81fa639">04650</a> <span class="preprocessor">#define  I2C_OAR1_ADDMODE                    ((uint16_t)0x8000)            </span>
<a name="l04652"></a>04652 <span class="preprocessor"></span><span class="comment">/*******************  Bit definition for I2C_OAR2 register  *******************/</span>
<a name="l04653"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gab83ed1ee64439cb2734a708445f37e94">04653</a> <span class="preprocessor">#define  I2C_OAR2_ENDUAL                     ((uint8_t)0x01)               </span>
<a name="l04654"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gadd3d8fd1de1f16d051efb52dd3d657c4">04654</a> <span class="preprocessor">#define  I2C_OAR2_ADD2                       ((uint8_t)0xFE)               </span>
<a name="l04656"></a>04656 <span class="preprocessor"></span><span class="comment">/********************  Bit definition for I2C_DR register  ********************/</span>
<a name="l04657"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gac43021a4a7f79672d27c36a469b301d5">04657</a> <span class="preprocessor">#define  I2C_DR_DR                           ((uint8_t)0xFF)               </span>
<a name="l04659"></a>04659 <span class="preprocessor"></span><span class="comment">/*******************  Bit definition for I2C_SR1 register  ********************/</span>
<a name="l04660"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga6935c920da59d755d0cf834548a70ec4">04660</a> <span class="preprocessor">#define  I2C_SR1_SB                          ((uint16_t)0x0001)            </span>
<a name="l04661"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga3db361a4d9dd84b187085a11d933b45d">04661</a> <span class="preprocessor">#define  I2C_SR1_ADDR                        ((uint16_t)0x0002)            </span>
<a name="l04662"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gafb279f85d78cfe5abd3eeb0b40a65ab1">04662</a> <span class="preprocessor">#define  I2C_SR1_BTF                         ((uint16_t)0x0004)            </span>
<a name="l04663"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga6faaa55a1e48aa7c1f2b69669901445d">04663</a> <span class="preprocessor">#define  I2C_SR1_ADD10                       ((uint16_t)0x0008)            </span>
<a name="l04664"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaafcea4cdbe2f6da31566c897fa893a7c">04664</a> <span class="preprocessor">#define  I2C_SR1_STOPF                       ((uint16_t)0x0010)            </span>
<a name="l04665"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaf6ebe33c992611bc2e25bbb01c1441a5">04665</a> <span class="preprocessor">#define  I2C_SR1_RXNE                        ((uint16_t)0x0040)            </span>
<a name="l04666"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gafdc4da49c163910203255e384591b6f7">04666</a> <span class="preprocessor">#define  I2C_SR1_TXE                         ((uint16_t)0x0080)            </span>
<a name="l04667"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga1d12990c90ab0757dcfea150ea50b227">04667</a> <span class="preprocessor">#define  I2C_SR1_BERR                        ((uint16_t)0x0100)            </span>
<a name="l04668"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gacbc52f6ec6172c71d8b026a22c2f69d2">04668</a> <span class="preprocessor">#define  I2C_SR1_ARLO                        ((uint16_t)0x0200)            </span>
<a name="l04669"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga62aa2496d4b3955214a16a7bd998fd88">04669</a> <span class="preprocessor">#define  I2C_SR1_AF                          ((uint16_t)0x0400)            </span>
<a name="l04670"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gad42d2435d2e64bf710c701c9b17adfb4">04670</a> <span class="preprocessor">#define  I2C_SR1_OVR                         ((uint16_t)0x0800)            </span>
<a name="l04671"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga4b2976279024e832e53ad12796a7bb71">04671</a> <span class="preprocessor">#define  I2C_SR1_PECERR                      ((uint16_t)0x1000)            </span>
<a name="l04672"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaef3a1e4921d7c509d1b639c67882c4c9">04672</a> <span class="preprocessor">#define  I2C_SR1_TIMEOUT                     ((uint16_t)0x4000)            </span>
<a name="l04673"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga8df36c38deb8791d0ac3cb5881298c1c">04673</a> <span class="preprocessor">#define  I2C_SR1_SMBALERT                    ((uint16_t)0x8000)            </span>
<a name="l04675"></a>04675 <span class="preprocessor"></span><span class="comment">/*******************  Bit definition for I2C_SR2 register  ********************/</span>
<a name="l04676"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga75cc361adf0e72e33d6771ebfa17b52d">04676</a> <span class="preprocessor">#define  I2C_SR2_MSL                         ((uint16_t)0x0001)            </span>
<a name="l04677"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga3b1e75a82da73ae2873cff1cd27c3179">04677</a> <span class="preprocessor">#define  I2C_SR2_BUSY                        ((uint16_t)0x0002)            </span>
<a name="l04678"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga288b20416b42a79e591aa80d9a690fca">04678</a> <span class="preprocessor">#define  I2C_SR2_TRA                         ((uint16_t)0x0004)            </span>
<a name="l04679"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaf3aeb79cbe04f7ec1e3c2615921c4fab">04679</a> <span class="preprocessor">#define  I2C_SR2_GENCALL                     ((uint16_t)0x0010)            </span>
<a name="l04680"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gafcf50334903013177a8c6f4e36b8d6fe">04680</a> <span class="preprocessor">#define  I2C_SR2_SMBDEFAULT                  ((uint16_t)0x0020)            </span>
<a name="l04681"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaa07cf3e404f9f57e98d1ba3793079c80">04681</a> <span class="preprocessor">#define  I2C_SR2_SMBHOST                     ((uint16_t)0x0040)            </span>
<a name="l04682"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga79a6a21835e06d9bc48009f4269b7798">04682</a> <span class="preprocessor">#define  I2C_SR2_DUALF                       ((uint16_t)0x0080)            </span>
<a name="l04683"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga4a4fd5d9c9e2593be920d19a5f6ae732">04683</a> <span class="preprocessor">#define  I2C_SR2_PEC                         ((uint16_t)0xFF00)            </span>
<a name="l04685"></a>04685 <span class="preprocessor"></span><span class="comment">/*******************  Bit definition for I2C_CCR register  ********************/</span>
<a name="l04686"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga5c8cb2bd83dd7dbdcf6ca4bbf4a841de">04686</a> <span class="preprocessor">#define  I2C_CCR_CCR                         ((uint16_t)0x0FFF)            </span>
<a name="l04687"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga851c8a6b598d54c1a805b1632a4078e5">04687</a> <span class="preprocessor">#define  I2C_CCR_DUTY                        ((uint16_t)0x4000)            </span>
<a name="l04688"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaea64e5d7eba609ac9a84964bc0bc2def">04688</a> <span class="preprocessor">#define  I2C_CCR_FS                          ((uint16_t)0x8000)            </span>
<a name="l04690"></a>04690 <span class="preprocessor"></span><span class="comment">/******************  Bit definition for I2C_TRISE register  *******************/</span>
<a name="l04691"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaff77a39aba630647af62dc7f1a5dc218">04691</a> <span class="preprocessor">#define  I2C_TRISE_TRISE                     ((uint8_t)0x3F)               </span>
<a name="l04693"></a>04693 <span class="preprocessor"></span><span class="comment">/******************************************************************************/</span>
<a name="l04694"></a>04694 <span class="comment">/*                                                                            */</span>
<a name="l04695"></a>04695 <span class="comment">/*                           Independent WATCHDOG                             */</span>
<a name="l04696"></a>04696 <span class="comment">/*                                                                            */</span>
<a name="l04697"></a>04697 <span class="comment">/******************************************************************************/</span>
<a name="l04698"></a>04698 <span class="comment">/*******************  Bit definition for IWDG_KR register  ********************/</span>
<a name="l04699"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga957f7d5f8a0ec1a6956a7f05cfbd97c2">04699</a> <span class="preprocessor">#define  IWDG_KR_KEY                         ((uint16_t)0xFFFF)            </span>
<a name="l04701"></a>04701 <span class="preprocessor"></span><span class="comment">/*******************  Bit definition for IWDG_PR register  ********************/</span>
<a name="l04702"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga4de39c5672f17d326fceb5adc9adc090">04702</a> <span class="preprocessor">#define  IWDG_PR_PR                          ((uint8_t)0x07)               </span>
<a name="l04703"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga9b727e7882603df1684cbf230520ca76">04703</a> <span class="preprocessor">#define  IWDG_PR_PR_0                        ((uint8_t)0x01)               </span>
<a name="l04704"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gafba2551b90c68d95c736a116224b473e">04704</a> <span class="preprocessor">#define  IWDG_PR_PR_1                        ((uint8_t)0x02)               </span>
<a name="l04705"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga55a1d7fde4e3e724a8644652ba9bb2b9">04705</a> <span class="preprocessor">#define  IWDG_PR_PR_2                        ((uint8_t)0x04)               </span>
<a name="l04707"></a>04707 <span class="preprocessor"></span><span class="comment">/*******************  Bit definition for IWDG_RLR register  *******************/</span>
<a name="l04708"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga87024bbb19f26def4c4c1510b22d3033">04708</a> <span class="preprocessor">#define  IWDG_RLR_RL                         ((uint16_t)0x0FFF)            </span>
<a name="l04710"></a>04710 <span class="preprocessor"></span><span class="comment">/*******************  Bit definition for IWDG_SR register  ********************/</span>
<a name="l04711"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga269bd5618ba773d32275b93be004c554">04711</a> <span class="preprocessor">#define  IWDG_SR_PVU                         ((uint8_t)0x01)               </span>
<a name="l04712"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gadffb8339e556a3b10120b15f0dacc232">04712</a> <span class="preprocessor">#define  IWDG_SR_RVU                         ((uint8_t)0x02)               </span>
<a name="l04714"></a>04714 <span class="preprocessor"></span><span class="comment">/******************************************************************************/</span>
<a name="l04715"></a>04715 <span class="comment">/*                                                                            */</span>
<a name="l04716"></a>04716 <span class="comment">/*                             Power Control                                  */</span>
<a name="l04717"></a>04717 <span class="comment">/*                                                                            */</span>
<a name="l04718"></a>04718 <span class="comment">/******************************************************************************/</span>
<a name="l04719"></a>04719 <span class="comment">/********************  Bit definition for PWR_CR register  ********************/</span>
<a name="l04720"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga3aeb8d6f2539b0a3a4b851aeba0eea66">04720</a> <span class="preprocessor">#define  PWR_CR_LPDS                         ((uint16_t)0x0001)     </span>
<a name="l04721"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga8c8075e98772470804c9e3fe74984115">04721</a> <span class="preprocessor">#define  PWR_CR_PDDS                         ((uint16_t)0x0002)     </span>
<a name="l04722"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga3928de64f633b84770b1cfecea702fa7">04722</a> <span class="preprocessor">#define  PWR_CR_CWUF                         ((uint16_t)0x0004)     </span>
<a name="l04723"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gab44484cacc35c80cf82eb011d6cbe13a">04723</a> <span class="preprocessor">#define  PWR_CR_CSBF                         ((uint16_t)0x0008)     </span>
<a name="l04724"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga05d5c39759e69a294c0ab9bea8f142e5">04724</a> <span class="preprocessor">#define  PWR_CR_PVDE                         ((uint16_t)0x0010)     </span>
<a name="l04726"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gac73c24d43953c7598e42acdd4c4e7435">04726</a> <span class="preprocessor">#define  PWR_CR_PLS                          ((uint16_t)0x00E0)     </span>
<a name="l04727"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gacef447510818c468c202e3b4991ea08e">04727</a> <span class="preprocessor">#define  PWR_CR_PLS_0                        ((uint16_t)0x0020)     </span>
<a name="l04728"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gafcd19d78943514a2f695a39b45594623">04728</a> <span class="preprocessor">#define  PWR_CR_PLS_1                        ((uint16_t)0x0040)     </span>
<a name="l04729"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga1a8986ee557f443d4a8eebf68026bd52">04729</a> <span class="preprocessor">#define  PWR_CR_PLS_2                        ((uint16_t)0x0080)     </span>
<a name="l04733"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gacb6b904b20d7e4fff958c75748861216">04733</a> <span class="preprocessor">#define  PWR_CR_PLS_LEV0                     ((uint16_t)0x0000)     </span>
<a name="l04734"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga15b71263f73f0c4e53ca91fc8d096818">04734</a> <span class="preprocessor">#define  PWR_CR_PLS_LEV1                     ((uint16_t)0x0020)     </span>
<a name="l04735"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga2ea128abc2fc4252b53d09ca2850e69e">04735</a> <span class="preprocessor">#define  PWR_CR_PLS_LEV2                     ((uint16_t)0x0040)     </span>
<a name="l04736"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga9c1782980a2fb12de80058729a74f174">04736</a> <span class="preprocessor">#define  PWR_CR_PLS_LEV3                     ((uint16_t)0x0060)     </span>
<a name="l04737"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga0fe79f097ea6c30a4ccf69ed3e177f85">04737</a> <span class="preprocessor">#define  PWR_CR_PLS_LEV4                     ((uint16_t)0x0080)     </span>
<a name="l04738"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga326781d09a07b4d215424fbbae11b7b2">04738</a> <span class="preprocessor">#define  PWR_CR_PLS_LEV5                     ((uint16_t)0x00A0)     </span>
<a name="l04739"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaaff17e9c7fe7d837523b1e9a2f4e9baf">04739</a> <span class="preprocessor">#define  PWR_CR_PLS_LEV6                     ((uint16_t)0x00C0)     </span>
<a name="l04740"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga95e3b301b5470ae94d32c53a9fbdfc8b">04740</a> <span class="preprocessor">#define  PWR_CR_PLS_LEV7                     ((uint16_t)0x00E0)     </span>
<a name="l04742"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaf5c65ab845794ef48f09faa2ee44f718">04742</a> <span class="preprocessor">#define  PWR_CR_DBP                          ((uint16_t)0x0100)     </span>
<a name="l04743"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gafc01f8b6d4bd0294f745fde6d8e57002">04743</a> <span class="preprocessor">#define  PWR_CR_FPDS                         ((uint16_t)0x0200)     </span>
<a name="l04744"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaccc33f1ba4e374e116ffa50f3a503030">04744</a> <span class="preprocessor">#define  PWR_CR_VOS                          ((uint16_t)0x4000)     </span>
<a name="l04745"></a>04745 <span class="preprocessor"></span><span class="comment">/* Legacy define */</span>
<a name="l04746"></a>04746 <span class="preprocessor">#define  PWR_CR_PMODE                        PWR_CR_VOS</span>
<a name="l04747"></a>04747 <span class="preprocessor"></span>
<a name="l04748"></a>04748 <span class="comment">/*******************  Bit definition for PWR_CSR register  ********************/</span>
<a name="l04749"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga9465bb7ad9ca936688344e2a077539e6">04749</a> <span class="preprocessor">#define  PWR_CSR_WUF                         ((uint16_t)0x0001)     </span>
<a name="l04750"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gab4fd42f153660593cad6f4fe22ff76bb">04750</a> <span class="preprocessor">#define  PWR_CSR_SBF                         ((uint16_t)0x0002)     </span>
<a name="l04751"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga3535ce181895cc00afeb28dcac68d04c">04751</a> <span class="preprocessor">#define  PWR_CSR_PVDO                        ((uint16_t)0x0004)     </span>
<a name="l04752"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga939410de980c5bc297ff04bcf30875cc">04752</a> <span class="preprocessor">#define  PWR_CSR_BRR                         ((uint16_t)0x0008)     </span>
<a name="l04753"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga7ac8c15a08bbee754ea720b0d4a4f580">04753</a> <span class="preprocessor">#define  PWR_CSR_EWUP                        ((uint16_t)0x0100)     </span>
<a name="l04754"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga0f99becaceb185431dbf46fb22718d0a">04754</a> <span class="preprocessor">#define  PWR_CSR_BRE                         ((uint16_t)0x0200)     </span>
<a name="l04755"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga4126ed19cce54a5411ff8dd440171695">04755</a> <span class="preprocessor">#define  PWR_CSR_VOSRDY                      ((uint16_t)0x4000)     </span>
<a name="l04756"></a>04756 <span class="preprocessor"></span><span class="comment">/* Legacy define */</span>
<a name="l04757"></a>04757 <span class="preprocessor">#define  PWR_CSR_REGRDY                      PWR_CSR_VOSRDY</span>
<a name="l04758"></a>04758 <span class="preprocessor"></span>
<a name="l04759"></a>04759 <span class="comment">/******************************************************************************/</span>
<a name="l04760"></a>04760 <span class="comment">/*                                                                            */</span>
<a name="l04761"></a>04761 <span class="comment">/*                         Reset and Clock Control                            */</span>
<a name="l04762"></a>04762 <span class="comment">/*                                                                            */</span>
<a name="l04763"></a>04763 <span class="comment">/******************************************************************************/</span>
<a name="l04764"></a>04764 <span class="comment">/********************  Bit definition for RCC_CR register  ********************/</span>
<a name="l04765"></a>04765 <span class="preprocessor">#define  RCC_CR_HSION                        ((uint32_t)0x00000001)</span>
<a name="l04766"></a>04766 <span class="preprocessor"></span><span class="preprocessor">#define  RCC_CR_HSIRDY                       ((uint32_t)0x00000002)</span>
<a name="l04767"></a>04767 <span class="preprocessor"></span>
<a name="l04768"></a>04768 <span class="preprocessor">#define  RCC_CR_HSITRIM                      ((uint32_t)0x000000F8)</span>
<a name="l04769"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaab999bbbc1d365d0100d34eaa9f426eb">04769</a> <span class="preprocessor"></span><span class="preprocessor">#define  RCC_CR_HSITRIM_0                    ((uint32_t)0x00000008)</span>
<a name="l04770"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga569d6a29d774e0f125b0c2b3671fae3c">04770</a> <span class="preprocessor">#define  RCC_CR_HSITRIM_1                    ((uint32_t)0x00000010)</span>
<a name="l04771"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga10d80d64137e36f5183f6aa7002de6f5">04771</a> <span class="preprocessor">#define  RCC_CR_HSITRIM_2                    ((uint32_t)0x00000020)</span>
<a name="l04772"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gafe20245d2d971238dba9ee371a299ba9">04772</a> <span class="preprocessor">#define  RCC_CR_HSITRIM_3                    ((uint32_t)0x00000040)</span>
<a name="l04773"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga1f9ab2e93a0b9b70d33812bcc5e920c1">04773</a> <span class="preprocessor">#define  RCC_CR_HSITRIM_4                    ((uint32_t)0x00000080)</span>
<a name="l04775"></a>04775 <span class="preprocessor">#define  RCC_CR_HSICAL                       ((uint32_t)0x0000FF00)</span>
<a name="l04776"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gad7daa7754e54d65916ddc54f37274d3a">04776</a> <span class="preprocessor"></span><span class="preprocessor">#define  RCC_CR_HSICAL_0                     ((uint32_t)0x00000100)</span>
<a name="l04777"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga78054087161dee567cadbb4b4b96fb08">04777</a> <span class="preprocessor">#define  RCC_CR_HSICAL_1                     ((uint32_t)0x00000200)</span>
<a name="l04778"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gab0c4bac85beb7de5916897f88150dc3f">04778</a> <span class="preprocessor">#define  RCC_CR_HSICAL_2                     ((uint32_t)0x00000400)</span>
<a name="l04779"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga03f71cd53f075e9d35fcbfe7ed3f6e12">04779</a> <span class="preprocessor">#define  RCC_CR_HSICAL_3                     ((uint32_t)0x00000800)</span>
<a name="l04780"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaf26eb00e1872a3754f200a3c32019e50">04780</a> <span class="preprocessor">#define  RCC_CR_HSICAL_4                     ((uint32_t)0x00001000)</span>
<a name="l04781"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga4c5b733061a3c4c6d69a7a15cbcb0b87">04781</a> <span class="preprocessor">#define  RCC_CR_HSICAL_5                     ((uint32_t)0x00002000)</span>
<a name="l04782"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaee2d6b30ee4bf41d2b171adf273a6ee7">04782</a> <span class="preprocessor">#define  RCC_CR_HSICAL_6                     ((uint32_t)0x00004000)</span>
<a name="l04783"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gab42d5e412867df093ec2ea4b8dc2bf29">04783</a> <span class="preprocessor">#define  RCC_CR_HSICAL_7                     ((uint32_t)0x00008000)</span>
<a name="l04785"></a>04785 <span class="preprocessor">#define  RCC_CR_HSEON                        ((uint32_t)0x00010000)</span>
<a name="l04786"></a>04786 <span class="preprocessor"></span><span class="preprocessor">#define  RCC_CR_HSERDY                       ((uint32_t)0x00020000)</span>
<a name="l04787"></a>04787 <span class="preprocessor"></span><span class="preprocessor">#define  RCC_CR_HSEBYP                       ((uint32_t)0x00040000)</span>
<a name="l04788"></a>04788 <span class="preprocessor"></span><span class="preprocessor">#define  RCC_CR_CSSON                        ((uint32_t)0x00080000)</span>
<a name="l04789"></a>04789 <span class="preprocessor"></span><span class="preprocessor">#define  RCC_CR_PLLON                        ((uint32_t)0x01000000)</span>
<a name="l04790"></a>04790 <span class="preprocessor"></span><span class="preprocessor">#define  RCC_CR_PLLRDY                       ((uint32_t)0x02000000)</span>
<a name="l04791"></a>04791 <span class="preprocessor"></span><span class="preprocessor">#define  RCC_CR_PLLI2SON                     ((uint32_t)0x04000000)</span>
<a name="l04792"></a>04792 <span class="preprocessor"></span><span class="preprocessor">#define  RCC_CR_PLLI2SRDY                    ((uint32_t)0x08000000)</span>
<a name="l04793"></a>04793 <span class="preprocessor"></span>
<a name="l04794"></a>04794 <span class="comment">/********************  Bit definition for RCC_PLLCFGR register  ***************/</span>
<a name="l04795"></a>04795 <span class="preprocessor">#define  RCC_PLLCFGR_PLLM                    ((uint32_t)0x0000003F)</span>
<a name="l04796"></a>04796 <span class="preprocessor"></span><span class="preprocessor">#define  RCC_PLLCFGR_PLLM_0                  ((uint32_t)0x00000001)</span>
<a name="l04797"></a>04797 <span class="preprocessor"></span><span class="preprocessor">#define  RCC_PLLCFGR_PLLM_1                  ((uint32_t)0x00000002)</span>
<a name="l04798"></a>04798 <span class="preprocessor"></span><span class="preprocessor">#define  RCC_PLLCFGR_PLLM_2                  ((uint32_t)0x00000004)</span>
<a name="l04799"></a>04799 <span class="preprocessor"></span><span class="preprocessor">#define  RCC_PLLCFGR_PLLM_3                  ((uint32_t)0x00000008)</span>
<a name="l04800"></a>04800 <span class="preprocessor"></span><span class="preprocessor">#define  RCC_PLLCFGR_PLLM_4                  ((uint32_t)0x00000010)</span>
<a name="l04801"></a>04801 <span class="preprocessor"></span><span class="preprocessor">#define  RCC_PLLCFGR_PLLM_5                  ((uint32_t)0x00000020)</span>
<a name="l04802"></a>04802 <span class="preprocessor"></span>
<a name="l04803"></a>04803 <span class="preprocessor">#define  RCC_PLLCFGR_PLLN                     ((uint32_t)0x00007FC0)</span>
<a name="l04804"></a>04804 <span class="preprocessor"></span><span class="preprocessor">#define  RCC_PLLCFGR_PLLN_0                   ((uint32_t)0x00000040)</span>
<a name="l04805"></a>04805 <span class="preprocessor"></span><span class="preprocessor">#define  RCC_PLLCFGR_PLLN_1                   ((uint32_t)0x00000080)</span>
<a name="l04806"></a>04806 <span class="preprocessor"></span><span class="preprocessor">#define  RCC_PLLCFGR_PLLN_2                   ((uint32_t)0x00000100)</span>
<a name="l04807"></a>04807 <span class="preprocessor"></span><span class="preprocessor">#define  RCC_PLLCFGR_PLLN_3                   ((uint32_t)0x00000200)</span>
<a name="l04808"></a>04808 <span class="preprocessor"></span><span class="preprocessor">#define  RCC_PLLCFGR_PLLN_4                   ((uint32_t)0x00000400)</span>
<a name="l04809"></a>04809 <span class="preprocessor"></span><span class="preprocessor">#define  RCC_PLLCFGR_PLLN_5                   ((uint32_t)0x00000800)</span>
<a name="l04810"></a>04810 <span class="preprocessor"></span><span class="preprocessor">#define  RCC_PLLCFGR_PLLN_6                   ((uint32_t)0x00001000)</span>
<a name="l04811"></a>04811 <span class="preprocessor"></span><span class="preprocessor">#define  RCC_PLLCFGR_PLLN_7                   ((uint32_t)0x00002000)</span>
<a name="l04812"></a>04812 <span class="preprocessor"></span><span class="preprocessor">#define  RCC_PLLCFGR_PLLN_8                   ((uint32_t)0x00004000)</span>
<a name="l04813"></a>04813 <span class="preprocessor"></span>
<a name="l04814"></a>04814 <span class="preprocessor">#define  RCC_PLLCFGR_PLLP                    ((uint32_t)0x00030000)</span>
<a name="l04815"></a>04815 <span class="preprocessor"></span><span class="preprocessor">#define  RCC_PLLCFGR_PLLP_0                  ((uint32_t)0x00010000)</span>
<a name="l04816"></a>04816 <span class="preprocessor"></span><span class="preprocessor">#define  RCC_PLLCFGR_PLLP_1                  ((uint32_t)0x00020000)</span>
<a name="l04817"></a>04817 <span class="preprocessor"></span>
<a name="l04818"></a>04818 <span class="preprocessor">#define  RCC_PLLCFGR_PLLSRC                  ((uint32_t)0x00400000)</span>
<a name="l04819"></a>04819 <span class="preprocessor"></span><span class="preprocessor">#define  RCC_PLLCFGR_PLLSRC_HSE              ((uint32_t)0x00400000)</span>
<a name="l04820"></a>04820 <span class="preprocessor"></span><span class="preprocessor">#define  RCC_PLLCFGR_PLLSRC_HSI              ((uint32_t)0x00000000)</span>
<a name="l04821"></a>04821 <span class="preprocessor"></span>
<a name="l04822"></a>04822 <span class="preprocessor">#define  RCC_PLLCFGR_PLLQ                    ((uint32_t)0x0F000000)</span>
<a name="l04823"></a>04823 <span class="preprocessor"></span><span class="preprocessor">#define  RCC_PLLCFGR_PLLQ_0                  ((uint32_t)0x01000000)</span>
<a name="l04824"></a>04824 <span class="preprocessor"></span><span class="preprocessor">#define  RCC_PLLCFGR_PLLQ_1                  ((uint32_t)0x02000000)</span>
<a name="l04825"></a>04825 <span class="preprocessor"></span><span class="preprocessor">#define  RCC_PLLCFGR_PLLQ_2                  ((uint32_t)0x04000000)</span>
<a name="l04826"></a>04826 <span class="preprocessor"></span><span class="preprocessor">#define  RCC_PLLCFGR_PLLQ_3                  ((uint32_t)0x08000000)</span>
<a name="l04827"></a>04827 <span class="preprocessor"></span>
<a name="l04828"></a>04828 <span class="comment">/********************  Bit definition for RCC_CFGR register  ******************/</span>
<a name="l04830"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga0eea5e5f7743a7e8995b8beeb18355c1">04830</a> <span class="preprocessor">#define  RCC_CFGR_SW                         ((uint32_t)0x00000003)        </span>
<a name="l04831"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga99f08d86fd41824058a7fdf817f7e2fd">04831</a> <span class="preprocessor">#define  RCC_CFGR_SW_0                       ((uint32_t)0x00000001)        </span>
<a name="l04832"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga72d51cb5d66ee1aa4d2c6f14796a072f">04832</a> <span class="preprocessor">#define  RCC_CFGR_SW_1                       ((uint32_t)0x00000002)        </span>
<a name="l04834"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gacbac8bae4f0808b3c3a5185aa10081fb">04834</a> <span class="preprocessor">#define  RCC_CFGR_SW_HSI                     ((uint32_t)0x00000000)        </span>
<a name="l04835"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gafb563f217242d969f4355d0818fde705">04835</a> <span class="preprocessor">#define  RCC_CFGR_SW_HSE                     ((uint32_t)0x00000001)        </span>
<a name="l04836"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga87389cacb2eaf53730da13a2a33cd487">04836</a> <span class="preprocessor">#define  RCC_CFGR_SW_PLL                     ((uint32_t)0x00000002)        </span>
<a name="l04839"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga15bf2269500dc97e137315f44aa015c9">04839</a> <span class="preprocessor">#define  RCC_CFGR_SWS                        ((uint32_t)0x0000000C)        </span>
<a name="l04840"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga1eae59112c51def51979e31e8695b39f">04840</a> <span class="preprocessor">#define  RCC_CFGR_SWS_0                      ((uint32_t)0x00000004)        </span>
<a name="l04841"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaad3a5718999d7259f216137a23c2a379">04841</a> <span class="preprocessor">#define  RCC_CFGR_SWS_1                      ((uint32_t)0x00000008)        </span>
<a name="l04843"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga6764639cf221e1ebc0b5448dcaed590a">04843</a> <span class="preprocessor">#define  RCC_CFGR_SWS_HSI                    ((uint32_t)0x00000000)        </span>
<a name="l04844"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gae09a0202f441c1a43e69c62331d50a08">04844</a> <span class="preprocessor">#define  RCC_CFGR_SWS_HSE                    ((uint32_t)0x00000004)        </span>
<a name="l04845"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga2c67e2279804a83ef24438267d9d4a6c">04845</a> <span class="preprocessor">#define  RCC_CFGR_SWS_PLL                    ((uint32_t)0x00000008)        </span>
<a name="l04848"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gafe10e66938644ee8054a2426ff23efea">04848</a> <span class="preprocessor">#define  RCC_CFGR_HPRE                       ((uint32_t)0x000000F0)        </span>
<a name="l04849"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga88ece6ca270b3ecf6f63bf20893bc172">04849</a> <span class="preprocessor">#define  RCC_CFGR_HPRE_0                     ((uint32_t)0x00000010)        </span>
<a name="l04850"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gacbdd3a02814178ba02b8ebbaccd91599">04850</a> <span class="preprocessor">#define  RCC_CFGR_HPRE_1                     ((uint32_t)0x00000020)        </span>
<a name="l04851"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gadac734bddb507eed4a62a0af4cef74a3">04851</a> <span class="preprocessor">#define  RCC_CFGR_HPRE_2                     ((uint32_t)0x00000040)        </span>
<a name="l04852"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga5a1180512cc5f3dde7895040a9037286">04852</a> <span class="preprocessor">#define  RCC_CFGR_HPRE_3                     ((uint32_t)0x00000080)        </span>
<a name="l04854"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga2b7d7f29b09a49c31404fc0d44645c84">04854</a> <span class="preprocessor">#define  RCC_CFGR_HPRE_DIV1                  ((uint32_t)0x00000000)        </span>
<a name="l04855"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaa9eeb5e38e53e79b08a4ac438497ebea">04855</a> <span class="preprocessor">#define  RCC_CFGR_HPRE_DIV2                  ((uint32_t)0x00000080)        </span>
<a name="l04856"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaffe860867ae4b1b6d28473ded1546d91">04856</a> <span class="preprocessor">#define  RCC_CFGR_HPRE_DIV4                  ((uint32_t)0x00000090)        </span>
<a name="l04857"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaca71d6b42bdb83b5ff5320578869a058">04857</a> <span class="preprocessor">#define  RCC_CFGR_HPRE_DIV8                  ((uint32_t)0x000000A0)        </span>
<a name="l04858"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga3806da4f1afc9e5be0fca001c8c57815">04858</a> <span class="preprocessor">#define  RCC_CFGR_HPRE_DIV16                 ((uint32_t)0x000000B0)        </span>
<a name="l04859"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga1caeba8dc2b4c0bb11be600e983e3370">04859</a> <span class="preprocessor">#define  RCC_CFGR_HPRE_DIV64                 ((uint32_t)0x000000C0)        </span>
<a name="l04860"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga280da821f0da1bec1f4c0e132ddf8eab">04860</a> <span class="preprocessor">#define  RCC_CFGR_HPRE_DIV128                ((uint32_t)0x000000D0)        </span>
<a name="l04861"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga089930cedd5b2cb201e717438f29d25b">04861</a> <span class="preprocessor">#define  RCC_CFGR_HPRE_DIV256                ((uint32_t)0x000000E0)        </span>
<a name="l04862"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gae5088dcbaefc55d4b6693e9b1e595ed0">04862</a> <span class="preprocessor">#define  RCC_CFGR_HPRE_DIV512                ((uint32_t)0x000000F0)        </span>
<a name="l04865"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga50b2423a5fea74a47b9eb8ab51869412">04865</a> <span class="preprocessor">#define  RCC_CFGR_PPRE1                      ((uint32_t)0x00001C00)        </span>
<a name="l04866"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga2d37c20686faa340a77021117f5908b7">04866</a> <span class="preprocessor">#define  RCC_CFGR_PPRE1_0                    ((uint32_t)0x00000400)        </span>
<a name="l04867"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gad41049f8a28fdced6bb4d9267845ffa2">04867</a> <span class="preprocessor">#define  RCC_CFGR_PPRE1_1                    ((uint32_t)0x00000800)        </span>
<a name="l04868"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga5fcb524f6ca203ddff1862c124d4f89f">04868</a> <span class="preprocessor">#define  RCC_CFGR_PPRE1_2                    ((uint32_t)0x00001000)        </span>
<a name="l04870"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gac8f6562bb2ecf65055a2f42cbb48ef11">04870</a> <span class="preprocessor">#define  RCC_CFGR_PPRE1_DIV1                 ((uint32_t)0x00000000)        </span>
<a name="l04871"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaf832ad6844c907d9bb37c1536defcb0d">04871</a> <span class="preprocessor">#define  RCC_CFGR_PPRE1_DIV2                 ((uint32_t)0x00001000)        </span>
<a name="l04872"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga0e340725f46e9462d9b02a079b9fa8ae">04872</a> <span class="preprocessor">#define  RCC_CFGR_PPRE1_DIV4                 ((uint32_t)0x00001400)        </span>
<a name="l04873"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga9ddd6d657837e1971bb86e3bf1c15e72">04873</a> <span class="preprocessor">#define  RCC_CFGR_PPRE1_DIV8                 ((uint32_t)0x00001800)        </span>
<a name="l04874"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga5c38ba326bde7c7a18c4f7f2aacf823f">04874</a> <span class="preprocessor">#define  RCC_CFGR_PPRE1_DIV16                ((uint32_t)0x00001C00)        </span>
<a name="l04877"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gad61bd4f9f345ba41806813b0bfff1311">04877</a> <span class="preprocessor">#define  RCC_CFGR_PPRE2                      ((uint32_t)0x0000E000)        </span>
<a name="l04878"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga82ca63155494ed59eb5e34bec1e5f4e9">04878</a> <span class="preprocessor">#define  RCC_CFGR_PPRE2_0                    ((uint32_t)0x00002000)        </span>
<a name="l04879"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gafdb19c9e76fe8e8a7c991714c92e937f">04879</a> <span class="preprocessor">#define  RCC_CFGR_PPRE2_1                    ((uint32_t)0x00004000)        </span>
<a name="l04880"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga9adc802687eab5b6ece99a20793219db">04880</a> <span class="preprocessor">#define  RCC_CFGR_PPRE2_2                    ((uint32_t)0x00008000)        </span>
<a name="l04882"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga247aebf1999a38ea07785558d277bb1a">04882</a> <span class="preprocessor">#define  RCC_CFGR_PPRE2_DIV1                 ((uint32_t)0x00000000)        </span>
<a name="l04883"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga99d9c91eaad122460d324a71cc939d1b">04883</a> <span class="preprocessor">#define  RCC_CFGR_PPRE2_DIV2                 ((uint32_t)0x00008000)        </span>
<a name="l04884"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga4340fc3fc52eca36eb302959fbecb715">04884</a> <span class="preprocessor">#define  RCC_CFGR_PPRE2_DIV4                 ((uint32_t)0x0000A000)        </span>
<a name="l04885"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga412b382a1134e0ee5614e0f4bcf97552">04885</a> <span class="preprocessor">#define  RCC_CFGR_PPRE2_DIV8                 ((uint32_t)0x0000C000)        </span>
<a name="l04886"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaece3ee58d4138f7452733bfa1ad37eb9">04886</a> <span class="preprocessor">#define  RCC_CFGR_PPRE2_DIV16                ((uint32_t)0x0000E000)        </span>
<a name="l04889"></a>04889 <span class="preprocessor">#define  RCC_CFGR_RTCPRE                     ((uint32_t)0x001F0000)</span>
<a name="l04890"></a>04890 <span class="preprocessor"></span><span class="preprocessor">#define  RCC_CFGR_RTCPRE_0                   ((uint32_t)0x00010000)</span>
<a name="l04891"></a>04891 <span class="preprocessor"></span><span class="preprocessor">#define  RCC_CFGR_RTCPRE_1                   ((uint32_t)0x00020000)</span>
<a name="l04892"></a>04892 <span class="preprocessor"></span><span class="preprocessor">#define  RCC_CFGR_RTCPRE_2                   ((uint32_t)0x00040000)</span>
<a name="l04893"></a>04893 <span class="preprocessor"></span><span class="preprocessor">#define  RCC_CFGR_RTCPRE_3                   ((uint32_t)0x00080000)</span>
<a name="l04894"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga02b93e5154259a1a201bbb9c9b903c0a">04894</a> <span class="preprocessor"></span><span class="preprocessor">#define  RCC_CFGR_RTCPRE_4                   ((uint32_t)0x00100000)</span>
<a name="l04895"></a>04895 <span class="preprocessor"></span>
<a name="l04897"></a>04897 <span class="preprocessor">#define  RCC_CFGR_MCO1                       ((uint32_t)0x00600000)</span>
<a name="l04898"></a>04898 <span class="preprocessor"></span><span class="preprocessor">#define  RCC_CFGR_MCO1_0                     ((uint32_t)0x00200000)</span>
<a name="l04899"></a>04899 <span class="preprocessor"></span><span class="preprocessor">#define  RCC_CFGR_MCO1_1                     ((uint32_t)0x00400000)</span>
<a name="l04900"></a>04900 <span class="preprocessor"></span>
<a name="l04901"></a>04901 <span class="preprocessor">#define  RCC_CFGR_I2SSRC                     ((uint32_t)0x00800000)</span>
<a name="l04902"></a>04902 <span class="preprocessor"></span>
<a name="l04903"></a>04903 <span class="preprocessor">#define  RCC_CFGR_MCO1PRE                    ((uint32_t)0x07000000)</span>
<a name="l04904"></a>04904 <span class="preprocessor"></span><span class="preprocessor">#define  RCC_CFGR_MCO1PRE_0                  ((uint32_t)0x01000000)</span>
<a name="l04905"></a>04905 <span class="preprocessor"></span><span class="preprocessor">#define  RCC_CFGR_MCO1PRE_1                  ((uint32_t)0x02000000)</span>
<a name="l04906"></a>04906 <span class="preprocessor"></span><span class="preprocessor">#define  RCC_CFGR_MCO1PRE_2                  ((uint32_t)0x04000000)</span>
<a name="l04907"></a>04907 <span class="preprocessor"></span>
<a name="l04908"></a>04908 <span class="preprocessor">#define  RCC_CFGR_MCO2PRE                    ((uint32_t)0x38000000)</span>
<a name="l04909"></a>04909 <span class="preprocessor"></span><span class="preprocessor">#define  RCC_CFGR_MCO2PRE_0                  ((uint32_t)0x08000000)</span>
<a name="l04910"></a>04910 <span class="preprocessor"></span><span class="preprocessor">#define  RCC_CFGR_MCO2PRE_1                  ((uint32_t)0x10000000)</span>
<a name="l04911"></a>04911 <span class="preprocessor"></span><span class="preprocessor">#define  RCC_CFGR_MCO2PRE_2                  ((uint32_t)0x20000000)</span>
<a name="l04912"></a>04912 <span class="preprocessor"></span>
<a name="l04913"></a>04913 <span class="preprocessor">#define  RCC_CFGR_MCO2                       ((uint32_t)0xC0000000)</span>
<a name="l04914"></a>04914 <span class="preprocessor"></span><span class="preprocessor">#define  RCC_CFGR_MCO2_0                     ((uint32_t)0x40000000)</span>
<a name="l04915"></a>04915 <span class="preprocessor"></span><span class="preprocessor">#define  RCC_CFGR_MCO2_1                     ((uint32_t)0x80000000)</span>
<a name="l04916"></a>04916 <span class="preprocessor"></span>
<a name="l04917"></a>04917 <span class="comment">/********************  Bit definition for RCC_CIR register  *******************/</span>
<a name="l04918"></a>04918 <span class="preprocessor">#define  RCC_CIR_LSIRDYF                     ((uint32_t)0x00000001)</span>
<a name="l04919"></a>04919 <span class="preprocessor"></span><span class="preprocessor">#define  RCC_CIR_LSERDYF                     ((uint32_t)0x00000002)</span>
<a name="l04920"></a>04920 <span class="preprocessor"></span><span class="preprocessor">#define  RCC_CIR_HSIRDYF                     ((uint32_t)0x00000004)</span>
<a name="l04921"></a>04921 <span class="preprocessor"></span><span class="preprocessor">#define  RCC_CIR_HSERDYF                     ((uint32_t)0x00000008)</span>
<a name="l04922"></a>04922 <span class="preprocessor"></span><span class="preprocessor">#define  RCC_CIR_PLLRDYF                     ((uint32_t)0x00000010)</span>
<a name="l04923"></a>04923 <span class="preprocessor"></span><span class="preprocessor">#define  RCC_CIR_PLLI2SRDYF                  ((uint32_t)0x00000020)</span>
<a name="l04924"></a>04924 <span class="preprocessor"></span><span class="preprocessor">#define  RCC_CIR_CSSF                        ((uint32_t)0x00000080)</span>
<a name="l04925"></a>04925 <span class="preprocessor"></span><span class="preprocessor">#define  RCC_CIR_LSIRDYIE                    ((uint32_t)0x00000100)</span>
<a name="l04926"></a>04926 <span class="preprocessor"></span><span class="preprocessor">#define  RCC_CIR_LSERDYIE                    ((uint32_t)0x00000200)</span>
<a name="l04927"></a>04927 <span class="preprocessor"></span><span class="preprocessor">#define  RCC_CIR_HSIRDYIE                    ((uint32_t)0x00000400)</span>
<a name="l04928"></a>04928 <span class="preprocessor"></span><span class="preprocessor">#define  RCC_CIR_HSERDYIE                    ((uint32_t)0x00000800)</span>
<a name="l04929"></a>04929 <span class="preprocessor"></span><span class="preprocessor">#define  RCC_CIR_PLLRDYIE                    ((uint32_t)0x00001000)</span>
<a name="l04930"></a>04930 <span class="preprocessor"></span><span class="preprocessor">#define  RCC_CIR_PLLI2SRDYIE                 ((uint32_t)0x00002000)</span>
<a name="l04931"></a>04931 <span class="preprocessor"></span><span class="preprocessor">#define  RCC_CIR_LSIRDYC                     ((uint32_t)0x00010000)</span>
<a name="l04932"></a>04932 <span class="preprocessor"></span><span class="preprocessor">#define  RCC_CIR_LSERDYC                     ((uint32_t)0x00020000)</span>
<a name="l04933"></a>04933 <span class="preprocessor"></span><span class="preprocessor">#define  RCC_CIR_HSIRDYC                     ((uint32_t)0x00040000)</span>
<a name="l04934"></a>04934 <span class="preprocessor"></span><span class="preprocessor">#define  RCC_CIR_HSERDYC                     ((uint32_t)0x00080000)</span>
<a name="l04935"></a>04935 <span class="preprocessor"></span><span class="preprocessor">#define  RCC_CIR_PLLRDYC                     ((uint32_t)0x00100000)</span>
<a name="l04936"></a>04936 <span class="preprocessor"></span><span class="preprocessor">#define  RCC_CIR_PLLI2SRDYC                  ((uint32_t)0x00200000)</span>
<a name="l04937"></a>04937 <span class="preprocessor"></span><span class="preprocessor">#define  RCC_CIR_CSSC                        ((uint32_t)0x00800000)</span>
<a name="l04938"></a>04938 <span class="preprocessor"></span>
<a name="l04939"></a>04939 <span class="comment">/********************  Bit definition for RCC_AHB1RSTR register  **************/</span>
<a name="l04940"></a>04940 <span class="preprocessor">#define  RCC_AHB1RSTR_GPIOARST               ((uint32_t)0x00000001)</span>
<a name="l04941"></a>04941 <span class="preprocessor"></span><span class="preprocessor">#define  RCC_AHB1RSTR_GPIOBRST               ((uint32_t)0x00000002)</span>
<a name="l04942"></a>04942 <span class="preprocessor"></span><span class="preprocessor">#define  RCC_AHB1RSTR_GPIOCRST               ((uint32_t)0x00000004)</span>
<a name="l04943"></a>04943 <span class="preprocessor"></span><span class="preprocessor">#define  RCC_AHB1RSTR_GPIODRST               ((uint32_t)0x00000008)</span>
<a name="l04944"></a>04944 <span class="preprocessor"></span><span class="preprocessor">#define  RCC_AHB1RSTR_GPIOERST               ((uint32_t)0x00000010)</span>
<a name="l04945"></a>04945 <span class="preprocessor"></span><span class="preprocessor">#define  RCC_AHB1RSTR_GPIOFRST               ((uint32_t)0x00000020)</span>
<a name="l04946"></a>04946 <span class="preprocessor"></span><span class="preprocessor">#define  RCC_AHB1RSTR_GPIOGRST               ((uint32_t)0x00000040)</span>
<a name="l04947"></a>04947 <span class="preprocessor"></span><span class="preprocessor">#define  RCC_AHB1RSTR_GPIOHRST               ((uint32_t)0x00000080)</span>
<a name="l04948"></a>04948 <span class="preprocessor"></span><span class="preprocessor">#define  RCC_AHB1RSTR_GPIOIRST               ((uint32_t)0x00000100)</span>
<a name="l04949"></a>04949 <span class="preprocessor"></span><span class="preprocessor">#define  RCC_AHB1RSTR_CRCRST                 ((uint32_t)0x00001000)</span>
<a name="l04950"></a>04950 <span class="preprocessor"></span><span class="preprocessor">#define  RCC_AHB1RSTR_DMA1RST                ((uint32_t)0x00200000)</span>
<a name="l04951"></a>04951 <span class="preprocessor"></span><span class="preprocessor">#define  RCC_AHB1RSTR_DMA2RST                ((uint32_t)0x00400000)</span>
<a name="l04952"></a>04952 <span class="preprocessor"></span><span class="preprocessor">#define  RCC_AHB1RSTR_ETHMACRST              ((uint32_t)0x02000000)</span>
<a name="l04953"></a>04953 <span class="preprocessor"></span><span class="preprocessor">#define  RCC_AHB1RSTR_OTGHRST                ((uint32_t)0x10000000)</span>
<a name="l04954"></a>04954 <span class="preprocessor"></span>
<a name="l04955"></a>04955 <span class="comment">/********************  Bit definition for RCC_AHB2RSTR register  **************/</span>
<a name="l04956"></a>04956 <span class="preprocessor">#define  RCC_AHB2RSTR_DCMIRST                ((uint32_t)0x00000001)</span>
<a name="l04957"></a>04957 <span class="preprocessor"></span><span class="preprocessor">#define  RCC_AHB2RSTR_CRYPRST                ((uint32_t)0x00000010)</span>
<a name="l04958"></a>04958 <span class="preprocessor"></span><span class="preprocessor">#define  RCC_AHB2RSTR_HSAHRST                ((uint32_t)0x00000020)</span>
<a name="l04959"></a>04959 <span class="preprocessor"></span><span class="preprocessor">#define  RCC_AHB2RSTR_RNGRST                 ((uint32_t)0x00000040)</span>
<a name="l04960"></a>04960 <span class="preprocessor"></span><span class="preprocessor">#define  RCC_AHB2RSTR_OTGFSRST               ((uint32_t)0x00000080)</span>
<a name="l04961"></a>04961 <span class="preprocessor"></span>
<a name="l04962"></a>04962 <span class="comment">/********************  Bit definition for RCC_AHB3RSTR register  **************/</span>
<a name="l04963"></a>04963 <span class="preprocessor">#define  RCC_AHB3RSTR_FSMCRST                ((uint32_t)0x00000001)</span>
<a name="l04964"></a>04964 <span class="preprocessor"></span>
<a name="l04965"></a>04965 <span class="comment">/********************  Bit definition for RCC_APB1RSTR register  **************/</span>
<a name="l04966"></a>04966 <span class="preprocessor">#define  RCC_APB1RSTR_TIM2RST                ((uint32_t)0x00000001)</span>
<a name="l04967"></a>04967 <span class="preprocessor"></span><span class="preprocessor">#define  RCC_APB1RSTR_TIM3RST                ((uint32_t)0x00000002)</span>
<a name="l04968"></a>04968 <span class="preprocessor"></span><span class="preprocessor">#define  RCC_APB1RSTR_TIM4RST                ((uint32_t)0x00000004)</span>
<a name="l04969"></a>04969 <span class="preprocessor"></span><span class="preprocessor">#define  RCC_APB1RSTR_TIM5RST                ((uint32_t)0x00000008)</span>
<a name="l04970"></a>04970 <span class="preprocessor"></span><span class="preprocessor">#define  RCC_APB1RSTR_TIM6RST                ((uint32_t)0x00000010)</span>
<a name="l04971"></a>04971 <span class="preprocessor"></span><span class="preprocessor">#define  RCC_APB1RSTR_TIM7RST                ((uint32_t)0x00000020)</span>
<a name="l04972"></a>04972 <span class="preprocessor"></span><span class="preprocessor">#define  RCC_APB1RSTR_TIM12RST               ((uint32_t)0x00000040)</span>
<a name="l04973"></a>04973 <span class="preprocessor"></span><span class="preprocessor">#define  RCC_APB1RSTR_TIM13RST               ((uint32_t)0x00000080)</span>
<a name="l04974"></a>04974 <span class="preprocessor"></span><span class="preprocessor">#define  RCC_APB1RSTR_TIM14RST               ((uint32_t)0x00000100)</span>
<a name="l04975"></a>04975 <span class="preprocessor"></span><span class="preprocessor">#define  RCC_APB1RSTR_WWDGEN                 ((uint32_t)0x00000800)</span>
<a name="l04976"></a>04976 <span class="preprocessor"></span><span class="preprocessor">#define  RCC_APB1RSTR_SPI2RST                ((uint32_t)0x00008000)</span>
<a name="l04977"></a>04977 <span class="preprocessor"></span><span class="preprocessor">#define  RCC_APB1RSTR_SPI3RST                ((uint32_t)0x00010000)</span>
<a name="l04978"></a>04978 <span class="preprocessor"></span><span class="preprocessor">#define  RCC_APB1RSTR_USART2RST              ((uint32_t)0x00020000)</span>
<a name="l04979"></a>04979 <span class="preprocessor"></span><span class="preprocessor">#define  RCC_APB1RSTR_USART3RST              ((uint32_t)0x00040000)</span>
<a name="l04980"></a>04980 <span class="preprocessor"></span><span class="preprocessor">#define  RCC_APB1RSTR_UART4RST               ((uint32_t)0x00080000)</span>
<a name="l04981"></a>04981 <span class="preprocessor"></span><span class="preprocessor">#define  RCC_APB1RSTR_UART5RST               ((uint32_t)0x00100000)</span>
<a name="l04982"></a>04982 <span class="preprocessor"></span><span class="preprocessor">#define  RCC_APB1RSTR_I2C1RST                ((uint32_t)0x00200000)</span>
<a name="l04983"></a>04983 <span class="preprocessor"></span><span class="preprocessor">#define  RCC_APB1RSTR_I2C2RST                ((uint32_t)0x00400000)</span>
<a name="l04984"></a>04984 <span class="preprocessor"></span><span class="preprocessor">#define  RCC_APB1RSTR_I2C3RST                ((uint32_t)0x00800000)</span>
<a name="l04985"></a>04985 <span class="preprocessor"></span><span class="preprocessor">#define  RCC_APB1RSTR_CAN1RST                ((uint32_t)0x02000000)</span>
<a name="l04986"></a>04986 <span class="preprocessor"></span><span class="preprocessor">#define  RCC_APB1RSTR_CAN2RST                ((uint32_t)0x04000000)</span>
<a name="l04987"></a>04987 <span class="preprocessor"></span><span class="preprocessor">#define  RCC_APB1RSTR_PWRRST                 ((uint32_t)0x10000000)</span>
<a name="l04988"></a>04988 <span class="preprocessor"></span><span class="preprocessor">#define  RCC_APB1RSTR_DACRST                 ((uint32_t)0x20000000)</span>
<a name="l04989"></a>04989 <span class="preprocessor"></span>
<a name="l04990"></a>04990 <span class="comment">/********************  Bit definition for RCC_APB2RSTR register  **************/</span>
<a name="l04991"></a>04991 <span class="preprocessor">#define  RCC_APB2RSTR_TIM1RST                ((uint32_t)0x00000001)</span>
<a name="l04992"></a>04992 <span class="preprocessor"></span><span class="preprocessor">#define  RCC_APB2RSTR_TIM8RST                ((uint32_t)0x00000002)</span>
<a name="l04993"></a>04993 <span class="preprocessor"></span><span class="preprocessor">#define  RCC_APB2RSTR_USART1RST              ((uint32_t)0x00000010)</span>
<a name="l04994"></a>04994 <span class="preprocessor"></span><span class="preprocessor">#define  RCC_APB2RSTR_USART6RST              ((uint32_t)0x00000020)</span>
<a name="l04995"></a>04995 <span class="preprocessor"></span><span class="preprocessor">#define  RCC_APB2RSTR_ADCRST                 ((uint32_t)0x00000100)</span>
<a name="l04996"></a>04996 <span class="preprocessor"></span><span class="preprocessor">#define  RCC_APB2RSTR_SDIORST                ((uint32_t)0x00000800)</span>
<a name="l04997"></a>04997 <span class="preprocessor"></span><span class="preprocessor">#define  RCC_APB2RSTR_SPI1RST                ((uint32_t)0x00001000)</span>
<a name="l04998"></a>04998 <span class="preprocessor"></span><span class="preprocessor">#define  RCC_APB2RSTR_SYSCFGRST              ((uint32_t)0x00004000)</span>
<a name="l04999"></a>04999 <span class="preprocessor"></span><span class="preprocessor">#define  RCC_APB2RSTR_TIM9RST                ((uint32_t)0x00010000)</span>
<a name="l05000"></a>05000 <span class="preprocessor"></span><span class="preprocessor">#define  RCC_APB2RSTR_TIM10RST               ((uint32_t)0x00020000)</span>
<a name="l05001"></a>05001 <span class="preprocessor"></span><span class="preprocessor">#define  RCC_APB2RSTR_TIM11RST               ((uint32_t)0x00040000)</span>
<a name="l05002"></a>05002 <span class="preprocessor"></span><span class="comment">/* Old SPI1RST bit definition, maintained for legacy purpose */</span>
<a name="l05003"></a>05003 <span class="preprocessor">#define  RCC_APB2RSTR_SPI1                   RCC_APB2RSTR_SPI1RST</span>
<a name="l05004"></a>05004 <span class="preprocessor"></span>
<a name="l05005"></a>05005 <span class="comment">/********************  Bit definition for RCC_AHB1ENR register  ***************/</span>
<a name="l05006"></a>05006 <span class="preprocessor">#define  RCC_AHB1ENR_GPIOAEN                 ((uint32_t)0x00000001)</span>
<a name="l05007"></a>05007 <span class="preprocessor"></span><span class="preprocessor">#define  RCC_AHB1ENR_GPIOBEN                 ((uint32_t)0x00000002)</span>
<a name="l05008"></a>05008 <span class="preprocessor"></span><span class="preprocessor">#define  RCC_AHB1ENR_GPIOCEN                 ((uint32_t)0x00000004)</span>
<a name="l05009"></a>05009 <span class="preprocessor"></span><span class="preprocessor">#define  RCC_AHB1ENR_GPIODEN                 ((uint32_t)0x00000008)</span>
<a name="l05010"></a>05010 <span class="preprocessor"></span><span class="preprocessor">#define  RCC_AHB1ENR_GPIOEEN                 ((uint32_t)0x00000010)</span>
<a name="l05011"></a>05011 <span class="preprocessor"></span><span class="preprocessor">#define  RCC_AHB1ENR_GPIOFEN                 ((uint32_t)0x00000020)</span>
<a name="l05012"></a>05012 <span class="preprocessor"></span><span class="preprocessor">#define  RCC_AHB1ENR_GPIOGEN                 ((uint32_t)0x00000040)</span>
<a name="l05013"></a>05013 <span class="preprocessor"></span><span class="preprocessor">#define  RCC_AHB1ENR_GPIOHEN                 ((uint32_t)0x00000080)</span>
<a name="l05014"></a>05014 <span class="preprocessor"></span><span class="preprocessor">#define  RCC_AHB1ENR_GPIOIEN                 ((uint32_t)0x00000100)</span>
<a name="l05015"></a>05015 <span class="preprocessor"></span><span class="preprocessor">#define  RCC_AHB1ENR_CRCEN                   ((uint32_t)0x00001000)</span>
<a name="l05016"></a>05016 <span class="preprocessor"></span><span class="preprocessor">#define  RCC_AHB1ENR_BKPSRAMEN               ((uint32_t)0x00040000)</span>
<a name="l05017"></a>05017 <span class="preprocessor"></span><span class="preprocessor">#define  RCC_AHB1ENR_CCMDATARAMEN            ((uint32_t)0x00100000)</span>
<a name="l05018"></a>05018 <span class="preprocessor"></span><span class="preprocessor">#define  RCC_AHB1ENR_DMA1EN                  ((uint32_t)0x00200000)</span>
<a name="l05019"></a>05019 <span class="preprocessor"></span><span class="preprocessor">#define  RCC_AHB1ENR_DMA2EN                  ((uint32_t)0x00400000)</span>
<a name="l05020"></a>05020 <span class="preprocessor"></span><span class="preprocessor">#define  RCC_AHB1ENR_ETHMACEN                ((uint32_t)0x02000000)</span>
<a name="l05021"></a>05021 <span class="preprocessor"></span><span class="preprocessor">#define  RCC_AHB1ENR_ETHMACTXEN              ((uint32_t)0x04000000)</span>
<a name="l05022"></a>05022 <span class="preprocessor"></span><span class="preprocessor">#define  RCC_AHB1ENR_ETHMACRXEN              ((uint32_t)0x08000000)</span>
<a name="l05023"></a>05023 <span class="preprocessor"></span><span class="preprocessor">#define  RCC_AHB1ENR_ETHMACPTPEN             ((uint32_t)0x10000000)</span>
<a name="l05024"></a>05024 <span class="preprocessor"></span><span class="preprocessor">#define  RCC_AHB1ENR_OTGHSEN                 ((uint32_t)0x20000000)</span>
<a name="l05025"></a>05025 <span class="preprocessor"></span><span class="preprocessor">#define  RCC_AHB1ENR_OTGHSULPIEN             ((uint32_t)0x40000000)</span>
<a name="l05026"></a>05026 <span class="preprocessor"></span>
<a name="l05027"></a>05027 <span class="comment">/********************  Bit definition for RCC_AHB2ENR register  ***************/</span>
<a name="l05028"></a>05028 <span class="preprocessor">#define  RCC_AHB2ENR_DCMIEN                  ((uint32_t)0x00000001)</span>
<a name="l05029"></a>05029 <span class="preprocessor"></span><span class="preprocessor">#define  RCC_AHB2ENR_CRYPEN                  ((uint32_t)0x00000010)</span>
<a name="l05030"></a>05030 <span class="preprocessor"></span><span class="preprocessor">#define  RCC_AHB2ENR_HASHEN                  ((uint32_t)0x00000020)</span>
<a name="l05031"></a>05031 <span class="preprocessor"></span><span class="preprocessor">#define  RCC_AHB2ENR_RNGEN                   ((uint32_t)0x00000040)</span>
<a name="l05032"></a>05032 <span class="preprocessor"></span><span class="preprocessor">#define  RCC_AHB2ENR_OTGFSEN                 ((uint32_t)0x00000080)</span>
<a name="l05033"></a>05033 <span class="preprocessor"></span>
<a name="l05034"></a>05034 <span class="comment">/********************  Bit definition for RCC_AHB3ENR register  ***************/</span>
<a name="l05035"></a>05035 <span class="preprocessor">#define  RCC_AHB3ENR_FSMCEN                  ((uint32_t)0x00000001)</span>
<a name="l05036"></a>05036 <span class="preprocessor"></span>
<a name="l05037"></a>05037 <span class="comment">/********************  Bit definition for RCC_APB1ENR register  ***************/</span>
<a name="l05038"></a>05038 <span class="preprocessor">#define  RCC_APB1ENR_TIM2EN                  ((uint32_t)0x00000001)</span>
<a name="l05039"></a>05039 <span class="preprocessor"></span><span class="preprocessor">#define  RCC_APB1ENR_TIM3EN                  ((uint32_t)0x00000002)</span>
<a name="l05040"></a>05040 <span class="preprocessor"></span><span class="preprocessor">#define  RCC_APB1ENR_TIM4EN                  ((uint32_t)0x00000004)</span>
<a name="l05041"></a>05041 <span class="preprocessor"></span><span class="preprocessor">#define  RCC_APB1ENR_TIM5EN                  ((uint32_t)0x00000008)</span>
<a name="l05042"></a>05042 <span class="preprocessor"></span><span class="preprocessor">#define  RCC_APB1ENR_TIM6EN                  ((uint32_t)0x00000010)</span>
<a name="l05043"></a>05043 <span class="preprocessor"></span><span class="preprocessor">#define  RCC_APB1ENR_TIM7EN                  ((uint32_t)0x00000020)</span>
<a name="l05044"></a>05044 <span class="preprocessor"></span><span class="preprocessor">#define  RCC_APB1ENR_TIM12EN                 ((uint32_t)0x00000040)</span>
<a name="l05045"></a>05045 <span class="preprocessor"></span><span class="preprocessor">#define  RCC_APB1ENR_TIM13EN                 ((uint32_t)0x00000080)</span>
<a name="l05046"></a>05046 <span class="preprocessor"></span><span class="preprocessor">#define  RCC_APB1ENR_TIM14EN                 ((uint32_t)0x00000100)</span>
<a name="l05047"></a>05047 <span class="preprocessor"></span><span class="preprocessor">#define  RCC_APB1ENR_WWDGEN                  ((uint32_t)0x00000800)</span>
<a name="l05048"></a>05048 <span class="preprocessor"></span><span class="preprocessor">#define  RCC_APB1ENR_SPI2EN                  ((uint32_t)0x00004000)</span>
<a name="l05049"></a>05049 <span class="preprocessor"></span><span class="preprocessor">#define  RCC_APB1ENR_SPI3EN                  ((uint32_t)0x00008000)</span>
<a name="l05050"></a>05050 <span class="preprocessor"></span><span class="preprocessor">#define  RCC_APB1ENR_USART2EN                ((uint32_t)0x00020000)</span>
<a name="l05051"></a>05051 <span class="preprocessor"></span><span class="preprocessor">#define  RCC_APB1ENR_USART3EN                ((uint32_t)0x00040000)</span>
<a name="l05052"></a>05052 <span class="preprocessor"></span><span class="preprocessor">#define  RCC_APB1ENR_UART4EN                 ((uint32_t)0x00080000)</span>
<a name="l05053"></a>05053 <span class="preprocessor"></span><span class="preprocessor">#define  RCC_APB1ENR_UART5EN                 ((uint32_t)0x00100000)</span>
<a name="l05054"></a>05054 <span class="preprocessor"></span><span class="preprocessor">#define  RCC_APB1ENR_I2C1EN                  ((uint32_t)0x00200000)</span>
<a name="l05055"></a>05055 <span class="preprocessor"></span><span class="preprocessor">#define  RCC_APB1ENR_I2C2EN                  ((uint32_t)0x00400000)</span>
<a name="l05056"></a>05056 <span class="preprocessor"></span><span class="preprocessor">#define  RCC_APB1ENR_I2C3EN                  ((uint32_t)0x00800000)</span>
<a name="l05057"></a>05057 <span class="preprocessor"></span><span class="preprocessor">#define  RCC_APB1ENR_CAN1EN                  ((uint32_t)0x02000000)</span>
<a name="l05058"></a>05058 <span class="preprocessor"></span><span class="preprocessor">#define  RCC_APB1ENR_CAN2EN                  ((uint32_t)0x04000000)</span>
<a name="l05059"></a>05059 <span class="preprocessor"></span><span class="preprocessor">#define  RCC_APB1ENR_PWREN                   ((uint32_t)0x10000000)</span>
<a name="l05060"></a>05060 <span class="preprocessor"></span><span class="preprocessor">#define  RCC_APB1ENR_DACEN                   ((uint32_t)0x20000000)</span>
<a name="l05061"></a>05061 <span class="preprocessor"></span>
<a name="l05062"></a>05062 <span class="comment">/********************  Bit definition for RCC_APB2ENR register  ***************/</span>
<a name="l05063"></a>05063 <span class="preprocessor">#define  RCC_APB2ENR_TIM1EN                  ((uint32_t)0x00000001)</span>
<a name="l05064"></a>05064 <span class="preprocessor"></span><span class="preprocessor">#define  RCC_APB2ENR_TIM8EN                  ((uint32_t)0x00000002)</span>
<a name="l05065"></a>05065 <span class="preprocessor"></span><span class="preprocessor">#define  RCC_APB2ENR_USART1EN                ((uint32_t)0x00000010)</span>
<a name="l05066"></a>05066 <span class="preprocessor"></span><span class="preprocessor">#define  RCC_APB2ENR_USART6EN                ((uint32_t)0x00000020)</span>
<a name="l05067"></a>05067 <span class="preprocessor"></span><span class="preprocessor">#define  RCC_APB2ENR_ADC1EN                  ((uint32_t)0x00000100)</span>
<a name="l05068"></a>05068 <span class="preprocessor"></span><span class="preprocessor">#define  RCC_APB2ENR_ADC2EN                  ((uint32_t)0x00000200)</span>
<a name="l05069"></a>05069 <span class="preprocessor"></span><span class="preprocessor">#define  RCC_APB2ENR_ADC3EN                  ((uint32_t)0x00000400)</span>
<a name="l05070"></a>05070 <span class="preprocessor"></span><span class="preprocessor">#define  RCC_APB2ENR_SDIOEN                  ((uint32_t)0x00000800)</span>
<a name="l05071"></a>05071 <span class="preprocessor"></span><span class="preprocessor">#define  RCC_APB2ENR_SPI1EN                  ((uint32_t)0x00001000)</span>
<a name="l05072"></a>05072 <span class="preprocessor"></span><span class="preprocessor">#define  RCC_APB2ENR_SYSCFGEN                ((uint32_t)0x00004000)</span>
<a name="l05073"></a>05073 <span class="preprocessor"></span><span class="preprocessor">#define  RCC_APB2ENR_TIM11EN                 ((uint32_t)0x00040000)</span>
<a name="l05074"></a>05074 <span class="preprocessor"></span><span class="preprocessor">#define  RCC_APB2ENR_TIM10EN                 ((uint32_t)0x00020000)</span>
<a name="l05075"></a>05075 <span class="preprocessor"></span><span class="preprocessor">#define  RCC_APB2ENR_TIM9EN                  ((uint32_t)0x00010000)</span>
<a name="l05076"></a>05076 <span class="preprocessor"></span>
<a name="l05077"></a>05077 <span class="comment">/********************  Bit definition for RCC_AHB1LPENR register  *************/</span>
<a name="l05078"></a>05078 <span class="preprocessor">#define  RCC_AHB1LPENR_GPIOALPEN             ((uint32_t)0x00000001)</span>
<a name="l05079"></a>05079 <span class="preprocessor"></span><span class="preprocessor">#define  RCC_AHB1LPENR_GPIOBLPEN             ((uint32_t)0x00000002)</span>
<a name="l05080"></a>05080 <span class="preprocessor"></span><span class="preprocessor">#define  RCC_AHB1LPENR_GPIOCLPEN             ((uint32_t)0x00000004)</span>
<a name="l05081"></a>05081 <span class="preprocessor"></span><span class="preprocessor">#define  RCC_AHB1LPENR_GPIODLPEN             ((uint32_t)0x00000008)</span>
<a name="l05082"></a>05082 <span class="preprocessor"></span><span class="preprocessor">#define  RCC_AHB1LPENR_GPIOELPEN             ((uint32_t)0x00000010)</span>
<a name="l05083"></a>05083 <span class="preprocessor"></span><span class="preprocessor">#define  RCC_AHB1LPENR_GPIOFLPEN             ((uint32_t)0x00000020)</span>
<a name="l05084"></a>05084 <span class="preprocessor"></span><span class="preprocessor">#define  RCC_AHB1LPENR_GPIOGLPEN             ((uint32_t)0x00000040)</span>
<a name="l05085"></a>05085 <span class="preprocessor"></span><span class="preprocessor">#define  RCC_AHB1LPENR_GPIOHLPEN             ((uint32_t)0x00000080)</span>
<a name="l05086"></a>05086 <span class="preprocessor"></span><span class="preprocessor">#define  RCC_AHB1LPENR_GPIOILPEN             ((uint32_t)0x00000100)</span>
<a name="l05087"></a>05087 <span class="preprocessor"></span><span class="preprocessor">#define  RCC_AHB1LPENR_CRCLPEN               ((uint32_t)0x00001000)</span>
<a name="l05088"></a>05088 <span class="preprocessor"></span><span class="preprocessor">#define  RCC_AHB1LPENR_FLITFLPEN             ((uint32_t)0x00008000)</span>
<a name="l05089"></a>05089 <span class="preprocessor"></span><span class="preprocessor">#define  RCC_AHB1LPENR_SRAM1LPEN             ((uint32_t)0x00010000)</span>
<a name="l05090"></a>05090 <span class="preprocessor"></span><span class="preprocessor">#define  RCC_AHB1LPENR_SRAM2LPEN             ((uint32_t)0x00020000)</span>
<a name="l05091"></a>05091 <span class="preprocessor"></span><span class="preprocessor">#define  RCC_AHB1LPENR_BKPSRAMLPEN           ((uint32_t)0x00040000)</span>
<a name="l05092"></a>05092 <span class="preprocessor"></span><span class="preprocessor">#define  RCC_AHB1LPENR_DMA1LPEN              ((uint32_t)0x00200000)</span>
<a name="l05093"></a>05093 <span class="preprocessor"></span><span class="preprocessor">#define  RCC_AHB1LPENR_DMA2LPEN              ((uint32_t)0x00400000)</span>
<a name="l05094"></a>05094 <span class="preprocessor"></span><span class="preprocessor">#define  RCC_AHB1LPENR_ETHMACLPEN            ((uint32_t)0x02000000)</span>
<a name="l05095"></a>05095 <span class="preprocessor"></span><span class="preprocessor">#define  RCC_AHB1LPENR_ETHMACTXLPEN          ((uint32_t)0x04000000)</span>
<a name="l05096"></a>05096 <span class="preprocessor"></span><span class="preprocessor">#define  RCC_AHB1LPENR_ETHMACRXLPEN          ((uint32_t)0x08000000)</span>
<a name="l05097"></a>05097 <span class="preprocessor"></span><span class="preprocessor">#define  RCC_AHB1LPENR_ETHMACPTPLPEN         ((uint32_t)0x10000000)</span>
<a name="l05098"></a>05098 <span class="preprocessor"></span><span class="preprocessor">#define  RCC_AHB1LPENR_OTGHSLPEN             ((uint32_t)0x20000000)</span>
<a name="l05099"></a>05099 <span class="preprocessor"></span><span class="preprocessor">#define  RCC_AHB1LPENR_OTGHSULPILPEN         ((uint32_t)0x40000000)</span>
<a name="l05100"></a>05100 <span class="preprocessor"></span>
<a name="l05101"></a>05101 <span class="comment">/********************  Bit definition for RCC_AHB2LPENR register  *************/</span>
<a name="l05102"></a>05102 <span class="preprocessor">#define  RCC_AHB2LPENR_DCMILPEN              ((uint32_t)0x00000001)</span>
<a name="l05103"></a>05103 <span class="preprocessor"></span><span class="preprocessor">#define  RCC_AHB2LPENR_CRYPLPEN              ((uint32_t)0x00000010)</span>
<a name="l05104"></a>05104 <span class="preprocessor"></span><span class="preprocessor">#define  RCC_AHB2LPENR_HASHLPEN              ((uint32_t)0x00000020)</span>
<a name="l05105"></a>05105 <span class="preprocessor"></span><span class="preprocessor">#define  RCC_AHB2LPENR_RNGLPEN               ((uint32_t)0x00000040)</span>
<a name="l05106"></a>05106 <span class="preprocessor"></span><span class="preprocessor">#define  RCC_AHB2LPENR_OTGFSLPEN             ((uint32_t)0x00000080)</span>
<a name="l05107"></a>05107 <span class="preprocessor"></span>
<a name="l05108"></a>05108 <span class="comment">/********************  Bit definition for RCC_AHB3LPENR register  *************/</span>
<a name="l05109"></a>05109 <span class="preprocessor">#define  RCC_AHB3LPENR_FSMCLPEN              ((uint32_t)0x00000001)</span>
<a name="l05110"></a>05110 <span class="preprocessor"></span>
<a name="l05111"></a>05111 <span class="comment">/********************  Bit definition for RCC_APB1LPENR register  *************/</span>
<a name="l05112"></a>05112 <span class="preprocessor">#define  RCC_APB1LPENR_TIM2LPEN              ((uint32_t)0x00000001)</span>
<a name="l05113"></a>05113 <span class="preprocessor"></span><span class="preprocessor">#define  RCC_APB1LPENR_TIM3LPEN              ((uint32_t)0x00000002)</span>
<a name="l05114"></a>05114 <span class="preprocessor"></span><span class="preprocessor">#define  RCC_APB1LPENR_TIM4LPEN              ((uint32_t)0x00000004)</span>
<a name="l05115"></a>05115 <span class="preprocessor"></span><span class="preprocessor">#define  RCC_APB1LPENR_TIM5LPEN              ((uint32_t)0x00000008)</span>
<a name="l05116"></a>05116 <span class="preprocessor"></span><span class="preprocessor">#define  RCC_APB1LPENR_TIM6LPEN              ((uint32_t)0x00000010)</span>
<a name="l05117"></a>05117 <span class="preprocessor"></span><span class="preprocessor">#define  RCC_APB1LPENR_TIM7LPEN              ((uint32_t)0x00000020)</span>
<a name="l05118"></a>05118 <span class="preprocessor"></span><span class="preprocessor">#define  RCC_APB1LPENR_TIM12LPEN             ((uint32_t)0x00000040)</span>
<a name="l05119"></a>05119 <span class="preprocessor"></span><span class="preprocessor">#define  RCC_APB1LPENR_TIM13LPEN             ((uint32_t)0x00000080)</span>
<a name="l05120"></a>05120 <span class="preprocessor"></span><span class="preprocessor">#define  RCC_APB1LPENR_TIM14LPEN             ((uint32_t)0x00000100)</span>
<a name="l05121"></a>05121 <span class="preprocessor"></span><span class="preprocessor">#define  RCC_APB1LPENR_WWDGLPEN              ((uint32_t)0x00000800)</span>
<a name="l05122"></a>05122 <span class="preprocessor"></span><span class="preprocessor">#define  RCC_APB1LPENR_SPI2LPEN              ((uint32_t)0x00004000)</span>
<a name="l05123"></a>05123 <span class="preprocessor"></span><span class="preprocessor">#define  RCC_APB1LPENR_SPI3LPEN              ((uint32_t)0x00008000)</span>
<a name="l05124"></a>05124 <span class="preprocessor"></span><span class="preprocessor">#define  RCC_APB1LPENR_USART2LPEN            ((uint32_t)0x00020000)</span>
<a name="l05125"></a>05125 <span class="preprocessor"></span><span class="preprocessor">#define  RCC_APB1LPENR_USART3LPEN            ((uint32_t)0x00040000)</span>
<a name="l05126"></a>05126 <span class="preprocessor"></span><span class="preprocessor">#define  RCC_APB1LPENR_UART4LPEN             ((uint32_t)0x00080000)</span>
<a name="l05127"></a>05127 <span class="preprocessor"></span><span class="preprocessor">#define  RCC_APB1LPENR_UART5LPEN             ((uint32_t)0x00100000)</span>
<a name="l05128"></a>05128 <span class="preprocessor"></span><span class="preprocessor">#define  RCC_APB1LPENR_I2C1LPEN              ((uint32_t)0x00200000)</span>
<a name="l05129"></a>05129 <span class="preprocessor"></span><span class="preprocessor">#define  RCC_APB1LPENR_I2C2LPEN              ((uint32_t)0x00400000)</span>
<a name="l05130"></a>05130 <span class="preprocessor"></span><span class="preprocessor">#define  RCC_APB1LPENR_I2C3LPEN              ((uint32_t)0x00800000)</span>
<a name="l05131"></a>05131 <span class="preprocessor"></span><span class="preprocessor">#define  RCC_APB1LPENR_CAN1LPEN              ((uint32_t)0x02000000)</span>
<a name="l05132"></a>05132 <span class="preprocessor"></span><span class="preprocessor">#define  RCC_APB1LPENR_CAN2LPEN              ((uint32_t)0x04000000)</span>
<a name="l05133"></a>05133 <span class="preprocessor"></span><span class="preprocessor">#define  RCC_APB1LPENR_PWRLPEN               ((uint32_t)0x10000000)</span>
<a name="l05134"></a>05134 <span class="preprocessor"></span><span class="preprocessor">#define  RCC_APB1LPENR_DACLPEN               ((uint32_t)0x20000000)</span>
<a name="l05135"></a>05135 <span class="preprocessor"></span>
<a name="l05136"></a>05136 <span class="comment">/********************  Bit definition for RCC_APB2LPENR register  *************/</span>
<a name="l05137"></a>05137 <span class="preprocessor">#define  RCC_APB2LPENR_TIM1LPEN              ((uint32_t)0x00000001)</span>
<a name="l05138"></a>05138 <span class="preprocessor"></span><span class="preprocessor">#define  RCC_APB2LPENR_TIM8LPEN              ((uint32_t)0x00000002)</span>
<a name="l05139"></a>05139 <span class="preprocessor"></span><span class="preprocessor">#define  RCC_APB2LPENR_USART1LPEN            ((uint32_t)0x00000010)</span>
<a name="l05140"></a>05140 <span class="preprocessor"></span><span class="preprocessor">#define  RCC_APB2LPENR_USART6LPEN            ((uint32_t)0x00000020)</span>
<a name="l05141"></a>05141 <span class="preprocessor"></span><span class="preprocessor">#define  RCC_APB2LPENR_ADC1LPEN              ((uint32_t)0x00000100)</span>
<a name="l05142"></a>05142 <span class="preprocessor"></span><span class="preprocessor">#define  RCC_APB2LPENR_ADC2PEN               ((uint32_t)0x00000200)</span>
<a name="l05143"></a>05143 <span class="preprocessor"></span><span class="preprocessor">#define  RCC_APB2LPENR_ADC3LPEN              ((uint32_t)0x00000400)</span>
<a name="l05144"></a>05144 <span class="preprocessor"></span><span class="preprocessor">#define  RCC_APB2LPENR_SDIOLPEN              ((uint32_t)0x00000800)</span>
<a name="l05145"></a>05145 <span class="preprocessor"></span><span class="preprocessor">#define  RCC_APB2LPENR_SPI1LPEN              ((uint32_t)0x00001000)</span>
<a name="l05146"></a>05146 <span class="preprocessor"></span><span class="preprocessor">#define  RCC_APB2LPENR_SYSCFGLPEN            ((uint32_t)0x00004000)</span>
<a name="l05147"></a>05147 <span class="preprocessor"></span><span class="preprocessor">#define  RCC_APB2LPENR_TIM9LPEN              ((uint32_t)0x00010000)</span>
<a name="l05148"></a>05148 <span class="preprocessor"></span><span class="preprocessor">#define  RCC_APB2LPENR_TIM10LPEN             ((uint32_t)0x00020000)</span>
<a name="l05149"></a>05149 <span class="preprocessor"></span><span class="preprocessor">#define  RCC_APB2LPENR_TIM11LPEN             ((uint32_t)0x00040000)</span>
<a name="l05150"></a>05150 <span class="preprocessor"></span>
<a name="l05151"></a>05151 <span class="comment">/********************  Bit definition for RCC_BDCR register  ******************/</span>
<a name="l05152"></a>05152 <span class="preprocessor">#define  RCC_BDCR_LSEON                      ((uint32_t)0x00000001)</span>
<a name="l05153"></a>05153 <span class="preprocessor"></span><span class="preprocessor">#define  RCC_BDCR_LSERDY                     ((uint32_t)0x00000002)</span>
<a name="l05154"></a>05154 <span class="preprocessor"></span><span class="preprocessor">#define  RCC_BDCR_LSEBYP                     ((uint32_t)0x00000004)</span>
<a name="l05155"></a>05155 <span class="preprocessor"></span>
<a name="l05156"></a>05156 <span class="preprocessor">#define  RCC_BDCR_RTCSEL                    ((uint32_t)0x00000300)</span>
<a name="l05157"></a>05157 <span class="preprocessor"></span><span class="preprocessor">#define  RCC_BDCR_RTCSEL_0                  ((uint32_t)0x00000100)</span>
<a name="l05158"></a>05158 <span class="preprocessor"></span><span class="preprocessor">#define  RCC_BDCR_RTCSEL_1                  ((uint32_t)0x00000200)</span>
<a name="l05159"></a>05159 <span class="preprocessor"></span>
<a name="l05160"></a>05160 <span class="preprocessor">#define  RCC_BDCR_RTCEN                      ((uint32_t)0x00008000)</span>
<a name="l05161"></a>05161 <span class="preprocessor"></span><span class="preprocessor">#define  RCC_BDCR_BDRST                      ((uint32_t)0x00010000)</span>
<a name="l05162"></a>05162 <span class="preprocessor"></span>
<a name="l05163"></a>05163 <span class="comment">/********************  Bit definition for RCC_CSR register  *******************/</span>
<a name="l05164"></a>05164 <span class="preprocessor">#define  RCC_CSR_LSION                       ((uint32_t)0x00000001)</span>
<a name="l05165"></a>05165 <span class="preprocessor"></span><span class="preprocessor">#define  RCC_CSR_LSIRDY                      ((uint32_t)0x00000002)</span>
<a name="l05166"></a>05166 <span class="preprocessor"></span><span class="preprocessor">#define  RCC_CSR_RMVF                        ((uint32_t)0x01000000)</span>
<a name="l05167"></a>05167 <span class="preprocessor"></span><span class="preprocessor">#define  RCC_CSR_BORRSTF                     ((uint32_t)0x02000000)</span>
<a name="l05168"></a>05168 <span class="preprocessor"></span><span class="preprocessor">#define  RCC_CSR_PADRSTF                     ((uint32_t)0x04000000)</span>
<a name="l05169"></a>05169 <span class="preprocessor"></span><span class="preprocessor">#define  RCC_CSR_PORRSTF                     ((uint32_t)0x08000000)</span>
<a name="l05170"></a>05170 <span class="preprocessor"></span><span class="preprocessor">#define  RCC_CSR_SFTRSTF                     ((uint32_t)0x10000000)</span>
<a name="l05171"></a>05171 <span class="preprocessor"></span><span class="preprocessor">#define  RCC_CSR_WDGRSTF                     ((uint32_t)0x20000000)</span>
<a name="l05172"></a>05172 <span class="preprocessor"></span><span class="preprocessor">#define  RCC_CSR_WWDGRSTF                    ((uint32_t)0x40000000)</span>
<a name="l05173"></a>05173 <span class="preprocessor"></span><span class="preprocessor">#define  RCC_CSR_LPWRRSTF                    ((uint32_t)0x80000000)</span>
<a name="l05174"></a>05174 <span class="preprocessor"></span>
<a name="l05175"></a>05175 <span class="comment">/********************  Bit definition for RCC_SSCGR register  *****************/</span>
<a name="l05176"></a>05176 <span class="preprocessor">#define  RCC_SSCGR_MODPER                    ((uint32_t)0x00001FFF)</span>
<a name="l05177"></a>05177 <span class="preprocessor"></span><span class="preprocessor">#define  RCC_SSCGR_INCSTEP                   ((uint32_t)0x0FFFE000)</span>
<a name="l05178"></a>05178 <span class="preprocessor"></span><span class="preprocessor">#define  RCC_SSCGR_SPREADSEL                 ((uint32_t)0x40000000)</span>
<a name="l05179"></a>05179 <span class="preprocessor"></span><span class="preprocessor">#define  RCC_SSCGR_SSCGEN                    ((uint32_t)0x80000000)</span>
<a name="l05180"></a>05180 <span class="preprocessor"></span>
<a name="l05181"></a>05181 <span class="comment">/********************  Bit definition for RCC_PLLI2SCFGR register  ************/</span>
<a name="l05182"></a>05182 <span class="preprocessor">#define  RCC_PLLI2SCFGR_PLLI2SN              ((uint32_t)0x00007FC0)</span>
<a name="l05183"></a>05183 <span class="preprocessor"></span><span class="preprocessor">#define  RCC_PLLI2SCFGR_PLLI2SR              ((uint32_t)0x70000000)</span>
<a name="l05184"></a>05184 <span class="preprocessor"></span>
<a name="l05185"></a>05185 <span class="comment">/******************************************************************************/</span>
<a name="l05186"></a>05186 <span class="comment">/*                                                                            */</span>
<a name="l05187"></a>05187 <span class="comment">/*                                    RNG                                     */</span>
<a name="l05188"></a>05188 <span class="comment">/*                                                                            */</span>
<a name="l05189"></a>05189 <span class="comment">/******************************************************************************/</span>
<a name="l05190"></a>05190 <span class="comment">/********************  Bits definition for RNG_CR register  *******************/</span>
<a name="l05191"></a>05191 <span class="preprocessor">#define RNG_CR_RNGEN                         ((uint32_t)0x00000004)</span>
<a name="l05192"></a>05192 <span class="preprocessor"></span><span class="preprocessor">#define RNG_CR_IE                            ((uint32_t)0x00000008)</span>
<a name="l05193"></a>05193 <span class="preprocessor"></span>
<a name="l05194"></a>05194 <span class="comment">/********************  Bits definition for RNG_SR register  *******************/</span>
<a name="l05195"></a>05195 <span class="preprocessor">#define RNG_SR_DRDY                          ((uint32_t)0x00000001)</span>
<a name="l05196"></a>05196 <span class="preprocessor"></span><span class="preprocessor">#define RNG_SR_CECS                          ((uint32_t)0x00000002)</span>
<a name="l05197"></a>05197 <span class="preprocessor"></span><span class="preprocessor">#define RNG_SR_SECS                          ((uint32_t)0x00000004)</span>
<a name="l05198"></a>05198 <span class="preprocessor"></span><span class="preprocessor">#define RNG_SR_CEIS                          ((uint32_t)0x00000020)</span>
<a name="l05199"></a>05199 <span class="preprocessor"></span><span class="preprocessor">#define RNG_SR_SEIS                          ((uint32_t)0x00000040)</span>
<a name="l05200"></a>05200 <span class="preprocessor"></span>
<a name="l05201"></a>05201 <span class="comment">/******************************************************************************/</span>
<a name="l05202"></a>05202 <span class="comment">/*                                                                            */</span>
<a name="l05203"></a>05203 <span class="comment">/*                           Real-Time Clock (RTC)                            */</span>
<a name="l05204"></a>05204 <span class="comment">/*                                                                            */</span>
<a name="l05205"></a>05205 <span class="comment">/******************************************************************************/</span>
<a name="l05206"></a>05206 <span class="comment">/********************  Bits definition for RTC_TR register  *******************/</span>
<a name="l05207"></a>05207 <span class="preprocessor">#define RTC_TR_PM                            ((uint32_t)0x00400000)</span>
<a name="l05208"></a>05208 <span class="preprocessor"></span><span class="preprocessor">#define RTC_TR_HT                            ((uint32_t)0x00300000)</span>
<a name="l05209"></a>05209 <span class="preprocessor"></span><span class="preprocessor">#define RTC_TR_HT_0                          ((uint32_t)0x00100000)</span>
<a name="l05210"></a>05210 <span class="preprocessor"></span><span class="preprocessor">#define RTC_TR_HT_1                          ((uint32_t)0x00200000)</span>
<a name="l05211"></a>05211 <span class="preprocessor"></span><span class="preprocessor">#define RTC_TR_HU                            ((uint32_t)0x000F0000)</span>
<a name="l05212"></a>05212 <span class="preprocessor"></span><span class="preprocessor">#define RTC_TR_HU_0                          ((uint32_t)0x00010000)</span>
<a name="l05213"></a>05213 <span class="preprocessor"></span><span class="preprocessor">#define RTC_TR_HU_1                          ((uint32_t)0x00020000)</span>
<a name="l05214"></a>05214 <span class="preprocessor"></span><span class="preprocessor">#define RTC_TR_HU_2                          ((uint32_t)0x00040000)</span>
<a name="l05215"></a>05215 <span class="preprocessor"></span><span class="preprocessor">#define RTC_TR_HU_3                          ((uint32_t)0x00080000)</span>
<a name="l05216"></a>05216 <span class="preprocessor"></span><span class="preprocessor">#define RTC_TR_MNT                           ((uint32_t)0x00007000)</span>
<a name="l05217"></a>05217 <span class="preprocessor"></span><span class="preprocessor">#define RTC_TR_MNT_0                         ((uint32_t)0x00001000)</span>
<a name="l05218"></a>05218 <span class="preprocessor"></span><span class="preprocessor">#define RTC_TR_MNT_1                         ((uint32_t)0x00002000)</span>
<a name="l05219"></a>05219 <span class="preprocessor"></span><span class="preprocessor">#define RTC_TR_MNT_2                         ((uint32_t)0x00004000)</span>
<a name="l05220"></a>05220 <span class="preprocessor"></span><span class="preprocessor">#define RTC_TR_MNU                           ((uint32_t)0x00000F00)</span>
<a name="l05221"></a>05221 <span class="preprocessor"></span><span class="preprocessor">#define RTC_TR_MNU_0                         ((uint32_t)0x00000100)</span>
<a name="l05222"></a>05222 <span class="preprocessor"></span><span class="preprocessor">#define RTC_TR_MNU_1                         ((uint32_t)0x00000200)</span>
<a name="l05223"></a>05223 <span class="preprocessor"></span><span class="preprocessor">#define RTC_TR_MNU_2                         ((uint32_t)0x00000400)</span>
<a name="l05224"></a>05224 <span class="preprocessor"></span><span class="preprocessor">#define RTC_TR_MNU_3                         ((uint32_t)0x00000800)</span>
<a name="l05225"></a>05225 <span class="preprocessor"></span><span class="preprocessor">#define RTC_TR_ST                            ((uint32_t)0x00000070)</span>
<a name="l05226"></a>05226 <span class="preprocessor"></span><span class="preprocessor">#define RTC_TR_ST_0                          ((uint32_t)0x00000010)</span>
<a name="l05227"></a>05227 <span class="preprocessor"></span><span class="preprocessor">#define RTC_TR_ST_1                          ((uint32_t)0x00000020)</span>
<a name="l05228"></a>05228 <span class="preprocessor"></span><span class="preprocessor">#define RTC_TR_ST_2                          ((uint32_t)0x00000040)</span>
<a name="l05229"></a>05229 <span class="preprocessor"></span><span class="preprocessor">#define RTC_TR_SU                            ((uint32_t)0x0000000F)</span>
<a name="l05230"></a>05230 <span class="preprocessor"></span><span class="preprocessor">#define RTC_TR_SU_0                          ((uint32_t)0x00000001)</span>
<a name="l05231"></a>05231 <span class="preprocessor"></span><span class="preprocessor">#define RTC_TR_SU_1                          ((uint32_t)0x00000002)</span>
<a name="l05232"></a>05232 <span class="preprocessor"></span><span class="preprocessor">#define RTC_TR_SU_2                          ((uint32_t)0x00000004)</span>
<a name="l05233"></a>05233 <span class="preprocessor"></span><span class="preprocessor">#define RTC_TR_SU_3                          ((uint32_t)0x00000008)</span>
<a name="l05234"></a>05234 <span class="preprocessor"></span>
<a name="l05235"></a>05235 <span class="comment">/********************  Bits definition for RTC_DR register  *******************/</span>
<a name="l05236"></a>05236 <span class="preprocessor">#define RTC_DR_YT                            ((uint32_t)0x00F00000)</span>
<a name="l05237"></a>05237 <span class="preprocessor"></span><span class="preprocessor">#define RTC_DR_YT_0                          ((uint32_t)0x00100000)</span>
<a name="l05238"></a>05238 <span class="preprocessor"></span><span class="preprocessor">#define RTC_DR_YT_1                          ((uint32_t)0x00200000)</span>
<a name="l05239"></a>05239 <span class="preprocessor"></span><span class="preprocessor">#define RTC_DR_YT_2                          ((uint32_t)0x00400000)</span>
<a name="l05240"></a>05240 <span class="preprocessor"></span><span class="preprocessor">#define RTC_DR_YT_3                          ((uint32_t)0x00800000)</span>
<a name="l05241"></a>05241 <span class="preprocessor"></span><span class="preprocessor">#define RTC_DR_YU                            ((uint32_t)0x000F0000)</span>
<a name="l05242"></a>05242 <span class="preprocessor"></span><span class="preprocessor">#define RTC_DR_YU_0                          ((uint32_t)0x00010000)</span>
<a name="l05243"></a>05243 <span class="preprocessor"></span><span class="preprocessor">#define RTC_DR_YU_1                          ((uint32_t)0x00020000)</span>
<a name="l05244"></a>05244 <span class="preprocessor"></span><span class="preprocessor">#define RTC_DR_YU_2                          ((uint32_t)0x00040000)</span>
<a name="l05245"></a>05245 <span class="preprocessor"></span><span class="preprocessor">#define RTC_DR_YU_3                          ((uint32_t)0x00080000)</span>
<a name="l05246"></a>05246 <span class="preprocessor"></span><span class="preprocessor">#define RTC_DR_WDU                           ((uint32_t)0x0000E000)</span>
<a name="l05247"></a>05247 <span class="preprocessor"></span><span class="preprocessor">#define RTC_DR_WDU_0                         ((uint32_t)0x00002000)</span>
<a name="l05248"></a>05248 <span class="preprocessor"></span><span class="preprocessor">#define RTC_DR_WDU_1                         ((uint32_t)0x00004000)</span>
<a name="l05249"></a>05249 <span class="preprocessor"></span><span class="preprocessor">#define RTC_DR_WDU_2                         ((uint32_t)0x00008000)</span>
<a name="l05250"></a>05250 <span class="preprocessor"></span><span class="preprocessor">#define RTC_DR_MT                            ((uint32_t)0x00001000)</span>
<a name="l05251"></a>05251 <span class="preprocessor"></span><span class="preprocessor">#define RTC_DR_MU                            ((uint32_t)0x00000F00)</span>
<a name="l05252"></a>05252 <span class="preprocessor"></span><span class="preprocessor">#define RTC_DR_MU_0                          ((uint32_t)0x00000100)</span>
<a name="l05253"></a>05253 <span class="preprocessor"></span><span class="preprocessor">#define RTC_DR_MU_1                          ((uint32_t)0x00000200)</span>
<a name="l05254"></a>05254 <span class="preprocessor"></span><span class="preprocessor">#define RTC_DR_MU_2                          ((uint32_t)0x00000400)</span>
<a name="l05255"></a>05255 <span class="preprocessor"></span><span class="preprocessor">#define RTC_DR_MU_3                          ((uint32_t)0x00000800)</span>
<a name="l05256"></a>05256 <span class="preprocessor"></span><span class="preprocessor">#define RTC_DR_DT                            ((uint32_t)0x00000030)</span>
<a name="l05257"></a>05257 <span class="preprocessor"></span><span class="preprocessor">#define RTC_DR_DT_0                          ((uint32_t)0x00000010)</span>
<a name="l05258"></a>05258 <span class="preprocessor"></span><span class="preprocessor">#define RTC_DR_DT_1                          ((uint32_t)0x00000020)</span>
<a name="l05259"></a>05259 <span class="preprocessor"></span><span class="preprocessor">#define RTC_DR_DU                            ((uint32_t)0x0000000F)</span>
<a name="l05260"></a>05260 <span class="preprocessor"></span><span class="preprocessor">#define RTC_DR_DU_0                          ((uint32_t)0x00000001)</span>
<a name="l05261"></a>05261 <span class="preprocessor"></span><span class="preprocessor">#define RTC_DR_DU_1                          ((uint32_t)0x00000002)</span>
<a name="l05262"></a>05262 <span class="preprocessor"></span><span class="preprocessor">#define RTC_DR_DU_2                          ((uint32_t)0x00000004)</span>
<a name="l05263"></a>05263 <span class="preprocessor"></span><span class="preprocessor">#define RTC_DR_DU_3                          ((uint32_t)0x00000008)</span>
<a name="l05264"></a>05264 <span class="preprocessor"></span>
<a name="l05265"></a>05265 <span class="comment">/********************  Bits definition for RTC_CR register  *******************/</span>
<a name="l05266"></a>05266 <span class="preprocessor">#define RTC_CR_COE                           ((uint32_t)0x00800000)</span>
<a name="l05267"></a>05267 <span class="preprocessor"></span><span class="preprocessor">#define RTC_CR_OSEL                          ((uint32_t)0x00600000)</span>
<a name="l05268"></a>05268 <span class="preprocessor"></span><span class="preprocessor">#define RTC_CR_OSEL_0                        ((uint32_t)0x00200000)</span>
<a name="l05269"></a>05269 <span class="preprocessor"></span><span class="preprocessor">#define RTC_CR_OSEL_1                        ((uint32_t)0x00400000)</span>
<a name="l05270"></a>05270 <span class="preprocessor"></span><span class="preprocessor">#define RTC_CR_POL                           ((uint32_t)0x00100000)</span>
<a name="l05271"></a>05271 <span class="preprocessor"></span><span class="preprocessor">#define RTC_CR_COSEL                         ((uint32_t)0x00080000)</span>
<a name="l05272"></a>05272 <span class="preprocessor"></span><span class="preprocessor">#define RTC_CR_BCK                           ((uint32_t)0x00040000)</span>
<a name="l05273"></a>05273 <span class="preprocessor"></span><span class="preprocessor">#define RTC_CR_SUB1H                         ((uint32_t)0x00020000)</span>
<a name="l05274"></a>05274 <span class="preprocessor"></span><span class="preprocessor">#define RTC_CR_ADD1H                         ((uint32_t)0x00010000)</span>
<a name="l05275"></a>05275 <span class="preprocessor"></span><span class="preprocessor">#define RTC_CR_TSIE                          ((uint32_t)0x00008000)</span>
<a name="l05276"></a>05276 <span class="preprocessor"></span><span class="preprocessor">#define RTC_CR_WUTIE                         ((uint32_t)0x00004000)</span>
<a name="l05277"></a>05277 <span class="preprocessor"></span><span class="preprocessor">#define RTC_CR_ALRBIE                        ((uint32_t)0x00002000)</span>
<a name="l05278"></a>05278 <span class="preprocessor"></span><span class="preprocessor">#define RTC_CR_ALRAIE                        ((uint32_t)0x00001000)</span>
<a name="l05279"></a>05279 <span class="preprocessor"></span><span class="preprocessor">#define RTC_CR_TSE                           ((uint32_t)0x00000800)</span>
<a name="l05280"></a>05280 <span class="preprocessor"></span><span class="preprocessor">#define RTC_CR_WUTE                          ((uint32_t)0x00000400)</span>
<a name="l05281"></a>05281 <span class="preprocessor"></span><span class="preprocessor">#define RTC_CR_ALRBE                         ((uint32_t)0x00000200)</span>
<a name="l05282"></a>05282 <span class="preprocessor"></span><span class="preprocessor">#define RTC_CR_ALRAE                         ((uint32_t)0x00000100)</span>
<a name="l05283"></a>05283 <span class="preprocessor"></span><span class="preprocessor">#define RTC_CR_DCE                           ((uint32_t)0x00000080)</span>
<a name="l05284"></a>05284 <span class="preprocessor"></span><span class="preprocessor">#define RTC_CR_FMT                           ((uint32_t)0x00000040)</span>
<a name="l05285"></a>05285 <span class="preprocessor"></span><span class="preprocessor">#define RTC_CR_BYPSHAD                       ((uint32_t)0x00000020)</span>
<a name="l05286"></a>05286 <span class="preprocessor"></span><span class="preprocessor">#define RTC_CR_REFCKON                       ((uint32_t)0x00000010)</span>
<a name="l05287"></a>05287 <span class="preprocessor"></span><span class="preprocessor">#define RTC_CR_TSEDGE                        ((uint32_t)0x00000008)</span>
<a name="l05288"></a>05288 <span class="preprocessor"></span><span class="preprocessor">#define RTC_CR_WUCKSEL                       ((uint32_t)0x00000007)</span>
<a name="l05289"></a>05289 <span class="preprocessor"></span><span class="preprocessor">#define RTC_CR_WUCKSEL_0                     ((uint32_t)0x00000001)</span>
<a name="l05290"></a>05290 <span class="preprocessor"></span><span class="preprocessor">#define RTC_CR_WUCKSEL_1                     ((uint32_t)0x00000002)</span>
<a name="l05291"></a>05291 <span class="preprocessor"></span><span class="preprocessor">#define RTC_CR_WUCKSEL_2                     ((uint32_t)0x00000004)</span>
<a name="l05292"></a>05292 <span class="preprocessor"></span>
<a name="l05293"></a>05293 <span class="comment">/********************  Bits definition for RTC_ISR register  ******************/</span>
<a name="l05294"></a>05294 <span class="preprocessor">#define RTC_ISR_RECALPF                      ((uint32_t)0x00010000)</span>
<a name="l05295"></a>05295 <span class="preprocessor"></span><span class="preprocessor">#define RTC_ISR_TAMP1F                       ((uint32_t)0x00002000)</span>
<a name="l05296"></a>05296 <span class="preprocessor"></span><span class="preprocessor">#define RTC_ISR_TSOVF                        ((uint32_t)0x00001000)</span>
<a name="l05297"></a>05297 <span class="preprocessor"></span><span class="preprocessor">#define RTC_ISR_TSF                          ((uint32_t)0x00000800)</span>
<a name="l05298"></a>05298 <span class="preprocessor"></span><span class="preprocessor">#define RTC_ISR_WUTF                         ((uint32_t)0x00000400)</span>
<a name="l05299"></a>05299 <span class="preprocessor"></span><span class="preprocessor">#define RTC_ISR_ALRBF                        ((uint32_t)0x00000200)</span>
<a name="l05300"></a>05300 <span class="preprocessor"></span><span class="preprocessor">#define RTC_ISR_ALRAF                        ((uint32_t)0x00000100)</span>
<a name="l05301"></a>05301 <span class="preprocessor"></span><span class="preprocessor">#define RTC_ISR_INIT                         ((uint32_t)0x00000080)</span>
<a name="l05302"></a>05302 <span class="preprocessor"></span><span class="preprocessor">#define RTC_ISR_INITF                        ((uint32_t)0x00000040)</span>
<a name="l05303"></a>05303 <span class="preprocessor"></span><span class="preprocessor">#define RTC_ISR_RSF                          ((uint32_t)0x00000020)</span>
<a name="l05304"></a>05304 <span class="preprocessor"></span><span class="preprocessor">#define RTC_ISR_INITS                        ((uint32_t)0x00000010)</span>
<a name="l05305"></a>05305 <span class="preprocessor"></span><span class="preprocessor">#define RTC_ISR_SHPF                         ((uint32_t)0x00000008)</span>
<a name="l05306"></a>05306 <span class="preprocessor"></span><span class="preprocessor">#define RTC_ISR_WUTWF                        ((uint32_t)0x00000004)</span>
<a name="l05307"></a>05307 <span class="preprocessor"></span><span class="preprocessor">#define RTC_ISR_ALRBWF                       ((uint32_t)0x00000002)</span>
<a name="l05308"></a>05308 <span class="preprocessor"></span><span class="preprocessor">#define RTC_ISR_ALRAWF                       ((uint32_t)0x00000001)</span>
<a name="l05309"></a>05309 <span class="preprocessor"></span>
<a name="l05310"></a>05310 <span class="comment">/********************  Bits definition for RTC_PRER register  *****************/</span>
<a name="l05311"></a>05311 <span class="preprocessor">#define RTC_PRER_PREDIV_A                    ((uint32_t)0x007F0000)</span>
<a name="l05312"></a>05312 <span class="preprocessor"></span><span class="preprocessor">#define RTC_PRER_PREDIV_S                    ((uint32_t)0x00001FFF)</span>
<a name="l05313"></a>05313 <span class="preprocessor"></span>
<a name="l05314"></a>05314 <span class="comment">/********************  Bits definition for RTC_WUTR register  *****************/</span>
<a name="l05315"></a>05315 <span class="preprocessor">#define RTC_WUTR_WUT                         ((uint32_t)0x0000FFFF)</span>
<a name="l05316"></a>05316 <span class="preprocessor"></span>
<a name="l05317"></a>05317 <span class="comment">/********************  Bits definition for RTC_CALIBR register  ***************/</span>
<a name="l05318"></a>05318 <span class="preprocessor">#define RTC_CALIBR_DCS                       ((uint32_t)0x00000080)</span>
<a name="l05319"></a>05319 <span class="preprocessor"></span><span class="preprocessor">#define RTC_CALIBR_DC                        ((uint32_t)0x0000001F)</span>
<a name="l05320"></a>05320 <span class="preprocessor"></span>
<a name="l05321"></a>05321 <span class="comment">/********************  Bits definition for RTC_ALRMAR register  ***************/</span>
<a name="l05322"></a>05322 <span class="preprocessor">#define RTC_ALRMAR_MSK4                      ((uint32_t)0x80000000)</span>
<a name="l05323"></a>05323 <span class="preprocessor"></span><span class="preprocessor">#define RTC_ALRMAR_WDSEL                     ((uint32_t)0x40000000)</span>
<a name="l05324"></a>05324 <span class="preprocessor"></span><span class="preprocessor">#define RTC_ALRMAR_DT                        ((uint32_t)0x30000000)</span>
<a name="l05325"></a>05325 <span class="preprocessor"></span><span class="preprocessor">#define RTC_ALRMAR_DT_0                      ((uint32_t)0x10000000)</span>
<a name="l05326"></a>05326 <span class="preprocessor"></span><span class="preprocessor">#define RTC_ALRMAR_DT_1                      ((uint32_t)0x20000000)</span>
<a name="l05327"></a>05327 <span class="preprocessor"></span><span class="preprocessor">#define RTC_ALRMAR_DU                        ((uint32_t)0x0F000000)</span>
<a name="l05328"></a>05328 <span class="preprocessor"></span><span class="preprocessor">#define RTC_ALRMAR_DU_0                      ((uint32_t)0x01000000)</span>
<a name="l05329"></a>05329 <span class="preprocessor"></span><span class="preprocessor">#define RTC_ALRMAR_DU_1                      ((uint32_t)0x02000000)</span>
<a name="l05330"></a>05330 <span class="preprocessor"></span><span class="preprocessor">#define RTC_ALRMAR_DU_2                      ((uint32_t)0x04000000)</span>
<a name="l05331"></a>05331 <span class="preprocessor"></span><span class="preprocessor">#define RTC_ALRMAR_DU_3                      ((uint32_t)0x08000000)</span>
<a name="l05332"></a>05332 <span class="preprocessor"></span><span class="preprocessor">#define RTC_ALRMAR_MSK3                      ((uint32_t)0x00800000)</span>
<a name="l05333"></a>05333 <span class="preprocessor"></span><span class="preprocessor">#define RTC_ALRMAR_PM                        ((uint32_t)0x00400000)</span>
<a name="l05334"></a>05334 <span class="preprocessor"></span><span class="preprocessor">#define RTC_ALRMAR_HT                        ((uint32_t)0x00300000)</span>
<a name="l05335"></a>05335 <span class="preprocessor"></span><span class="preprocessor">#define RTC_ALRMAR_HT_0                      ((uint32_t)0x00100000)</span>
<a name="l05336"></a>05336 <span class="preprocessor"></span><span class="preprocessor">#define RTC_ALRMAR_HT_1                      ((uint32_t)0x00200000)</span>
<a name="l05337"></a>05337 <span class="preprocessor"></span><span class="preprocessor">#define RTC_ALRMAR_HU                        ((uint32_t)0x000F0000)</span>
<a name="l05338"></a>05338 <span class="preprocessor"></span><span class="preprocessor">#define RTC_ALRMAR_HU_0                      ((uint32_t)0x00010000)</span>
<a name="l05339"></a>05339 <span class="preprocessor"></span><span class="preprocessor">#define RTC_ALRMAR_HU_1                      ((uint32_t)0x00020000)</span>
<a name="l05340"></a>05340 <span class="preprocessor"></span><span class="preprocessor">#define RTC_ALRMAR_HU_2                      ((uint32_t)0x00040000)</span>
<a name="l05341"></a>05341 <span class="preprocessor"></span><span class="preprocessor">#define RTC_ALRMAR_HU_3                      ((uint32_t)0x00080000)</span>
<a name="l05342"></a>05342 <span class="preprocessor"></span><span class="preprocessor">#define RTC_ALRMAR_MSK2                      ((uint32_t)0x00008000)</span>
<a name="l05343"></a>05343 <span class="preprocessor"></span><span class="preprocessor">#define RTC_ALRMAR_MNT                       ((uint32_t)0x00007000)</span>
<a name="l05344"></a>05344 <span class="preprocessor"></span><span class="preprocessor">#define RTC_ALRMAR_MNT_0                     ((uint32_t)0x00001000)</span>
<a name="l05345"></a>05345 <span class="preprocessor"></span><span class="preprocessor">#define RTC_ALRMAR_MNT_1                     ((uint32_t)0x00002000)</span>
<a name="l05346"></a>05346 <span class="preprocessor"></span><span class="preprocessor">#define RTC_ALRMAR_MNT_2                     ((uint32_t)0x00004000)</span>
<a name="l05347"></a>05347 <span class="preprocessor"></span><span class="preprocessor">#define RTC_ALRMAR_MNU                       ((uint32_t)0x00000F00)</span>
<a name="l05348"></a>05348 <span class="preprocessor"></span><span class="preprocessor">#define RTC_ALRMAR_MNU_0                     ((uint32_t)0x00000100)</span>
<a name="l05349"></a>05349 <span class="preprocessor"></span><span class="preprocessor">#define RTC_ALRMAR_MNU_1                     ((uint32_t)0x00000200)</span>
<a name="l05350"></a>05350 <span class="preprocessor"></span><span class="preprocessor">#define RTC_ALRMAR_MNU_2                     ((uint32_t)0x00000400)</span>
<a name="l05351"></a>05351 <span class="preprocessor"></span><span class="preprocessor">#define RTC_ALRMAR_MNU_3                     ((uint32_t)0x00000800)</span>
<a name="l05352"></a>05352 <span class="preprocessor"></span><span class="preprocessor">#define RTC_ALRMAR_MSK1                      ((uint32_t)0x00000080)</span>
<a name="l05353"></a>05353 <span class="preprocessor"></span><span class="preprocessor">#define RTC_ALRMAR_ST                        ((uint32_t)0x00000070)</span>
<a name="l05354"></a>05354 <span class="preprocessor"></span><span class="preprocessor">#define RTC_ALRMAR_ST_0                      ((uint32_t)0x00000010)</span>
<a name="l05355"></a>05355 <span class="preprocessor"></span><span class="preprocessor">#define RTC_ALRMAR_ST_1                      ((uint32_t)0x00000020)</span>
<a name="l05356"></a>05356 <span class="preprocessor"></span><span class="preprocessor">#define RTC_ALRMAR_ST_2                      ((uint32_t)0x00000040)</span>
<a name="l05357"></a>05357 <span class="preprocessor"></span><span class="preprocessor">#define RTC_ALRMAR_SU                        ((uint32_t)0x0000000F)</span>
<a name="l05358"></a>05358 <span class="preprocessor"></span><span class="preprocessor">#define RTC_ALRMAR_SU_0                      ((uint32_t)0x00000001)</span>
<a name="l05359"></a>05359 <span class="preprocessor"></span><span class="preprocessor">#define RTC_ALRMAR_SU_1                      ((uint32_t)0x00000002)</span>
<a name="l05360"></a>05360 <span class="preprocessor"></span><span class="preprocessor">#define RTC_ALRMAR_SU_2                      ((uint32_t)0x00000004)</span>
<a name="l05361"></a>05361 <span class="preprocessor"></span><span class="preprocessor">#define RTC_ALRMAR_SU_3                      ((uint32_t)0x00000008)</span>
<a name="l05362"></a>05362 <span class="preprocessor"></span>
<a name="l05363"></a>05363 <span class="comment">/********************  Bits definition for RTC_ALRMBR register  ***************/</span>
<a name="l05364"></a>05364 <span class="preprocessor">#define RTC_ALRMBR_MSK4                      ((uint32_t)0x80000000)</span>
<a name="l05365"></a>05365 <span class="preprocessor"></span><span class="preprocessor">#define RTC_ALRMBR_WDSEL                     ((uint32_t)0x40000000)</span>
<a name="l05366"></a>05366 <span class="preprocessor"></span><span class="preprocessor">#define RTC_ALRMBR_DT                        ((uint32_t)0x30000000)</span>
<a name="l05367"></a>05367 <span class="preprocessor"></span><span class="preprocessor">#define RTC_ALRMBR_DT_0                      ((uint32_t)0x10000000)</span>
<a name="l05368"></a>05368 <span class="preprocessor"></span><span class="preprocessor">#define RTC_ALRMBR_DT_1                      ((uint32_t)0x20000000)</span>
<a name="l05369"></a>05369 <span class="preprocessor"></span><span class="preprocessor">#define RTC_ALRMBR_DU                        ((uint32_t)0x0F000000)</span>
<a name="l05370"></a>05370 <span class="preprocessor"></span><span class="preprocessor">#define RTC_ALRMBR_DU_0                      ((uint32_t)0x01000000)</span>
<a name="l05371"></a>05371 <span class="preprocessor"></span><span class="preprocessor">#define RTC_ALRMBR_DU_1                      ((uint32_t)0x02000000)</span>
<a name="l05372"></a>05372 <span class="preprocessor"></span><span class="preprocessor">#define RTC_ALRMBR_DU_2                      ((uint32_t)0x04000000)</span>
<a name="l05373"></a>05373 <span class="preprocessor"></span><span class="preprocessor">#define RTC_ALRMBR_DU_3                      ((uint32_t)0x08000000)</span>
<a name="l05374"></a>05374 <span class="preprocessor"></span><span class="preprocessor">#define RTC_ALRMBR_MSK3                      ((uint32_t)0x00800000)</span>
<a name="l05375"></a>05375 <span class="preprocessor"></span><span class="preprocessor">#define RTC_ALRMBR_PM                        ((uint32_t)0x00400000)</span>
<a name="l05376"></a>05376 <span class="preprocessor"></span><span class="preprocessor">#define RTC_ALRMBR_HT                        ((uint32_t)0x00300000)</span>
<a name="l05377"></a>05377 <span class="preprocessor"></span><span class="preprocessor">#define RTC_ALRMBR_HT_0                      ((uint32_t)0x00100000)</span>
<a name="l05378"></a>05378 <span class="preprocessor"></span><span class="preprocessor">#define RTC_ALRMBR_HT_1                      ((uint32_t)0x00200000)</span>
<a name="l05379"></a>05379 <span class="preprocessor"></span><span class="preprocessor">#define RTC_ALRMBR_HU                        ((uint32_t)0x000F0000)</span>
<a name="l05380"></a>05380 <span class="preprocessor"></span><span class="preprocessor">#define RTC_ALRMBR_HU_0                      ((uint32_t)0x00010000)</span>
<a name="l05381"></a>05381 <span class="preprocessor"></span><span class="preprocessor">#define RTC_ALRMBR_HU_1                      ((uint32_t)0x00020000)</span>
<a name="l05382"></a>05382 <span class="preprocessor"></span><span class="preprocessor">#define RTC_ALRMBR_HU_2                      ((uint32_t)0x00040000)</span>
<a name="l05383"></a>05383 <span class="preprocessor"></span><span class="preprocessor">#define RTC_ALRMBR_HU_3                      ((uint32_t)0x00080000)</span>
<a name="l05384"></a>05384 <span class="preprocessor"></span><span class="preprocessor">#define RTC_ALRMBR_MSK2                      ((uint32_t)0x00008000)</span>
<a name="l05385"></a>05385 <span class="preprocessor"></span><span class="preprocessor">#define RTC_ALRMBR_MNT                       ((uint32_t)0x00007000)</span>
<a name="l05386"></a>05386 <span class="preprocessor"></span><span class="preprocessor">#define RTC_ALRMBR_MNT_0                     ((uint32_t)0x00001000)</span>
<a name="l05387"></a>05387 <span class="preprocessor"></span><span class="preprocessor">#define RTC_ALRMBR_MNT_1                     ((uint32_t)0x00002000)</span>
<a name="l05388"></a>05388 <span class="preprocessor"></span><span class="preprocessor">#define RTC_ALRMBR_MNT_2                     ((uint32_t)0x00004000)</span>
<a name="l05389"></a>05389 <span class="preprocessor"></span><span class="preprocessor">#define RTC_ALRMBR_MNU                       ((uint32_t)0x00000F00)</span>
<a name="l05390"></a>05390 <span class="preprocessor"></span><span class="preprocessor">#define RTC_ALRMBR_MNU_0                     ((uint32_t)0x00000100)</span>
<a name="l05391"></a>05391 <span class="preprocessor"></span><span class="preprocessor">#define RTC_ALRMBR_MNU_1                     ((uint32_t)0x00000200)</span>
<a name="l05392"></a>05392 <span class="preprocessor"></span><span class="preprocessor">#define RTC_ALRMBR_MNU_2                     ((uint32_t)0x00000400)</span>
<a name="l05393"></a>05393 <span class="preprocessor"></span><span class="preprocessor">#define RTC_ALRMBR_MNU_3                     ((uint32_t)0x00000800)</span>
<a name="l05394"></a>05394 <span class="preprocessor"></span><span class="preprocessor">#define RTC_ALRMBR_MSK1                      ((uint32_t)0x00000080)</span>
<a name="l05395"></a>05395 <span class="preprocessor"></span><span class="preprocessor">#define RTC_ALRMBR_ST                        ((uint32_t)0x00000070)</span>
<a name="l05396"></a>05396 <span class="preprocessor"></span><span class="preprocessor">#define RTC_ALRMBR_ST_0                      ((uint32_t)0x00000010)</span>
<a name="l05397"></a>05397 <span class="preprocessor"></span><span class="preprocessor">#define RTC_ALRMBR_ST_1                      ((uint32_t)0x00000020)</span>
<a name="l05398"></a>05398 <span class="preprocessor"></span><span class="preprocessor">#define RTC_ALRMBR_ST_2                      ((uint32_t)0x00000040)</span>
<a name="l05399"></a>05399 <span class="preprocessor"></span><span class="preprocessor">#define RTC_ALRMBR_SU                        ((uint32_t)0x0000000F)</span>
<a name="l05400"></a>05400 <span class="preprocessor"></span><span class="preprocessor">#define RTC_ALRMBR_SU_0                      ((uint32_t)0x00000001)</span>
<a name="l05401"></a>05401 <span class="preprocessor"></span><span class="preprocessor">#define RTC_ALRMBR_SU_1                      ((uint32_t)0x00000002)</span>
<a name="l05402"></a>05402 <span class="preprocessor"></span><span class="preprocessor">#define RTC_ALRMBR_SU_2                      ((uint32_t)0x00000004)</span>
<a name="l05403"></a>05403 <span class="preprocessor"></span><span class="preprocessor">#define RTC_ALRMBR_SU_3                      ((uint32_t)0x00000008)</span>
<a name="l05404"></a>05404 <span class="preprocessor"></span>
<a name="l05405"></a>05405 <span class="comment">/********************  Bits definition for RTC_WPR register  ******************/</span>
<a name="l05406"></a>05406 <span class="preprocessor">#define RTC_WPR_KEY                          ((uint32_t)0x000000FF)</span>
<a name="l05407"></a>05407 <span class="preprocessor"></span>
<a name="l05408"></a>05408 <span class="comment">/********************  Bits definition for RTC_SSR register  ******************/</span>
<a name="l05409"></a>05409 <span class="preprocessor">#define RTC_SSR_SS                           ((uint32_t)0x0000FFFF)</span>
<a name="l05410"></a>05410 <span class="preprocessor"></span>
<a name="l05411"></a>05411 <span class="comment">/********************  Bits definition for RTC_SHIFTR register  ***************/</span>
<a name="l05412"></a>05412 <span class="preprocessor">#define RTC_SHIFTR_SUBFS                     ((uint32_t)0x00007FFF)</span>
<a name="l05413"></a>05413 <span class="preprocessor"></span><span class="preprocessor">#define RTC_SHIFTR_ADD1S                     ((uint32_t)0x80000000)</span>
<a name="l05414"></a>05414 <span class="preprocessor"></span>
<a name="l05415"></a>05415 <span class="comment">/********************  Bits definition for RTC_TSTR register  *****************/</span>
<a name="l05416"></a>05416 <span class="preprocessor">#define RTC_TSTR_PM                          ((uint32_t)0x00400000)</span>
<a name="l05417"></a>05417 <span class="preprocessor"></span><span class="preprocessor">#define RTC_TSTR_HT                          ((uint32_t)0x00300000)</span>
<a name="l05418"></a>05418 <span class="preprocessor"></span><span class="preprocessor">#define RTC_TSTR_HT_0                        ((uint32_t)0x00100000)</span>
<a name="l05419"></a>05419 <span class="preprocessor"></span><span class="preprocessor">#define RTC_TSTR_HT_1                        ((uint32_t)0x00200000)</span>
<a name="l05420"></a>05420 <span class="preprocessor"></span><span class="preprocessor">#define RTC_TSTR_HU                          ((uint32_t)0x000F0000)</span>
<a name="l05421"></a>05421 <span class="preprocessor"></span><span class="preprocessor">#define RTC_TSTR_HU_0                        ((uint32_t)0x00010000)</span>
<a name="l05422"></a>05422 <span class="preprocessor"></span><span class="preprocessor">#define RTC_TSTR_HU_1                        ((uint32_t)0x00020000)</span>
<a name="l05423"></a>05423 <span class="preprocessor"></span><span class="preprocessor">#define RTC_TSTR_HU_2                        ((uint32_t)0x00040000)</span>
<a name="l05424"></a>05424 <span class="preprocessor"></span><span class="preprocessor">#define RTC_TSTR_HU_3                        ((uint32_t)0x00080000)</span>
<a name="l05425"></a>05425 <span class="preprocessor"></span><span class="preprocessor">#define RTC_TSTR_MNT                         ((uint32_t)0x00007000)</span>
<a name="l05426"></a>05426 <span class="preprocessor"></span><span class="preprocessor">#define RTC_TSTR_MNT_0                       ((uint32_t)0x00001000)</span>
<a name="l05427"></a>05427 <span class="preprocessor"></span><span class="preprocessor">#define RTC_TSTR_MNT_1                       ((uint32_t)0x00002000)</span>
<a name="l05428"></a>05428 <span class="preprocessor"></span><span class="preprocessor">#define RTC_TSTR_MNT_2                       ((uint32_t)0x00004000)</span>
<a name="l05429"></a>05429 <span class="preprocessor"></span><span class="preprocessor">#define RTC_TSTR_MNU                         ((uint32_t)0x00000F00)</span>
<a name="l05430"></a>05430 <span class="preprocessor"></span><span class="preprocessor">#define RTC_TSTR_MNU_0                       ((uint32_t)0x00000100)</span>
<a name="l05431"></a>05431 <span class="preprocessor"></span><span class="preprocessor">#define RTC_TSTR_MNU_1                       ((uint32_t)0x00000200)</span>
<a name="l05432"></a>05432 <span class="preprocessor"></span><span class="preprocessor">#define RTC_TSTR_MNU_2                       ((uint32_t)0x00000400)</span>
<a name="l05433"></a>05433 <span class="preprocessor"></span><span class="preprocessor">#define RTC_TSTR_MNU_3                       ((uint32_t)0x00000800)</span>
<a name="l05434"></a>05434 <span class="preprocessor"></span><span class="preprocessor">#define RTC_TSTR_ST                          ((uint32_t)0x00000070)</span>
<a name="l05435"></a>05435 <span class="preprocessor"></span><span class="preprocessor">#define RTC_TSTR_ST_0                        ((uint32_t)0x00000010)</span>
<a name="l05436"></a>05436 <span class="preprocessor"></span><span class="preprocessor">#define RTC_TSTR_ST_1                        ((uint32_t)0x00000020)</span>
<a name="l05437"></a>05437 <span class="preprocessor"></span><span class="preprocessor">#define RTC_TSTR_ST_2                        ((uint32_t)0x00000040)</span>
<a name="l05438"></a>05438 <span class="preprocessor"></span><span class="preprocessor">#define RTC_TSTR_SU                          ((uint32_t)0x0000000F)</span>
<a name="l05439"></a>05439 <span class="preprocessor"></span><span class="preprocessor">#define RTC_TSTR_SU_0                        ((uint32_t)0x00000001)</span>
<a name="l05440"></a>05440 <span class="preprocessor"></span><span class="preprocessor">#define RTC_TSTR_SU_1                        ((uint32_t)0x00000002)</span>
<a name="l05441"></a>05441 <span class="preprocessor"></span><span class="preprocessor">#define RTC_TSTR_SU_2                        ((uint32_t)0x00000004)</span>
<a name="l05442"></a>05442 <span class="preprocessor"></span><span class="preprocessor">#define RTC_TSTR_SU_3                        ((uint32_t)0x00000008)</span>
<a name="l05443"></a>05443 <span class="preprocessor"></span>
<a name="l05444"></a>05444 <span class="comment">/********************  Bits definition for RTC_TSDR register  *****************/</span>
<a name="l05445"></a>05445 <span class="preprocessor">#define RTC_TSDR_WDU                         ((uint32_t)0x0000E000)</span>
<a name="l05446"></a>05446 <span class="preprocessor"></span><span class="preprocessor">#define RTC_TSDR_WDU_0                       ((uint32_t)0x00002000)</span>
<a name="l05447"></a>05447 <span class="preprocessor"></span><span class="preprocessor">#define RTC_TSDR_WDU_1                       ((uint32_t)0x00004000)</span>
<a name="l05448"></a>05448 <span class="preprocessor"></span><span class="preprocessor">#define RTC_TSDR_WDU_2                       ((uint32_t)0x00008000)</span>
<a name="l05449"></a>05449 <span class="preprocessor"></span><span class="preprocessor">#define RTC_TSDR_MT                          ((uint32_t)0x00001000)</span>
<a name="l05450"></a>05450 <span class="preprocessor"></span><span class="preprocessor">#define RTC_TSDR_MU                          ((uint32_t)0x00000F00)</span>
<a name="l05451"></a>05451 <span class="preprocessor"></span><span class="preprocessor">#define RTC_TSDR_MU_0                        ((uint32_t)0x00000100)</span>
<a name="l05452"></a>05452 <span class="preprocessor"></span><span class="preprocessor">#define RTC_TSDR_MU_1                        ((uint32_t)0x00000200)</span>
<a name="l05453"></a>05453 <span class="preprocessor"></span><span class="preprocessor">#define RTC_TSDR_MU_2                        ((uint32_t)0x00000400)</span>
<a name="l05454"></a>05454 <span class="preprocessor"></span><span class="preprocessor">#define RTC_TSDR_MU_3                        ((uint32_t)0x00000800)</span>
<a name="l05455"></a>05455 <span class="preprocessor"></span><span class="preprocessor">#define RTC_TSDR_DT                          ((uint32_t)0x00000030)</span>
<a name="l05456"></a>05456 <span class="preprocessor"></span><span class="preprocessor">#define RTC_TSDR_DT_0                        ((uint32_t)0x00000010)</span>
<a name="l05457"></a>05457 <span class="preprocessor"></span><span class="preprocessor">#define RTC_TSDR_DT_1                        ((uint32_t)0x00000020)</span>
<a name="l05458"></a>05458 <span class="preprocessor"></span><span class="preprocessor">#define RTC_TSDR_DU                          ((uint32_t)0x0000000F)</span>
<a name="l05459"></a>05459 <span class="preprocessor"></span><span class="preprocessor">#define RTC_TSDR_DU_0                        ((uint32_t)0x00000001)</span>
<a name="l05460"></a>05460 <span class="preprocessor"></span><span class="preprocessor">#define RTC_TSDR_DU_1                        ((uint32_t)0x00000002)</span>
<a name="l05461"></a>05461 <span class="preprocessor"></span><span class="preprocessor">#define RTC_TSDR_DU_2                        ((uint32_t)0x00000004)</span>
<a name="l05462"></a>05462 <span class="preprocessor"></span><span class="preprocessor">#define RTC_TSDR_DU_3                        ((uint32_t)0x00000008)</span>
<a name="l05463"></a>05463 <span class="preprocessor"></span>
<a name="l05464"></a>05464 <span class="comment">/********************  Bits definition for RTC_TSSSR register  ****************/</span>
<a name="l05465"></a>05465 <span class="preprocessor">#define RTC_TSSSR_SS                         ((uint32_t)0x0000FFFF)</span>
<a name="l05466"></a>05466 <span class="preprocessor"></span>
<a name="l05467"></a>05467 <span class="comment">/********************  Bits definition for RTC_CAL register  *****************/</span>
<a name="l05468"></a>05468 <span class="preprocessor">#define RTC_CALR_CALP                        ((uint32_t)0x00008000)</span>
<a name="l05469"></a>05469 <span class="preprocessor"></span><span class="preprocessor">#define RTC_CALR_CALW8                       ((uint32_t)0x00004000)</span>
<a name="l05470"></a>05470 <span class="preprocessor"></span><span class="preprocessor">#define RTC_CALR_CALW16                      ((uint32_t)0x00002000)</span>
<a name="l05471"></a>05471 <span class="preprocessor"></span><span class="preprocessor">#define RTC_CALR_CALM                        ((uint32_t)0x000001FF)</span>
<a name="l05472"></a>05472 <span class="preprocessor"></span><span class="preprocessor">#define RTC_CALR_CALM_0                      ((uint32_t)0x00000001)</span>
<a name="l05473"></a>05473 <span class="preprocessor"></span><span class="preprocessor">#define RTC_CALR_CALM_1                      ((uint32_t)0x00000002)</span>
<a name="l05474"></a>05474 <span class="preprocessor"></span><span class="preprocessor">#define RTC_CALR_CALM_2                      ((uint32_t)0x00000004)</span>
<a name="l05475"></a>05475 <span class="preprocessor"></span><span class="preprocessor">#define RTC_CALR_CALM_3                      ((uint32_t)0x00000008)</span>
<a name="l05476"></a>05476 <span class="preprocessor"></span><span class="preprocessor">#define RTC_CALR_CALM_4                      ((uint32_t)0x00000010)</span>
<a name="l05477"></a>05477 <span class="preprocessor"></span><span class="preprocessor">#define RTC_CALR_CALM_5                      ((uint32_t)0x00000020)</span>
<a name="l05478"></a>05478 <span class="preprocessor"></span><span class="preprocessor">#define RTC_CALR_CALM_6                      ((uint32_t)0x00000040)</span>
<a name="l05479"></a>05479 <span class="preprocessor"></span><span class="preprocessor">#define RTC_CALR_CALM_7                      ((uint32_t)0x00000080)</span>
<a name="l05480"></a>05480 <span class="preprocessor"></span><span class="preprocessor">#define RTC_CALR_CALM_8                      ((uint32_t)0x00000100)</span>
<a name="l05481"></a>05481 <span class="preprocessor"></span>
<a name="l05482"></a>05482 <span class="comment">/********************  Bits definition for RTC_TAFCR register  ****************/</span>
<a name="l05483"></a>05483 <span class="preprocessor">#define RTC_TAFCR_ALARMOUTTYPE               ((uint32_t)0x00040000)</span>
<a name="l05484"></a>05484 <span class="preprocessor"></span><span class="preprocessor">#define RTC_TAFCR_TSINSEL                    ((uint32_t)0x00020000)</span>
<a name="l05485"></a>05485 <span class="preprocessor"></span><span class="preprocessor">#define RTC_TAFCR_TAMPINSEL                  ((uint32_t)0x00010000)</span>
<a name="l05486"></a>05486 <span class="preprocessor"></span><span class="preprocessor">#define RTC_TAFCR_TAMPPUDIS                  ((uint32_t)0x00008000)</span>
<a name="l05487"></a>05487 <span class="preprocessor"></span><span class="preprocessor">#define RTC_TAFCR_TAMPPRCH                   ((uint32_t)0x00006000)</span>
<a name="l05488"></a>05488 <span class="preprocessor"></span><span class="preprocessor">#define RTC_TAFCR_TAMPPRCH_0                 ((uint32_t)0x00002000)</span>
<a name="l05489"></a>05489 <span class="preprocessor"></span><span class="preprocessor">#define RTC_TAFCR_TAMPPRCH_1                 ((uint32_t)0x00004000)</span>
<a name="l05490"></a>05490 <span class="preprocessor"></span><span class="preprocessor">#define RTC_TAFCR_TAMPFLT                    ((uint32_t)0x00001800)</span>
<a name="l05491"></a>05491 <span class="preprocessor"></span><span class="preprocessor">#define RTC_TAFCR_TAMPFLT_0                  ((uint32_t)0x00000800)</span>
<a name="l05492"></a>05492 <span class="preprocessor"></span><span class="preprocessor">#define RTC_TAFCR_TAMPFLT_1                  ((uint32_t)0x00001000)</span>
<a name="l05493"></a>05493 <span class="preprocessor"></span><span class="preprocessor">#define RTC_TAFCR_TAMPFREQ                   ((uint32_t)0x00000700)</span>
<a name="l05494"></a>05494 <span class="preprocessor"></span><span class="preprocessor">#define RTC_TAFCR_TAMPFREQ_0                 ((uint32_t)0x00000100)</span>
<a name="l05495"></a>05495 <span class="preprocessor"></span><span class="preprocessor">#define RTC_TAFCR_TAMPFREQ_1                 ((uint32_t)0x00000200)</span>
<a name="l05496"></a>05496 <span class="preprocessor"></span><span class="preprocessor">#define RTC_TAFCR_TAMPFREQ_2                 ((uint32_t)0x00000400)</span>
<a name="l05497"></a>05497 <span class="preprocessor"></span><span class="preprocessor">#define RTC_TAFCR_TAMPTS                     ((uint32_t)0x00000080)</span>
<a name="l05498"></a>05498 <span class="preprocessor"></span><span class="preprocessor">#define RTC_TAFCR_TAMPIE                     ((uint32_t)0x00000004)</span>
<a name="l05499"></a>05499 <span class="preprocessor"></span><span class="preprocessor">#define RTC_TAFCR_TAMP1TRG                   ((uint32_t)0x00000002)</span>
<a name="l05500"></a>05500 <span class="preprocessor"></span><span class="preprocessor">#define RTC_TAFCR_TAMP1E                     ((uint32_t)0x00000001)</span>
<a name="l05501"></a>05501 <span class="preprocessor"></span>
<a name="l05502"></a>05502 <span class="comment">/********************  Bits definition for RTC_ALRMASSR register  *************/</span>
<a name="l05503"></a>05503 <span class="preprocessor">#define RTC_ALRMASSR_MASKSS                  ((uint32_t)0x0F000000)</span>
<a name="l05504"></a>05504 <span class="preprocessor"></span><span class="preprocessor">#define RTC_ALRMASSR_MASKSS_0                ((uint32_t)0x01000000)</span>
<a name="l05505"></a>05505 <span class="preprocessor"></span><span class="preprocessor">#define RTC_ALRMASSR_MASKSS_1                ((uint32_t)0x02000000)</span>
<a name="l05506"></a>05506 <span class="preprocessor"></span><span class="preprocessor">#define RTC_ALRMASSR_MASKSS_2                ((uint32_t)0x04000000)</span>
<a name="l05507"></a>05507 <span class="preprocessor"></span><span class="preprocessor">#define RTC_ALRMASSR_MASKSS_3                ((uint32_t)0x08000000)</span>
<a name="l05508"></a>05508 <span class="preprocessor"></span><span class="preprocessor">#define RTC_ALRMASSR_SS                      ((uint32_t)0x00007FFF)</span>
<a name="l05509"></a>05509 <span class="preprocessor"></span>
<a name="l05510"></a>05510 <span class="comment">/********************  Bits definition for RTC_ALRMBSSR register  *************/</span>
<a name="l05511"></a>05511 <span class="preprocessor">#define RTC_ALRMBSSR_MASKSS                  ((uint32_t)0x0F000000)</span>
<a name="l05512"></a>05512 <span class="preprocessor"></span><span class="preprocessor">#define RTC_ALRMBSSR_MASKSS_0                ((uint32_t)0x01000000)</span>
<a name="l05513"></a>05513 <span class="preprocessor"></span><span class="preprocessor">#define RTC_ALRMBSSR_MASKSS_1                ((uint32_t)0x02000000)</span>
<a name="l05514"></a>05514 <span class="preprocessor"></span><span class="preprocessor">#define RTC_ALRMBSSR_MASKSS_2                ((uint32_t)0x04000000)</span>
<a name="l05515"></a>05515 <span class="preprocessor"></span><span class="preprocessor">#define RTC_ALRMBSSR_MASKSS_3                ((uint32_t)0x08000000)</span>
<a name="l05516"></a>05516 <span class="preprocessor"></span><span class="preprocessor">#define RTC_ALRMBSSR_SS                      ((uint32_t)0x00007FFF)</span>
<a name="l05517"></a>05517 <span class="preprocessor"></span>
<a name="l05518"></a>05518 <span class="comment">/********************  Bits definition for RTC_BKP0R register  ****************/</span>
<a name="l05519"></a>05519 <span class="preprocessor">#define RTC_BKP0R                            ((uint32_t)0xFFFFFFFF)</span>
<a name="l05520"></a>05520 <span class="preprocessor"></span>
<a name="l05521"></a>05521 <span class="comment">/********************  Bits definition for RTC_BKP1R register  ****************/</span>
<a name="l05522"></a>05522 <span class="preprocessor">#define RTC_BKP1R                            ((uint32_t)0xFFFFFFFF)</span>
<a name="l05523"></a>05523 <span class="preprocessor"></span>
<a name="l05524"></a>05524 <span class="comment">/********************  Bits definition for RTC_BKP2R register  ****************/</span>
<a name="l05525"></a>05525 <span class="preprocessor">#define RTC_BKP2R                            ((uint32_t)0xFFFFFFFF)</span>
<a name="l05526"></a>05526 <span class="preprocessor"></span>
<a name="l05527"></a>05527 <span class="comment">/********************  Bits definition for RTC_BKP3R register  ****************/</span>
<a name="l05528"></a>05528 <span class="preprocessor">#define RTC_BKP3R                            ((uint32_t)0xFFFFFFFF)</span>
<a name="l05529"></a>05529 <span class="preprocessor"></span>
<a name="l05530"></a>05530 <span class="comment">/********************  Bits definition for RTC_BKP4R register  ****************/</span>
<a name="l05531"></a>05531 <span class="preprocessor">#define RTC_BKP4R                            ((uint32_t)0xFFFFFFFF)</span>
<a name="l05532"></a>05532 <span class="preprocessor"></span>
<a name="l05533"></a>05533 <span class="comment">/********************  Bits definition for RTC_BKP5R register  ****************/</span>
<a name="l05534"></a>05534 <span class="preprocessor">#define RTC_BKP5R                            ((uint32_t)0xFFFFFFFF)</span>
<a name="l05535"></a>05535 <span class="preprocessor"></span>
<a name="l05536"></a>05536 <span class="comment">/********************  Bits definition for RTC_BKP6R register  ****************/</span>
<a name="l05537"></a>05537 <span class="preprocessor">#define RTC_BKP6R                            ((uint32_t)0xFFFFFFFF)</span>
<a name="l05538"></a>05538 <span class="preprocessor"></span>
<a name="l05539"></a>05539 <span class="comment">/********************  Bits definition for RTC_BKP7R register  ****************/</span>
<a name="l05540"></a>05540 <span class="preprocessor">#define RTC_BKP7R                            ((uint32_t)0xFFFFFFFF)</span>
<a name="l05541"></a>05541 <span class="preprocessor"></span>
<a name="l05542"></a>05542 <span class="comment">/********************  Bits definition for RTC_BKP8R register  ****************/</span>
<a name="l05543"></a>05543 <span class="preprocessor">#define RTC_BKP8R                            ((uint32_t)0xFFFFFFFF)</span>
<a name="l05544"></a>05544 <span class="preprocessor"></span>
<a name="l05545"></a>05545 <span class="comment">/********************  Bits definition for RTC_BKP9R register  ****************/</span>
<a name="l05546"></a>05546 <span class="preprocessor">#define RTC_BKP9R                            ((uint32_t)0xFFFFFFFF)</span>
<a name="l05547"></a>05547 <span class="preprocessor"></span>
<a name="l05548"></a>05548 <span class="comment">/********************  Bits definition for RTC_BKP10R register  ***************/</span>
<a name="l05549"></a>05549 <span class="preprocessor">#define RTC_BKP10R                           ((uint32_t)0xFFFFFFFF)</span>
<a name="l05550"></a>05550 <span class="preprocessor"></span>
<a name="l05551"></a>05551 <span class="comment">/********************  Bits definition for RTC_BKP11R register  ***************/</span>
<a name="l05552"></a>05552 <span class="preprocessor">#define RTC_BKP11R                           ((uint32_t)0xFFFFFFFF)</span>
<a name="l05553"></a>05553 <span class="preprocessor"></span>
<a name="l05554"></a>05554 <span class="comment">/********************  Bits definition for RTC_BKP12R register  ***************/</span>
<a name="l05555"></a>05555 <span class="preprocessor">#define RTC_BKP12R                           ((uint32_t)0xFFFFFFFF)</span>
<a name="l05556"></a>05556 <span class="preprocessor"></span>
<a name="l05557"></a>05557 <span class="comment">/********************  Bits definition for RTC_BKP13R register  ***************/</span>
<a name="l05558"></a>05558 <span class="preprocessor">#define RTC_BKP13R                           ((uint32_t)0xFFFFFFFF)</span>
<a name="l05559"></a>05559 <span class="preprocessor"></span>
<a name="l05560"></a>05560 <span class="comment">/********************  Bits definition for RTC_BKP14R register  ***************/</span>
<a name="l05561"></a>05561 <span class="preprocessor">#define RTC_BKP14R                           ((uint32_t)0xFFFFFFFF)</span>
<a name="l05562"></a>05562 <span class="preprocessor"></span>
<a name="l05563"></a>05563 <span class="comment">/********************  Bits definition for RTC_BKP15R register  ***************/</span>
<a name="l05564"></a>05564 <span class="preprocessor">#define RTC_BKP15R                           ((uint32_t)0xFFFFFFFF)</span>
<a name="l05565"></a>05565 <span class="preprocessor"></span>
<a name="l05566"></a>05566 <span class="comment">/********************  Bits definition for RTC_BKP16R register  ***************/</span>
<a name="l05567"></a>05567 <span class="preprocessor">#define RTC_BKP16R                           ((uint32_t)0xFFFFFFFF)</span>
<a name="l05568"></a>05568 <span class="preprocessor"></span>
<a name="l05569"></a>05569 <span class="comment">/********************  Bits definition for RTC_BKP17R register  ***************/</span>
<a name="l05570"></a>05570 <span class="preprocessor">#define RTC_BKP17R                           ((uint32_t)0xFFFFFFFF)</span>
<a name="l05571"></a>05571 <span class="preprocessor"></span>
<a name="l05572"></a>05572 <span class="comment">/********************  Bits definition for RTC_BKP18R register  ***************/</span>
<a name="l05573"></a>05573 <span class="preprocessor">#define RTC_BKP18R                           ((uint32_t)0xFFFFFFFF)</span>
<a name="l05574"></a>05574 <span class="preprocessor"></span>
<a name="l05575"></a>05575 <span class="comment">/********************  Bits definition for RTC_BKP19R register  ***************/</span>
<a name="l05576"></a>05576 <span class="preprocessor">#define RTC_BKP19R                           ((uint32_t)0xFFFFFFFF)</span>
<a name="l05577"></a>05577 <span class="preprocessor"></span>
<a name="l05578"></a>05578 <span class="comment">/******************************************************************************/</span>
<a name="l05579"></a>05579 <span class="comment">/*                                                                            */</span>
<a name="l05580"></a>05580 <span class="comment">/*                          SD host Interface                                 */</span>
<a name="l05581"></a>05581 <span class="comment">/*                                                                            */</span>
<a name="l05582"></a>05582 <span class="comment">/******************************************************************************/</span>
<a name="l05583"></a>05583 <span class="comment">/******************  Bit definition for SDIO_POWER register  ******************/</span>
<a name="l05584"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaf125c56eeb40163b617c9fb6329da67f">05584</a> <span class="preprocessor">#define  SDIO_POWER_PWRCTRL                  ((uint8_t)0x03)               </span>
<a name="l05585"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaa82b7689b02f54318d3f629d70b85098">05585</a> <span class="preprocessor">#define  SDIO_POWER_PWRCTRL_0                ((uint8_t)0x01)               </span>
<a name="l05586"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gadd149efb1d6062f37165ac01268a875e">05586</a> <span class="preprocessor">#define  SDIO_POWER_PWRCTRL_1                ((uint8_t)0x02)               </span>
<a name="l05588"></a>05588 <span class="preprocessor"></span><span class="comment">/******************  Bit definition for SDIO_CLKCR register  ******************/</span>
<a name="l05589"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga316271d0147b22c6267fc563d4c24424">05589</a> <span class="preprocessor">#define  SDIO_CLKCR_CLKDIV                   ((uint16_t)0x00FF)            </span>
<a name="l05590"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaf27847573683f91dbfe387a2571b514f">05590</a> <span class="preprocessor">#define  SDIO_CLKCR_CLKEN                    ((uint16_t)0x0100)            </span>
<a name="l05591"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gafbb618f32aef2970fd8b8b285f7b4118">05591</a> <span class="preprocessor">#define  SDIO_CLKCR_PWRSAV                   ((uint16_t)0x0200)            </span>
<a name="l05592"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga1f362c1d228156c50639d79b9be99c9b">05592</a> <span class="preprocessor">#define  SDIO_CLKCR_BYPASS                   ((uint16_t)0x0400)            </span>
<a name="l05594"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gae9d57d7917c39bdc5309506e8c28b7d7">05594</a> <span class="preprocessor">#define  SDIO_CLKCR_WIDBUS                   ((uint16_t)0x1800)            </span>
<a name="l05595"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gab532dbf366c3fb731488017b0a794151">05595</a> <span class="preprocessor">#define  SDIO_CLKCR_WIDBUS_0                 ((uint16_t)0x0800)            </span>
<a name="l05596"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga49f3e7998bca487f5354ef6f8dffbb21">05596</a> <span class="preprocessor">#define  SDIO_CLKCR_WIDBUS_1                 ((uint16_t)0x1000)            </span>
<a name="l05598"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gad124bd76f6543497c90372e182ec48a2">05598</a> <span class="preprocessor">#define  SDIO_CLKCR_NEGEDGE                  ((uint16_t)0x2000)            </span>
<a name="l05599"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga693d7b533dd5a5a668bc13b4365b18dc">05599</a> <span class="preprocessor">#define  SDIO_CLKCR_HWFC_EN                  ((uint16_t)0x4000)            </span>
<a name="l05601"></a>05601 <span class="preprocessor"></span><span class="comment">/*******************  Bit definition for SDIO_ARG register  *******************/</span>
<a name="l05602"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga2d917a4fdc7442e270c2c727df78b819">05602</a> <span class="preprocessor">#define  SDIO_ARG_CMDARG                     ((uint32_t)0xFFFFFFFF)            </span>
<a name="l05604"></a>05604 <span class="preprocessor"></span><span class="comment">/*******************  Bit definition for SDIO_CMD register  *******************/</span>
<a name="l05605"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaf91b593b5681a68db5ff9fd11600c9c8">05605</a> <span class="preprocessor">#define  SDIO_CMD_CMDINDEX                   ((uint16_t)0x003F)            </span>
<a name="l05607"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga5d617f0e08d697c3b263e6a79f417d0f">05607</a> <span class="preprocessor">#define  SDIO_CMD_WAITRESP                   ((uint16_t)0x00C0)            </span>
<a name="l05608"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gae5797a389fecf611dccd483658b822fa">05608</a> <span class="preprocessor">#define  SDIO_CMD_WAITRESP_0                 ((uint16_t)0x0040)            </span>
<a name="l05609"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga8f5457b48feda0056466e5c380c44373">05609</a> <span class="preprocessor">#define  SDIO_CMD_WAITRESP_1                 ((uint16_t)0x0080)            </span>
<a name="l05611"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga4b037f34e297f38d56b14d46d008ef58">05611</a> <span class="preprocessor">#define  SDIO_CMD_WAITINT                    ((uint16_t)0x0100)            </span>
<a name="l05612"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaf4118c9200bae6732764f6c87a0962a9">05612</a> <span class="preprocessor">#define  SDIO_CMD_WAITPEND                   ((uint16_t)0x0200)            </span>
<a name="l05613"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga982f3fd09ce7e31709e0628b1fae86b8">05613</a> <span class="preprocessor">#define  SDIO_CMD_CPSMEN                     ((uint16_t)0x0400)            </span>
<a name="l05614"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gad560080c3e7ab5aeafe151dafcc64368">05614</a> <span class="preprocessor">#define  SDIO_CMD_SDIOSUSPEND                ((uint16_t)0x0800)            </span>
<a name="l05615"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga905b78ecf464857e6501ef5fd5e6ef1b">05615</a> <span class="preprocessor">#define  SDIO_CMD_ENCMDCOMPL                 ((uint16_t)0x1000)            </span>
<a name="l05616"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga3a9d5b2366ec7ca38db9d6d9f0f63f81">05616</a> <span class="preprocessor">#define  SDIO_CMD_NIEN                       ((uint16_t)0x2000)            </span>
<a name="l05617"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga87422225274de986e7abe6b2a91a79c5">05617</a> <span class="preprocessor">#define  SDIO_CMD_CEATACMD                   ((uint16_t)0x4000)            </span>
<a name="l05619"></a>05619 <span class="preprocessor"></span><span class="comment">/*****************  Bit definition for SDIO_RESPCMD register  *****************/</span>
<a name="l05620"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga27f9a6cbfd364bbb050b526ebc01d2d7">05620</a> <span class="preprocessor">#define  SDIO_RESPCMD_RESPCMD                ((uint8_t)0x3F)               </span>
<a name="l05622"></a>05622 <span class="preprocessor"></span><span class="comment">/******************  Bit definition for SDIO_RESP0 register  ******************/</span>
<a name="l05623"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga56a55231f7a91cfd2cefaca0f6135cbc">05623</a> <span class="preprocessor">#define  SDIO_RESP0_CARDSTATUS0              ((uint32_t)0xFFFFFFFF)        </span>
<a name="l05625"></a>05625 <span class="preprocessor"></span><span class="comment">/******************  Bit definition for SDIO_RESP1 register  ******************/</span>
<a name="l05626"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga1d20abddfc99835a2954eda5899f6db1">05626</a> <span class="preprocessor">#define  SDIO_RESP1_CARDSTATUS1              ((uint32_t)0xFFFFFFFF)        </span>
<a name="l05628"></a>05628 <span class="preprocessor"></span><span class="comment">/******************  Bit definition for SDIO_RESP2 register  ******************/</span>
<a name="l05629"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga31a482ff36bde1df56ab603c864c4066">05629</a> <span class="preprocessor">#define  SDIO_RESP2_CARDSTATUS2              ((uint32_t)0xFFFFFFFF)        </span>
<a name="l05631"></a>05631 <span class="preprocessor"></span><span class="comment">/******************  Bit definition for SDIO_RESP3 register  ******************/</span>
<a name="l05632"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga1075c96b5818b0500d5cce231ace89cf">05632</a> <span class="preprocessor">#define  SDIO_RESP3_CARDSTATUS3              ((uint32_t)0xFFFFFFFF)        </span>
<a name="l05634"></a>05634 <span class="preprocessor"></span><span class="comment">/******************  Bit definition for SDIO_RESP4 register  ******************/</span>
<a name="l05635"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga407ab1e46a80426602ab36e86457da26">05635</a> <span class="preprocessor">#define  SDIO_RESP4_CARDSTATUS4              ((uint32_t)0xFFFFFFFF)        </span>
<a name="l05637"></a>05637 <span class="preprocessor"></span><span class="comment">/******************  Bit definition for SDIO_DTIMER register  *****************/</span>
<a name="l05638"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga27e45eea9ce17b7251f10ea763180690">05638</a> <span class="preprocessor">#define  SDIO_DTIMER_DATATIME                ((uint32_t)0xFFFFFFFF)        </span>
<a name="l05640"></a>05640 <span class="preprocessor"></span><span class="comment">/******************  Bit definition for SDIO_DLEN register  *******************/</span>
<a name="l05641"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga4d3b07bca9aec8ef5456ba9b73f13adb">05641</a> <span class="preprocessor">#define  SDIO_DLEN_DATALENGTH                ((uint32_t)0x01FFFFFF)        </span>
<a name="l05643"></a>05643 <span class="preprocessor"></span><span class="comment">/******************  Bit definition for SDIO_DCTRL register  ******************/</span>
<a name="l05644"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaa03ff8fb9ff70e0a623a5c1f7aa2bc9a">05644</a> <span class="preprocessor">#define  SDIO_DCTRL_DTEN                     ((uint16_t)0x0001)            </span>
<a name="l05645"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga801fe27f7175a308d56776db19776c93">05645</a> <span class="preprocessor">#define  SDIO_DCTRL_DTDIR                    ((uint16_t)0x0002)            </span>
<a name="l05646"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaa90cd50ae364b992ca8ccab319eb5513">05646</a> <span class="preprocessor">#define  SDIO_DCTRL_DTMODE                   ((uint16_t)0x0004)            </span>
<a name="l05647"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga03a2148910ae02dde7e4cd63e0f5e008">05647</a> <span class="preprocessor">#define  SDIO_DCTRL_DMAEN                    ((uint16_t)0x0008)            </span>
<a name="l05649"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga948072d8a6db53d0c377944523a4b15a">05649</a> <span class="preprocessor">#define  SDIO_DCTRL_DBLOCKSIZE               ((uint16_t)0x00F0)            </span>
<a name="l05650"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga51e2cb99cf325bb32c8910204b1507db">05650</a> <span class="preprocessor">#define  SDIO_DCTRL_DBLOCKSIZE_0             ((uint16_t)0x0010)            </span>
<a name="l05651"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga0add3ad2b72a21e7f8d48da3ea0b3d0f">05651</a> <span class="preprocessor">#define  SDIO_DCTRL_DBLOCKSIZE_1             ((uint16_t)0x0020)            </span>
<a name="l05652"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga93825036eceb86872e2ca179c63163ec">05652</a> <span class="preprocessor">#define  SDIO_DCTRL_DBLOCKSIZE_2             ((uint16_t)0x0040)            </span>
<a name="l05653"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gac2025aa63b595bfccc747b99caec8799">05653</a> <span class="preprocessor">#define  SDIO_DCTRL_DBLOCKSIZE_3             ((uint16_t)0x0080)            </span>
<a name="l05655"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gafe9600da3e751118d49ea14ce44e91b9">05655</a> <span class="preprocessor">#define  SDIO_DCTRL_RWSTART                  ((uint16_t)0x0100)            </span>
<a name="l05656"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga3f1b5b6a32ce712fbb3767090b1b045e">05656</a> <span class="preprocessor">#define  SDIO_DCTRL_RWSTOP                   ((uint16_t)0x0200)            </span>
<a name="l05657"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga4bf721a25f656b3de6fa0b0fe32edb6a">05657</a> <span class="preprocessor">#define  SDIO_DCTRL_RWMOD                    ((uint16_t)0x0400)            </span>
<a name="l05658"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaa16b4c4037cf974162a591aea753fc21">05658</a> <span class="preprocessor">#define  SDIO_DCTRL_SDIOEN                   ((uint16_t)0x0800)            </span>
<a name="l05660"></a>05660 <span class="preprocessor"></span><span class="comment">/******************  Bit definition for SDIO_DCOUNT register  *****************/</span>
<a name="l05661"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga2f8ab9dfe9d4f809b61fa2b7826adbde">05661</a> <span class="preprocessor">#define  SDIO_DCOUNT_DATACOUNT               ((uint32_t)0x01FFFFFF)        </span>
<a name="l05663"></a>05663 <span class="preprocessor"></span><span class="comment">/******************  Bit definition for SDIO_STA register  ********************/</span>
<a name="l05664"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gad6dbe59c4bdd8b9a12b092cf84a9daef">05664</a> <span class="preprocessor">#define  SDIO_STA_CCRCFAIL                   ((uint32_t)0x00000001)        </span>
<a name="l05665"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga554d1f9986bf5c715dd6f27a6493ce31">05665</a> <span class="preprocessor">#define  SDIO_STA_DCRCFAIL                   ((uint32_t)0x00000002)        </span>
<a name="l05666"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gae72c4f34bb3ccffeef1d7cdcb7415bdc">05666</a> <span class="preprocessor">#define  SDIO_STA_CTIMEOUT                   ((uint32_t)0x00000004)        </span>
<a name="l05667"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga8a2cad7ef3406a46ddba51f7ab5df94b">05667</a> <span class="preprocessor">#define  SDIO_STA_DTIMEOUT                   ((uint32_t)0x00000008)        </span>
<a name="l05668"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga4b9dcdb8b90d8266eb0c5a2be81238aa">05668</a> <span class="preprocessor">#define  SDIO_STA_TXUNDERR                   ((uint32_t)0x00000010)        </span>
<a name="l05669"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gad4b91289c9f6b773f928706ae8a5ddfc">05669</a> <span class="preprocessor">#define  SDIO_STA_RXOVERR                    ((uint32_t)0x00000020)        </span>
<a name="l05670"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga096f11117736a2252f1cd5c4cccdc6e6">05670</a> <span class="preprocessor">#define  SDIO_STA_CMDREND                    ((uint32_t)0x00000040)        </span>
<a name="l05671"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaa550641dc6aa942e1b524ad0e557a284">05671</a> <span class="preprocessor">#define  SDIO_STA_CMDSENT                    ((uint32_t)0x00000080)        </span>
<a name="l05672"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gafe7e354a903b957943cf5b6bed4cdf6b">05672</a> <span class="preprocessor">#define  SDIO_STA_DATAEND                    ((uint32_t)0x00000100)        </span>
<a name="l05673"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga7a9ef8e72604e9997da23601a2dd84a4">05673</a> <span class="preprocessor">#define  SDIO_STA_STBITERR                   ((uint32_t)0x00000200)        </span>
<a name="l05674"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga2fabf2c02cba6d4de1e90d8d1dc9793c">05674</a> <span class="preprocessor">#define  SDIO_STA_DBCKEND                    ((uint32_t)0x00000400)        </span>
<a name="l05675"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga99ccdac7a223635ee5b38a4bae8f30cc">05675</a> <span class="preprocessor">#define  SDIO_STA_CMDACT                     ((uint32_t)0x00000800)        </span>
<a name="l05676"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga908feb4957f48390bc2fc0bde47ac784">05676</a> <span class="preprocessor">#define  SDIO_STA_TXACT                      ((uint32_t)0x00001000)        </span>
<a name="l05677"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaad2f52b50765fa449dcfabc39b099796">05677</a> <span class="preprocessor">#define  SDIO_STA_RXACT                      ((uint32_t)0x00002000)        </span>
<a name="l05678"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga62b9e38be5956dde69049154facc62fd">05678</a> <span class="preprocessor">#define  SDIO_STA_TXFIFOHE                   ((uint32_t)0x00004000)        </span>
<a name="l05679"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga7916c47ee972376a0eaee584133ca36d">05679</a> <span class="preprocessor">#define  SDIO_STA_RXFIFOHF                   ((uint32_t)0x00008000)        </span>
<a name="l05680"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gae1497b46f9a906001dabb7d7604f6c05">05680</a> <span class="preprocessor">#define  SDIO_STA_TXFIFOF                    ((uint32_t)0x00010000)        </span>
<a name="l05681"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga85f46f873ca5fe91a1e8206d157b9446">05681</a> <span class="preprocessor">#define  SDIO_STA_RXFIFOF                    ((uint32_t)0x00020000)        </span>
<a name="l05682"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga4624f95c5224c631f99571b5454acd86">05682</a> <span class="preprocessor">#define  SDIO_STA_TXFIFOE                    ((uint32_t)0x00040000)        </span>
<a name="l05683"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga44bf9f7321d65a3effd2df469a58a464">05683</a> <span class="preprocessor">#define  SDIO_STA_RXFIFOE                    ((uint32_t)0x00080000)        </span>
<a name="l05684"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga19b374518e813f7a1ac4aec3b24b7517">05684</a> <span class="preprocessor">#define  SDIO_STA_TXDAVL                     ((uint32_t)0x00100000)        </span>
<a name="l05685"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gadcad9b8c0e3ccba1aa389d7713db6803">05685</a> <span class="preprocessor">#define  SDIO_STA_RXDAVL                     ((uint32_t)0x00200000)        </span>
<a name="l05686"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga5df3c10c37285faedb2d853aea4e63dc">05686</a> <span class="preprocessor">#define  SDIO_STA_SDIOIT                     ((uint32_t)0x00400000)        </span>
<a name="l05687"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga5d8ef3b4157374fd2b5fc8ed12b77a0c">05687</a> <span class="preprocessor">#define  SDIO_STA_CEATAEND                   ((uint32_t)0x00800000)        </span>
<a name="l05689"></a>05689 <span class="preprocessor"></span><span class="comment">/*******************  Bit definition for SDIO_ICR register  *******************/</span>
<a name="l05690"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga44708c45f675cf065f1c7fc9311d6e43">05690</a> <span class="preprocessor">#define  SDIO_ICR_CCRCFAILC                  ((uint32_t)0x00000001)        </span>
<a name="l05691"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga2cb6cde5f88a5d2b635a830dd401c4e0">05691</a> <span class="preprocessor">#define  SDIO_ICR_DCRCFAILC                  ((uint32_t)0x00000002)        </span>
<a name="l05692"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gac4d128bee8a97ae9971d42f844d2e297">05692</a> <span class="preprocessor">#define  SDIO_ICR_CTIMEOUTC                  ((uint32_t)0x00000004)        </span>
<a name="l05693"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gadcb64d3d07a5841ee9f18ff6bc75350b">05693</a> <span class="preprocessor">#define  SDIO_ICR_DTIMEOUTC                  ((uint32_t)0x00000008)        </span>
<a name="l05694"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga9628d77973f35d628924172831b029f8">05694</a> <span class="preprocessor">#define  SDIO_ICR_TXUNDERRC                  ((uint32_t)0x00000010)        </span>
<a name="l05695"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga2513d040c7695b152b0b423ad6f5c81e">05695</a> <span class="preprocessor">#define  SDIO_ICR_RXOVERRC                   ((uint32_t)0x00000020)        </span>
<a name="l05696"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga8fb5c67aef48d5ee27b60107d938a58f">05696</a> <span class="preprocessor">#define  SDIO_ICR_CMDRENDC                   ((uint32_t)0x00000040)        </span>
<a name="l05697"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaa27fe45ef7461caf704186630b26a196">05697</a> <span class="preprocessor">#define  SDIO_ICR_CMDSENTC                   ((uint32_t)0x00000080)        </span>
<a name="l05698"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga527e1f9cd295845d5be9975cf26bae7e">05698</a> <span class="preprocessor">#define  SDIO_ICR_DATAENDC                   ((uint32_t)0x00000100)        </span>
<a name="l05699"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gae614b5ab8a8aecbc3c1ce74645cdc28c">05699</a> <span class="preprocessor">#define  SDIO_ICR_STBITERRC                  ((uint32_t)0x00000200)        </span>
<a name="l05700"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gadc5518c07e39dc1f91603737d1a7180b">05700</a> <span class="preprocessor">#define  SDIO_ICR_DBCKENDC                   ((uint32_t)0x00000400)        </span>
<a name="l05701"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga2990db729fb017dfd659dc6cf8823761">05701</a> <span class="preprocessor">#define  SDIO_ICR_SDIOITC                    ((uint32_t)0x00400000)        </span>
<a name="l05702"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga6f1cebd40fd1eafb59635b284c5a3f34">05702</a> <span class="preprocessor">#define  SDIO_ICR_CEATAENDC                  ((uint32_t)0x00800000)        </span>
<a name="l05704"></a>05704 <span class="preprocessor"></span><span class="comment">/******************  Bit definition for SDIO_MASK register  *******************/</span>
<a name="l05705"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga5e24d12a6c9af91337cb391d3ba698f3">05705</a> <span class="preprocessor">#define  SDIO_MASK_CCRCFAILIE                ((uint32_t)0x00000001)        </span>
<a name="l05706"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga5e2e106a1f7792f054c6cc1f60906a09">05706</a> <span class="preprocessor">#define  SDIO_MASK_DCRCFAILIE                ((uint32_t)0x00000002)        </span>
<a name="l05707"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga23f5a8c06e289522af0a679b08bdb014">05707</a> <span class="preprocessor">#define  SDIO_MASK_CTIMEOUTIE                ((uint32_t)0x00000004)        </span>
<a name="l05708"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga7b4cc63338fe72abd76e5b399c47379b">05708</a> <span class="preprocessor">#define  SDIO_MASK_DTIMEOUTIE                ((uint32_t)0x00000008)        </span>
<a name="l05709"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga1e02e525dc6ca1bb294b174e7391753d">05709</a> <span class="preprocessor">#define  SDIO_MASK_TXUNDERRIE                ((uint32_t)0x00000010)        </span>
<a name="l05710"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga39f494cf2a6af6ced9eaeac751ea81e4">05710</a> <span class="preprocessor">#define  SDIO_MASK_RXOVERRIE                 ((uint32_t)0x00000020)        </span>
<a name="l05711"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga5fdedfc60a2019ff5f64533fcdd0c3f1">05711</a> <span class="preprocessor">#define  SDIO_MASK_CMDRENDIE                 ((uint32_t)0x00000040)        </span>
<a name="l05712"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga0d541aea02974c03bd8a8426125c35ff">05712</a> <span class="preprocessor">#define  SDIO_MASK_CMDSENTIE                 ((uint32_t)0x00000080)        </span>
<a name="l05713"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gae6398bd3e8312eea3b986ab59b80b466">05713</a> <span class="preprocessor">#define  SDIO_MASK_DATAENDIE                 ((uint32_t)0x00000100)        </span>
<a name="l05714"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga4194bed51eb4a951a58a5d4062ba978f">05714</a> <span class="preprocessor">#define  SDIO_MASK_STBITERRIE                ((uint32_t)0x00000200)        </span>
<a name="l05715"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga947e5da36c9eeca0b48f3356067dff00">05715</a> <span class="preprocessor">#define  SDIO_MASK_DBCKENDIE                 ((uint32_t)0x00000400)        </span>
<a name="l05716"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gad63b504f02ea0b1e5ec48962799fde88">05716</a> <span class="preprocessor">#define  SDIO_MASK_CMDACTIE                  ((uint32_t)0x00000800)        </span>
<a name="l05717"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga9bbfbc3f69ab77171eb1a0058783b1e0">05717</a> <span class="preprocessor">#define  SDIO_MASK_TXACTIE                   ((uint32_t)0x00001000)        </span>
<a name="l05718"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga9768c39a5d9d3c5519eb522c62a75eae">05718</a> <span class="preprocessor">#define  SDIO_MASK_RXACTIE                   ((uint32_t)0x00002000)        </span>
<a name="l05719"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gad9cf28de8489fee023ea353df0e13fa7">05719</a> <span class="preprocessor">#define  SDIO_MASK_TXFIFOHEIE                ((uint32_t)0x00004000)        </span>
<a name="l05720"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga04d50028fc671494508aecb04e727102">05720</a> <span class="preprocessor">#define  SDIO_MASK_RXFIFOHFIE                ((uint32_t)0x00008000)        </span>
<a name="l05721"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga03a602b975ce16ef03083947aded0172">05721</a> <span class="preprocessor">#define  SDIO_MASK_TXFIFOFIE                 ((uint32_t)0x00010000)        </span>
<a name="l05722"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaf18c4bdf8fa4ee85596a89de00158fbb">05722</a> <span class="preprocessor">#define  SDIO_MASK_RXFIFOFIE                 ((uint32_t)0x00020000)        </span>
<a name="l05723"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga11e1d67150fad62dc1ca7783f3a19372">05723</a> <span class="preprocessor">#define  SDIO_MASK_TXFIFOEIE                 ((uint32_t)0x00040000)        </span>
<a name="l05724"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gadbc23fa1c153a9e5216baeef7922e412">05724</a> <span class="preprocessor">#define  SDIO_MASK_RXFIFOEIE                 ((uint32_t)0x00080000)        </span>
<a name="l05725"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga9a1988093a6df087ebb8ff41a51962da">05725</a> <span class="preprocessor">#define  SDIO_MASK_TXDAVLIE                  ((uint32_t)0x00100000)        </span>
<a name="l05726"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gafa9da7d15902e6f94b79968a07250696">05726</a> <span class="preprocessor">#define  SDIO_MASK_RXDAVLIE                  ((uint32_t)0x00200000)        </span>
<a name="l05727"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gad73b7c7d480d2d71613995cfecc59138">05727</a> <span class="preprocessor">#define  SDIO_MASK_SDIOITIE                  ((uint32_t)0x00400000)        </span>
<a name="l05728"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga0a19dd3039888ebdc40b2406be400749">05728</a> <span class="preprocessor">#define  SDIO_MASK_CEATAENDIE                ((uint32_t)0x00800000)        </span>
<a name="l05730"></a>05730 <span class="preprocessor"></span><span class="comment">/*****************  Bit definition for SDIO_FIFOCNT register  *****************/</span>
<a name="l05731"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaa45f5e0a2be89267f79cad57f456f0a2">05731</a> <span class="preprocessor">#define  SDIO_FIFOCNT_FIFOCOUNT              ((uint32_t)0x00FFFFFF)        </span>
<a name="l05733"></a>05733 <span class="preprocessor"></span><span class="comment">/******************  Bit definition for SDIO_FIFO register  *******************/</span>
<a name="l05734"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga5fc0d1e12c55398e2881fe917672da25">05734</a> <span class="preprocessor">#define  SDIO_FIFO_FIFODATA                  ((uint32_t)0xFFFFFFFF)        </span>
<a name="l05736"></a>05736 <span class="preprocessor"></span><span class="comment">/******************************************************************************/</span>
<a name="l05737"></a>05737 <span class="comment">/*                                                                            */</span>
<a name="l05738"></a>05738 <span class="comment">/*                        Serial Peripheral Interface                         */</span>
<a name="l05739"></a>05739 <span class="comment">/*                                                                            */</span>
<a name="l05740"></a>05740 <span class="comment">/******************************************************************************/</span>
<a name="l05741"></a>05741 <span class="comment">/*******************  Bit definition for SPI_CR1 register  ********************/</span>
<a name="l05742"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga97602d8ded14bbd2c1deadaf308755a3">05742</a> <span class="preprocessor">#define  SPI_CR1_CPHA                        ((uint16_t)0x0001)            </span>
<a name="l05743"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga2616a10f5118cdc68fbdf0582481e124">05743</a> <span class="preprocessor">#define  SPI_CR1_CPOL                        ((uint16_t)0x0002)            </span>
<a name="l05744"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga5b3b6ae107fc37bf18e14506298d7a55">05744</a> <span class="preprocessor">#define  SPI_CR1_MSTR                        ((uint16_t)0x0004)            </span>
<a name="l05746"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga261af22667719a32b3ce566c1e261936">05746</a> <span class="preprocessor">#define  SPI_CR1_BR                          ((uint16_t)0x0038)            </span>
<a name="l05747"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaa364b123cf797044094cc229330ce321">05747</a> <span class="preprocessor">#define  SPI_CR1_BR_0                        ((uint16_t)0x0008)            </span>
<a name="l05748"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga45e93d18c8966964ed1926d5ca87ef46">05748</a> <span class="preprocessor">#define  SPI_CR1_BR_1                        ((uint16_t)0x0010)            </span>
<a name="l05749"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga28b823d564e9d90150bcc6744b4ed622">05749</a> <span class="preprocessor">#define  SPI_CR1_BR_2                        ((uint16_t)0x0020)            </span>
<a name="l05751"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gac5a646d978d3b98eb7c6a5d95d75c3f9">05751</a> <span class="preprocessor">#define  SPI_CR1_SPE                         ((uint16_t)0x0040)            </span>
<a name="l05752"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gab929e9d5ddbb66f229c501ab18d0e6e8">05752</a> <span class="preprocessor">#define  SPI_CR1_LSBFIRST                    ((uint16_t)0x0080)            </span>
<a name="l05753"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga5f154374b58c0234f82ea326cb303a1e">05753</a> <span class="preprocessor">#define  SPI_CR1_SSI                         ((uint16_t)0x0100)            </span>
<a name="l05754"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga0e236047e05106cf1ba7929766311382">05754</a> <span class="preprocessor">#define  SPI_CR1_SSM                         ((uint16_t)0x0200)            </span>
<a name="l05755"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga9ffecf774b84a8cdc11ab1f931791883">05755</a> <span class="preprocessor">#define  SPI_CR1_RXONLY                      ((uint16_t)0x0400)            </span>
<a name="l05756"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga3ffabea0de695a19198d906bf6a1d9fd">05756</a> <span class="preprocessor">#define  SPI_CR1_DFF                         ((uint16_t)0x0800)            </span>
<a name="l05757"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga57072f13c2e54c12186ae8c5fdecb250">05757</a> <span class="preprocessor">#define  SPI_CR1_CRCNEXT                     ((uint16_t)0x1000)            </span>
<a name="l05758"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gac9339b7c6466f09ad26c26b3bb81c51b">05758</a> <span class="preprocessor">#define  SPI_CR1_CRCEN                       ((uint16_t)0x2000)            </span>
<a name="l05759"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga378953916b7701bd49f063c0366b703f">05759</a> <span class="preprocessor">#define  SPI_CR1_BIDIOE                      ((uint16_t)0x4000)            </span>
<a name="l05760"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga43608d3c2959fc9ca64398d61cbf484e">05760</a> <span class="preprocessor">#define  SPI_CR1_BIDIMODE                    ((uint16_t)0x8000)            </span>
<a name="l05762"></a>05762 <span class="preprocessor"></span><span class="comment">/*******************  Bit definition for SPI_CR2 register  ********************/</span>
<a name="l05763"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaf23c590d98279634af05550702a806da">05763</a> <span class="preprocessor">#define  SPI_CR2_RXDMAEN                     ((uint8_t)0x01)               </span>
<a name="l05764"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga3eee671793983a3bd669c9173b2ce210">05764</a> <span class="preprocessor">#define  SPI_CR2_TXDMAEN                     ((uint8_t)0x02)               </span>
<a name="l05765"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gae94612b95395eff626f5f3d7d28352dd">05765</a> <span class="preprocessor">#define  SPI_CR2_SSOE                        ((uint8_t)0x04)               </span>
<a name="l05766"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaf18705567de7ab52a62e5ef3ba27418b">05766</a> <span class="preprocessor">#define  SPI_CR2_ERRIE                       ((uint8_t)0x20)               </span>
<a name="l05767"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaa7d4c37fbbcced7f2a0421e6ffd103ea">05767</a> <span class="preprocessor">#define  SPI_CR2_RXNEIE                      ((uint8_t)0x40)               </span>
<a name="l05768"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga23f683a1252ccaf625cae1a978989b2c">05768</a> <span class="preprocessor">#define  SPI_CR2_TXEIE                       ((uint8_t)0x80)               </span>
<a name="l05770"></a>05770 <span class="preprocessor"></span><span class="comment">/********************  Bit definition for SPI_SR register  ********************/</span>
<a name="l05771"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga40e14de547aa06864abcd4b0422d8b48">05771</a> <span class="preprocessor">#define  SPI_SR_RXNE                         ((uint8_t)0x01)               </span>
<a name="l05772"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga5bd5d21816947fcb25ccae7d3bf8eb2c">05772</a> <span class="preprocessor">#define  SPI_SR_TXE                          ((uint8_t)0x02)               </span>
<a name="l05773"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga81bd052f0b2e819ddd6bb16c2292a2de">05773</a> <span class="preprocessor">#define  SPI_SR_CHSIDE                       ((uint8_t)0x04)               </span>
<a name="l05774"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga13d3292e963499c0e9a36869909229e6">05774</a> <span class="preprocessor">#define  SPI_SR_UDR                          ((uint8_t)0x08)               </span>
<a name="l05775"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga69e543fa9584fd636032a3ee735f750b">05775</a> <span class="preprocessor">#define  SPI_SR_CRCERR                       ((uint8_t)0x10)               </span>
<a name="l05776"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gabaa043349833dc7b8138969c64f63adf">05776</a> <span class="preprocessor">#define  SPI_SR_MODF                         ((uint8_t)0x20)               </span>
<a name="l05777"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaa8d902302c5eb81ce4a57029de281232">05777</a> <span class="preprocessor">#define  SPI_SR_OVR                          ((uint8_t)0x40)               </span>
<a name="l05778"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaa3498df67729ae048dc5f315ef7c16bf">05778</a> <span class="preprocessor">#define  SPI_SR_BSY                          ((uint8_t)0x80)               </span>
<a name="l05780"></a>05780 <span class="preprocessor"></span><span class="comment">/********************  Bit definition for SPI_DR register  ********************/</span>
<a name="l05781"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaa4da7d7f05a28d1aaa52ec557e55e1ad">05781</a> <span class="preprocessor">#define  SPI_DR_DR                           ((uint16_t)0xFFFF)            </span>
<a name="l05783"></a>05783 <span class="preprocessor"></span><span class="comment">/*******************  Bit definition for SPI_CRCPR register  ******************/</span>
<a name="l05784"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gae968658ab837800723eafcc21af10247">05784</a> <span class="preprocessor">#define  SPI_CRCPR_CRCPOLY                   ((uint16_t)0xFFFF)            </span>
<a name="l05786"></a>05786 <span class="preprocessor"></span><span class="comment">/******************  Bit definition for SPI_RXCRCR register  ******************/</span>
<a name="l05787"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga3a01a578c2c7bb4e587a8f1610843181">05787</a> <span class="preprocessor">#define  SPI_RXCRCR_RXCRC                    ((uint16_t)0xFFFF)            </span>
<a name="l05789"></a>05789 <span class="preprocessor"></span><span class="comment">/******************  Bit definition for SPI_TXCRCR register  ******************/</span>
<a name="l05790"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga1c69dc721e89e40056999b64572dff09">05790</a> <span class="preprocessor">#define  SPI_TXCRCR_TXCRC                    ((uint16_t)0xFFFF)            </span>
<a name="l05792"></a>05792 <span class="preprocessor"></span><span class="comment">/******************  Bit definition for SPI_I2SCFGR register  *****************/</span>
<a name="l05793"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga9c362b3d703698a7891f032f6b29056f">05793</a> <span class="preprocessor">#define  SPI_I2SCFGR_CHLEN                   ((uint16_t)0x0001)            </span>
<a name="l05795"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gacc12f9d2003ab169a3f68e9d809f84ae">05795</a> <span class="preprocessor">#define  SPI_I2SCFGR_DATLEN                  ((uint16_t)0x0006)            </span>
<a name="l05796"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaa20ad624085d2e533eea3662cb03d8fa">05796</a> <span class="preprocessor">#define  SPI_I2SCFGR_DATLEN_0                ((uint16_t)0x0002)            </span>
<a name="l05797"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gadf6e940d195fa1633cb1b23414f00412">05797</a> <span class="preprocessor">#define  SPI_I2SCFGR_DATLEN_1                ((uint16_t)0x0004)            </span>
<a name="l05799"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga5c5be1f1c8b4689643e04cd5034e7f5f">05799</a> <span class="preprocessor">#define  SPI_I2SCFGR_CKPOL                   ((uint16_t)0x0008)            </span>
<a name="l05801"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga7a822a80be3a51524b42491248f8031f">05801</a> <span class="preprocessor">#define  SPI_I2SCFGR_I2SSTD                  ((uint16_t)0x0030)            </span>
<a name="l05802"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gafeba0a45703463dfe05334364bdacbe8">05802</a> <span class="preprocessor">#define  SPI_I2SCFGR_I2SSTD_0                ((uint16_t)0x0010)            </span>
<a name="l05803"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga0142a3667f59bce9bae80d31e88a124a">05803</a> <span class="preprocessor">#define  SPI_I2SCFGR_I2SSTD_1                ((uint16_t)0x0020)            </span>
<a name="l05805"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga66a29efc32a31f903e89b7ddcd20857b">05805</a> <span class="preprocessor">#define  SPI_I2SCFGR_PCMSYNC                 ((uint16_t)0x0080)            </span>
<a name="l05807"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaf09fd11f6f97000266b30b015bf2cb68">05807</a> <span class="preprocessor">#define  SPI_I2SCFGR_I2SCFG                  ((uint16_t)0x0300)            </span>
<a name="l05808"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga421c94680ee8a2583419e2b0c89e995e">05808</a> <span class="preprocessor">#define  SPI_I2SCFGR_I2SCFG_0                ((uint16_t)0x0100)            </span>
<a name="l05809"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga80c398b9e79fcc61a497f9d7dd910352">05809</a> <span class="preprocessor">#define  SPI_I2SCFGR_I2SCFG_1                ((uint16_t)0x0200)            </span>
<a name="l05811"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga30d76c7552c91bbd5cbac70d9c56ebb3">05811</a> <span class="preprocessor">#define  SPI_I2SCFGR_I2SE                    ((uint16_t)0x0400)            </span>
<a name="l05812"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gae99763414b3c2f11fcfecb1f93eb6701">05812</a> <span class="preprocessor">#define  SPI_I2SCFGR_I2SMOD                  ((uint16_t)0x0800)            </span>
<a name="l05814"></a>05814 <span class="preprocessor"></span><span class="comment">/******************  Bit definition for SPI_I2SPR register  *******************/</span>
<a name="l05815"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga406ce88b2580a421f5b28bdbeb303543">05815</a> <span class="preprocessor">#define  SPI_I2SPR_I2SDIV                    ((uint16_t)0x00FF)            </span>
<a name="l05816"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga3d6d4136a5ae12f9bd5940324282355a">05816</a> <span class="preprocessor">#define  SPI_I2SPR_ODD                       ((uint16_t)0x0100)            </span>
<a name="l05817"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga25669c3686c0c577d2d371ac09200ff0">05817</a> <span class="preprocessor">#define  SPI_I2SPR_MCKOE                     ((uint16_t)0x0200)            </span>
<a name="l05819"></a>05819 <span class="preprocessor"></span><span class="comment">/******************************************************************************/</span>
<a name="l05820"></a>05820 <span class="comment">/*                                                                            */</span>
<a name="l05821"></a>05821 <span class="comment">/*                                 SYSCFG                                     */</span>
<a name="l05822"></a>05822 <span class="comment">/*                                                                            */</span>
<a name="l05823"></a>05823 <span class="comment">/******************************************************************************/</span>
<a name="l05824"></a>05824 <span class="comment">/******************  Bit definition for SYSCFG_MEMRMP register  ***************/</span>  
<a name="l05825"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga3c05039ec67573c00da29f58b914f258">05825</a> <span class="preprocessor">#define SYSCFG_MEMRMP_MEM_MODE          ((uint32_t)0x00000003) </span>
<a name="l05826"></a>05826 <span class="preprocessor">#define SYSCFG_MEMRMP_MEM_MODE_0        ((uint32_t)0x00000001)</span>
<a name="l05827"></a>05827 <span class="preprocessor"></span><span class="preprocessor">#define SYSCFG_MEMRMP_MEM_MODE_1        ((uint32_t)0x00000002)</span>
<a name="l05828"></a>05828 <span class="preprocessor"></span>
<a name="l05829"></a>05829 <span class="comment">/******************  Bit definition for SYSCFG_PMC register  ******************/</span>
<a name="l05830"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gae9d8ca35cdab213cb2400c49434de326">05830</a> <span class="preprocessor">#define SYSCFG_PMC_MII_RMII_SEL         ((uint32_t)0x00800000) </span>
<a name="l05831"></a>05831 <span class="preprocessor"></span><span class="comment">/* Old MII_RMII_SEL bit definition, maintained for legacy purpose */</span>
<a name="l05832"></a>05832 <span class="preprocessor">#define SYSCFG_PMC_MII_RMII             SYSCFG_PMC_MII_RMII_SEL</span>
<a name="l05833"></a>05833 <span class="preprocessor"></span>
<a name="l05834"></a>05834 <span class="comment">/*****************  Bit definition for SYSCFG_EXTICR1 register  ***************/</span>
<a name="l05835"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga75b70d07448c3037234bc2abb8e3d884">05835</a> <span class="preprocessor">#define SYSCFG_EXTICR1_EXTI0            ((uint16_t)0x000F) </span>
<a name="l05836"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga7fc84838c77f799cb7e57d6e97c6c16d">05836</a> <span class="preprocessor">#define SYSCFG_EXTICR1_EXTI1            ((uint16_t)0x00F0) </span>
<a name="l05837"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga6d0a0a6b8223777937d8c9012658d6cd">05837</a> <span class="preprocessor">#define SYSCFG_EXTICR1_EXTI2            ((uint16_t)0x0F00) </span>
<a name="l05838"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gac3bf2306f79ebb709da5ecf83e59ded4">05838</a> <span class="preprocessor">#define SYSCFG_EXTICR1_EXTI3            ((uint16_t)0xF000) </span>
<a name="l05842"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga6de6aa8e32ae5cd07fd69e42e7226bd1">05842</a> <span class="preprocessor">#define SYSCFG_EXTICR1_EXTI0_PA         ((uint16_t)0x0000) </span>
<a name="l05843"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaf43c9ef6b61e39655cbe969967c79a69">05843</a> <span class="preprocessor">#define SYSCFG_EXTICR1_EXTI0_PB         ((uint16_t)0x0001) </span>
<a name="l05844"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga861a4d7b48ffd93997267baaad12fd51">05844</a> <span class="preprocessor">#define SYSCFG_EXTICR1_EXTI0_PC         ((uint16_t)0x0002) </span>
<a name="l05845"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaf6439042c8cd14f99fe3813cff47c0ee">05845</a> <span class="preprocessor">#define SYSCFG_EXTICR1_EXTI0_PD         ((uint16_t)0x0003) </span>
<a name="l05846"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gacb087e2ded8ac927ee9e1fc0234bfdef">05846</a> <span class="preprocessor">#define SYSCFG_EXTICR1_EXTI0_PE         ((uint16_t)0x0004) </span>
<a name="l05847"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaa897f1ac8311e57339eaf7813239eaf4">05847</a> <span class="preprocessor">#define SYSCFG_EXTICR1_EXTI0_PF         ((uint16_t)0x0005) </span>
<a name="l05848"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga98b2d929e79e5cc2ee7961a75a0ab094">05848</a> <span class="preprocessor">#define SYSCFG_EXTICR1_EXTI0_PG         ((uint16_t)0x0006) </span>
<a name="l05849"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga766d0bf3501e207b0baa066cf756688f">05849</a> <span class="preprocessor">#define SYSCFG_EXTICR1_EXTI0_PH         ((uint16_t)0x0007) </span>
<a name="l05850"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gacfc4b69ff5f5d9b35bf01f26d6aa4e60">05850</a> <span class="preprocessor">#define SYSCFG_EXTICR1_EXTI0_PI         ((uint16_t)0x0008) </span>
<a name="l05854"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaf4b78c30e4ef4fa441582eb3c102865d">05854</a> <span class="preprocessor">#define SYSCFG_EXTICR1_EXTI1_PA         ((uint16_t)0x0000) </span>
<a name="l05855"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga19a11fce288d19546c76257483e0dcb6">05855</a> <span class="preprocessor">#define SYSCFG_EXTICR1_EXTI1_PB         ((uint16_t)0x0010) </span>
<a name="l05856"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gae45a8c814b13fa19f157364dc715c08a">05856</a> <span class="preprocessor">#define SYSCFG_EXTICR1_EXTI1_PC         ((uint16_t)0x0020) </span>
<a name="l05857"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga93cb136eaf357affc4a28a8d423cabbb">05857</a> <span class="preprocessor">#define SYSCFG_EXTICR1_EXTI1_PD         ((uint16_t)0x0030) </span>
<a name="l05858"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga8f5c3d1e914af78112179a13e9c736d6">05858</a> <span class="preprocessor">#define SYSCFG_EXTICR1_EXTI1_PE         ((uint16_t)0x0040) </span>
<a name="l05859"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga43ea410456aa31dfe6ec4889de62428b">05859</a> <span class="preprocessor">#define SYSCFG_EXTICR1_EXTI1_PF         ((uint16_t)0x0050) </span>
<a name="l05860"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaf9118efcafa89eeada012ff5ab98387d">05860</a> <span class="preprocessor">#define SYSCFG_EXTICR1_EXTI1_PG         ((uint16_t)0x0060) </span>
<a name="l05861"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga0ac69d7f391e837d8e8adce27704d87d">05861</a> <span class="preprocessor">#define SYSCFG_EXTICR1_EXTI1_PH         ((uint16_t)0x0070) </span>
<a name="l05862"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga010784c7bdee3c742b48c500ee52e223">05862</a> <span class="preprocessor">#define SYSCFG_EXTICR1_EXTI1_PI         ((uint16_t)0x0080) </span>
<a name="l05866"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga4096f472e87e021f4d4c94457ddaf5f1">05866</a> <span class="preprocessor">#define SYSCFG_EXTICR1_EXTI2_PA         ((uint16_t)0x0000) </span>
<a name="l05867"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga8cd240d61fd8a9666621f0dee07a08e5">05867</a> <span class="preprocessor">#define SYSCFG_EXTICR1_EXTI2_PB         ((uint16_t)0x0100) </span>
<a name="l05868"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga03ce7faaf56aa9efcc74af65619e275e">05868</a> <span class="preprocessor">#define SYSCFG_EXTICR1_EXTI2_PC         ((uint16_t)0x0200) </span>
<a name="l05869"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gafc35fcdcc89b487fab2901e1f5a7f41b">05869</a> <span class="preprocessor">#define SYSCFG_EXTICR1_EXTI2_PD         ((uint16_t)0x0300) </span>
<a name="l05870"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gac3f2b7465d81745f7a772e7689a29618">05870</a> <span class="preprocessor">#define SYSCFG_EXTICR1_EXTI2_PE         ((uint16_t)0x0400) </span>
<a name="l05871"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gab538769f1da056b3f57fb984adeef252">05871</a> <span class="preprocessor">#define SYSCFG_EXTICR1_EXTI2_PF         ((uint16_t)0x0500) </span>
<a name="l05872"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gabe4f5fa56e98b42b64e894f7a9216e05">05872</a> <span class="preprocessor">#define SYSCFG_EXTICR1_EXTI2_PG         ((uint16_t)0x0600) </span>
<a name="l05873"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gada5ffab92c39cbfc695ce57a4e6177e5">05873</a> <span class="preprocessor">#define SYSCFG_EXTICR1_EXTI2_PH         ((uint16_t)0x0700) </span>
<a name="l05874"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga00bc1224b7bfd46dcec32676a601de51">05874</a> <span class="preprocessor">#define SYSCFG_EXTICR1_EXTI2_PI         ((uint16_t)0x0800) </span>
<a name="l05878"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga45ed24773c389f4477944c2c43d106c0">05878</a> <span class="preprocessor">#define SYSCFG_EXTICR1_EXTI3_PA         ((uint16_t)0x0000) </span>
<a name="l05879"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga652183838bb096717551bf8a1917c257">05879</a> <span class="preprocessor">#define SYSCFG_EXTICR1_EXTI3_PB         ((uint16_t)0x1000) </span>
<a name="l05880"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gacb1809e5b8a9ebc4b1cbc8967d985929">05880</a> <span class="preprocessor">#define SYSCFG_EXTICR1_EXTI3_PC         ((uint16_t)0x2000) </span>
<a name="l05881"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga205440ffa174509d57c2b6a1814f8202">05881</a> <span class="preprocessor">#define SYSCFG_EXTICR1_EXTI3_PD         ((uint16_t)0x3000) </span>
<a name="l05882"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gab2b33beb6294fd7a257f0f3a36e0dcda">05882</a> <span class="preprocessor">#define SYSCFG_EXTICR1_EXTI3_PE         ((uint16_t)0x4000) </span>
<a name="l05883"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga40240ee616b6e06ecd8dabe9d8e56e71">05883</a> <span class="preprocessor">#define SYSCFG_EXTICR1_EXTI3_PF         ((uint16_t)0x5000) </span>
<a name="l05884"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaaa73420dbafb7f20f16c350a12b0a0f5">05884</a> <span class="preprocessor">#define SYSCFG_EXTICR1_EXTI3_PG         ((uint16_t)0x6000) </span>
<a name="l05885"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gae49def2961bf528448a4fbb4aa9c9d94">05885</a> <span class="preprocessor">#define SYSCFG_EXTICR1_EXTI3_PH         ((uint16_t)0x7000) </span>
<a name="l05886"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga337e37f58e8710ea8305a16c08e390b9">05886</a> <span class="preprocessor">#define SYSCFG_EXTICR1_EXTI3_PI         ((uint16_t)0x8000) </span>
<a name="l05888"></a>05888 <span class="preprocessor"></span><span class="comment">/*****************  Bit definition for SYSCFG_EXTICR2 register  ***************/</span>
<a name="l05889"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gad2a57b4872977812e60d521268190e1e">05889</a> <span class="preprocessor">#define SYSCFG_EXTICR2_EXTI4            ((uint16_t)0x000F) </span>
<a name="l05890"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga6682a1b97b04c5c33085ffd2827ccd17">05890</a> <span class="preprocessor">#define SYSCFG_EXTICR2_EXTI5            ((uint16_t)0x00F0) </span>
<a name="l05891"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga6c50caf6019fd7d5038d77e61f57ad7b">05891</a> <span class="preprocessor">#define SYSCFG_EXTICR2_EXTI6            ((uint16_t)0x0F00) </span>
<a name="l05892"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga638ea3bb014752813d064d37b3388950">05892</a> <span class="preprocessor">#define SYSCFG_EXTICR2_EXTI7            ((uint16_t)0xF000) </span>
<a name="l05896"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga51147f1747daf48dbcfad03285ae8889">05896</a> <span class="preprocessor">#define SYSCFG_EXTICR2_EXTI4_PA         ((uint16_t)0x0000) </span>
<a name="l05897"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga917aeb0df688d6b34785085fc85d9e47">05897</a> <span class="preprocessor">#define SYSCFG_EXTICR2_EXTI4_PB         ((uint16_t)0x0001) </span>
<a name="l05898"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga14ac312beeb19d3bb34a552546477613">05898</a> <span class="preprocessor">#define SYSCFG_EXTICR2_EXTI4_PC         ((uint16_t)0x0002) </span>
<a name="l05899"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaec62164e18d1b525e8272169b1efe642">05899</a> <span class="preprocessor">#define SYSCFG_EXTICR2_EXTI4_PD         ((uint16_t)0x0003) </span>
<a name="l05900"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gac1d2292b6a856a8a71d82f595b580b9b">05900</a> <span class="preprocessor">#define SYSCFG_EXTICR2_EXTI4_PE         ((uint16_t)0x0004) </span>
<a name="l05901"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga0adc3c72bddc65977e3ef56df74ed40e">05901</a> <span class="preprocessor">#define SYSCFG_EXTICR2_EXTI4_PF         ((uint16_t)0x0005) </span>
<a name="l05902"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gad5aad8ed8589e28677332ea0b200617b">05902</a> <span class="preprocessor">#define SYSCFG_EXTICR2_EXTI4_PG         ((uint16_t)0x0006) </span>
<a name="l05903"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga339f8994c317190a387a96b857aa79d0">05903</a> <span class="preprocessor">#define SYSCFG_EXTICR2_EXTI4_PH         ((uint16_t)0x0007) </span>
<a name="l05904"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaad36a509bf6deabd5446a07c20964f83">05904</a> <span class="preprocessor">#define SYSCFG_EXTICR2_EXTI4_PI         ((uint16_t)0x0008) </span>
<a name="l05908"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gafb9581c515a4bdf1ed88fe96d8c24794">05908</a> <span class="preprocessor">#define SYSCFG_EXTICR2_EXTI5_PA         ((uint16_t)0x0000) </span>
<a name="l05909"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga90a3f610234dfa13f56e72c76a12be74">05909</a> <span class="preprocessor">#define SYSCFG_EXTICR2_EXTI5_PB         ((uint16_t)0x0010) </span>
<a name="l05910"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga33b6bdc1b4bfeda0d4034dc67f1a6046">05910</a> <span class="preprocessor">#define SYSCFG_EXTICR2_EXTI5_PC         ((uint16_t)0x0020) </span>
<a name="l05911"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga0eea392f1530c7cb794a63d04e268a70">05911</a> <span class="preprocessor">#define SYSCFG_EXTICR2_EXTI5_PD         ((uint16_t)0x0030) </span>
<a name="l05912"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga8a4e6644d0144bfb0f913cf20eaf2f8e">05912</a> <span class="preprocessor">#define SYSCFG_EXTICR2_EXTI5_PE         ((uint16_t)0x0040) </span>
<a name="l05913"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga740e27c5bead2c914a134ac4ed4d05b3">05913</a> <span class="preprocessor">#define SYSCFG_EXTICR2_EXTI5_PF         ((uint16_t)0x0050) </span>
<a name="l05914"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga7d78839e577ab90090abcdcff88e18c8">05914</a> <span class="preprocessor">#define SYSCFG_EXTICR2_EXTI5_PG         ((uint16_t)0x0060) </span>
<a name="l05915"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga4a06842a64138b5010186d980cb594f9">05915</a> <span class="preprocessor">#define SYSCFG_EXTICR2_EXTI5_PH         ((uint16_t)0x0070) </span>
<a name="l05916"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga4f3c4ebe4d750f89465acd067ab0ee30">05916</a> <span class="preprocessor">#define SYSCFG_EXTICR2_EXTI5_PI         ((uint16_t)0x0080) </span>
<a name="l05920"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga3e87c78fb6dfde7c8b7f81fe3b65aae9">05920</a> <span class="preprocessor">#define SYSCFG_EXTICR2_EXTI6_PA         ((uint16_t)0x0000) </span>
<a name="l05921"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga6528de8e4ca8741e86ae254e1d6b2a70">05921</a> <span class="preprocessor">#define SYSCFG_EXTICR2_EXTI6_PB         ((uint16_t)0x0100) </span>
<a name="l05922"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga53d8745705d5eb84c70a8554f61d59ac">05922</a> <span class="preprocessor">#define SYSCFG_EXTICR2_EXTI6_PC         ((uint16_t)0x0200) </span>
<a name="l05923"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga26c97cdece451441e49120e754020cdc">05923</a> <span class="preprocessor">#define SYSCFG_EXTICR2_EXTI6_PD         ((uint16_t)0x0300) </span>
<a name="l05924"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga804218f2dd83c72e672143ec4f283ad3">05924</a> <span class="preprocessor">#define SYSCFG_EXTICR2_EXTI6_PE         ((uint16_t)0x0400) </span>
<a name="l05925"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga0d36de53e52c8a4c7991513fec326df6">05925</a> <span class="preprocessor">#define SYSCFG_EXTICR2_EXTI6_PF         ((uint16_t)0x0500) </span>
<a name="l05926"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga278997204184bfe7c951c1da327e6fb5">05926</a> <span class="preprocessor">#define SYSCFG_EXTICR2_EXTI6_PG         ((uint16_t)0x0600) </span>
<a name="l05927"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga283486dccd660fbf830e8c44b0161a63">05927</a> <span class="preprocessor">#define SYSCFG_EXTICR2_EXTI6_PH         ((uint16_t)0x0700) </span>
<a name="l05928"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga4222e7d9ed672ea2de3a038c23f9566b">05928</a> <span class="preprocessor">#define SYSCFG_EXTICR2_EXTI6_PI         ((uint16_t)0x0800) </span>
<a name="l05932"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga2f1bfd3af524288b6ce54d7f9aef410a">05932</a> <span class="preprocessor">#define SYSCFG_EXTICR2_EXTI7_PA         ((uint16_t)0x0000) </span>
<a name="l05933"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gab18d324986b18858f901febbcc2a57b7">05933</a> <span class="preprocessor">#define SYSCFG_EXTICR2_EXTI7_PB         ((uint16_t)0x1000) </span>
<a name="l05934"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gae9f53618d9cf13af2b2ecf191da8595a">05934</a> <span class="preprocessor">#define SYSCFG_EXTICR2_EXTI7_PC         ((uint16_t)0x2000) </span>
<a name="l05935"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gae38aa3b76227bb8e9d8cedc31c023f63">05935</a> <span class="preprocessor">#define SYSCFG_EXTICR2_EXTI7_PD         ((uint16_t)0x3000) </span>
<a name="l05936"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga90d097c1b5cbb62dc86327604907dcd4">05936</a> <span class="preprocessor">#define SYSCFG_EXTICR2_EXTI7_PE         ((uint16_t)0x4000) </span>
<a name="l05937"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaaf2c3a661be3569fffe11515e37de1e4">05937</a> <span class="preprocessor">#define SYSCFG_EXTICR2_EXTI7_PF         ((uint16_t)0x5000) </span>
<a name="l05938"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga987bc0488e57b14b0a98e4952df2b539">05938</a> <span class="preprocessor">#define SYSCFG_EXTICR2_EXTI7_PG         ((uint16_t)0x6000) </span>
<a name="l05939"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gab0ce56e15f4eb86a3e262deaa845cb99">05939</a> <span class="preprocessor">#define SYSCFG_EXTICR2_EXTI7_PH         ((uint16_t)0x7000) </span>
<a name="l05940"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gae68ca6758cf36232dd5ac63afae97cbc">05940</a> <span class="preprocessor">#define SYSCFG_EXTICR2_EXTI7_PI         ((uint16_t)0x8000) </span>
<a name="l05942"></a>05942 <span class="preprocessor"></span><span class="comment">/*****************  Bit definition for SYSCFG_EXTICR3 register  ***************/</span>
<a name="l05943"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaf2a656b18cc728e38acb72cf8d7e7935">05943</a> <span class="preprocessor">#define SYSCFG_EXTICR3_EXTI8            ((uint16_t)0x000F) </span>
<a name="l05944"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga002462e4c233adc6dd502de726994575">05944</a> <span class="preprocessor">#define SYSCFG_EXTICR3_EXTI9            ((uint16_t)0x00F0) </span>
<a name="l05945"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga8fc06b17c3b3d393b749bf9924a43a80">05945</a> <span class="preprocessor">#define SYSCFG_EXTICR3_EXTI10           ((uint16_t)0x0F00) </span>
<a name="l05946"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaa66cc9a579696c8f5c41f5f138ee1e67">05946</a> <span class="preprocessor">#define SYSCFG_EXTICR3_EXTI11           ((uint16_t)0xF000) </span>
<a name="l05951"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gae1c6843a871f1a06ca25c0de50048b10">05951</a> <span class="preprocessor">#define SYSCFG_EXTICR3_EXTI8_PA         ((uint16_t)0x0000) </span>
<a name="l05952"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga4818dc7bffc8dfc2acc48995a62e66c5">05952</a> <span class="preprocessor">#define SYSCFG_EXTICR3_EXTI8_PB         ((uint16_t)0x0001) </span>
<a name="l05953"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaba0d34ff57632d7753981404cef548e2">05953</a> <span class="preprocessor">#define SYSCFG_EXTICR3_EXTI8_PC         ((uint16_t)0x0002) </span>
<a name="l05954"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaa15260ba354dee354f0a71e7913009c3">05954</a> <span class="preprocessor">#define SYSCFG_EXTICR3_EXTI8_PD         ((uint16_t)0x0003) </span>
<a name="l05955"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga185287204b8cead31d3760f65c5ca19d">05955</a> <span class="preprocessor">#define SYSCFG_EXTICR3_EXTI8_PE         ((uint16_t)0x0004) </span>
<a name="l05956"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga425e41001af4b205b8fbfba723572a81">05956</a> <span class="preprocessor">#define SYSCFG_EXTICR3_EXTI8_PF         ((uint16_t)0x0005) </span>
<a name="l05957"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga2ecc7a12103b805da045093eb626614d">05957</a> <span class="preprocessor">#define SYSCFG_EXTICR3_EXTI8_PG         ((uint16_t)0x0006) </span>
<a name="l05958"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga0bf3fc7a2e35b7cbb9f08f2e3b06a3c4">05958</a> <span class="preprocessor">#define SYSCFG_EXTICR3_EXTI8_PH         ((uint16_t)0x0007) </span>
<a name="l05959"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaf0b679636c97041f5584012c78f6d7a3">05959</a> <span class="preprocessor">#define SYSCFG_EXTICR3_EXTI8_PI         ((uint16_t)0x0008) </span>
<a name="l05963"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga93e284e59c4ff887b2e79851ac0a81c4">05963</a> <span class="preprocessor">#define SYSCFG_EXTICR3_EXTI9_PA         ((uint16_t)0x0000) </span>
<a name="l05964"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaa9271cbc1ed09774a5fef4b379cab260">05964</a> <span class="preprocessor">#define SYSCFG_EXTICR3_EXTI9_PB         ((uint16_t)0x0010) </span>
<a name="l05965"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga1cc355176941881870c620c0837cab48">05965</a> <span class="preprocessor">#define SYSCFG_EXTICR3_EXTI9_PC         ((uint16_t)0x0020) </span>
<a name="l05966"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga75af3c7a94cfc78361c94b054f9fe064">05966</a> <span class="preprocessor">#define SYSCFG_EXTICR3_EXTI9_PD         ((uint16_t)0x0030) </span>
<a name="l05967"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gafce176ef4b389251dadb98d9f59f8fe6">05967</a> <span class="preprocessor">#define SYSCFG_EXTICR3_EXTI9_PE         ((uint16_t)0x0040) </span>
<a name="l05968"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga76ef2422b4d021d0cc038cb6325ed311">05968</a> <span class="preprocessor">#define SYSCFG_EXTICR3_EXTI9_PF         ((uint16_t)0x0050) </span>
<a name="l05969"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gae1b37bf746ccfe0750aebd28cfa52a0c">05969</a> <span class="preprocessor">#define SYSCFG_EXTICR3_EXTI9_PG         ((uint16_t)0x0060) </span>
<a name="l05970"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga31fdedc4a90328881fe8817f4eef61b2">05970</a> <span class="preprocessor">#define SYSCFG_EXTICR3_EXTI9_PH         ((uint16_t)0x0070) </span>
<a name="l05971"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga8cd8a0da1b9ede601094f6c651a499e4">05971</a> <span class="preprocessor">#define SYSCFG_EXTICR3_EXTI9_PI         ((uint16_t)0x0080) </span>
<a name="l05975"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga25acdbb9e916c440c41a060d861130ee">05975</a> <span class="preprocessor">#define SYSCFG_EXTICR3_EXTI10_PA        ((uint16_t)0x0000) </span>
<a name="l05976"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gab8d9aec4349bf38a4a9753b267b7de7e">05976</a> <span class="preprocessor">#define SYSCFG_EXTICR3_EXTI10_PB        ((uint16_t)0x0100) </span>
<a name="l05977"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga62d2b81d49e30ab4fe96572be5da8484">05977</a> <span class="preprocessor">#define SYSCFG_EXTICR3_EXTI10_PC        ((uint16_t)0x0200) </span>
<a name="l05978"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaab3553c540cd836d465824939c2e3b79">05978</a> <span class="preprocessor">#define SYSCFG_EXTICR3_EXTI10_PD        ((uint16_t)0x0300) </span>
<a name="l05979"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gabde568ef1c8f4bfaf18954e8ee0716a9">05979</a> <span class="preprocessor">#define SYSCFG_EXTICR3_EXTI10_PE        ((uint16_t)0x0400) </span>
<a name="l05980"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga09ed841a11367cda67c7a416ed6d9b99">05980</a> <span class="preprocessor">#define SYSCFG_EXTICR3_EXTI10_PF        ((uint16_t)0x0500) </span>
<a name="l05981"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga6dff840a6986b440e7633a3671ce57cc">05981</a> <span class="preprocessor">#define SYSCFG_EXTICR3_EXTI10_PG        ((uint16_t)0x0600) </span>
<a name="l05982"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga791e7d2bd23ae969540e5509c6718255">05982</a> <span class="preprocessor">#define SYSCFG_EXTICR3_EXTI10_PH        ((uint16_t)0x0700) </span>
<a name="l05983"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga8bee76cf4bed88ff7b51145393b2cd19">05983</a> <span class="preprocessor">#define SYSCFG_EXTICR3_EXTI10_PI        ((uint16_t)0x0800) </span>
<a name="l05987"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga0ca8a85d4512677eff6ed2aac897a366">05987</a> <span class="preprocessor">#define SYSCFG_EXTICR3_EXTI11_PA        ((uint16_t)0x0000) </span>
<a name="l05988"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaedb3a8cc6b1763e303986553c0e4e7f8">05988</a> <span class="preprocessor">#define SYSCFG_EXTICR3_EXTI11_PB        ((uint16_t)0x1000) </span>
<a name="l05989"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga0b01c8ba6cb27899a4f5fa494bf2b3f5">05989</a> <span class="preprocessor">#define SYSCFG_EXTICR3_EXTI11_PC        ((uint16_t)0x2000) </span>
<a name="l05990"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga6a69d636cda0352da0982c54f582787d">05990</a> <span class="preprocessor">#define SYSCFG_EXTICR3_EXTI11_PD        ((uint16_t)0x3000) </span>
<a name="l05991"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga44affe06868a0490f8d0cbbba51ff412">05991</a> <span class="preprocessor">#define SYSCFG_EXTICR3_EXTI11_PE        ((uint16_t)0x4000) </span>
<a name="l05992"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga66fb050835077047b576b3a510700d64">05992</a> <span class="preprocessor">#define SYSCFG_EXTICR3_EXTI11_PF        ((uint16_t)0x5000) </span>
<a name="l05993"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaf7b66390eeb4a8d50ebb7e87e2f281b3">05993</a> <span class="preprocessor">#define SYSCFG_EXTICR3_EXTI11_PG        ((uint16_t)0x6000) </span>
<a name="l05994"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaa58cfe5d03072c259582ba8fefa322bf">05994</a> <span class="preprocessor">#define SYSCFG_EXTICR3_EXTI11_PH        ((uint16_t)0x7000) </span>
<a name="l05995"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gafadb14df8764208abeeaf6197489f1b4">05995</a> <span class="preprocessor">#define SYSCFG_EXTICR3_EXTI11_PI        ((uint16_t)0x8000) </span>
<a name="l05997"></a>05997 <span class="preprocessor"></span><span class="comment">/*****************  Bit definition for SYSCFG_EXTICR4 register  ***************/</span>
<a name="l05998"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga9d4b31f4a75d935b6a52afe6a16463d1">05998</a> <span class="preprocessor">#define SYSCFG_EXTICR4_EXTI12           ((uint16_t)0x000F) </span>
<a name="l05999"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga7f04cda5bfe876431d5ad864302d7fa1">05999</a> <span class="preprocessor">#define SYSCFG_EXTICR4_EXTI13           ((uint16_t)0x00F0) </span>
<a name="l06000"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gabde06df3ec6e357374820a5a615991aa">06000</a> <span class="preprocessor">#define SYSCFG_EXTICR4_EXTI14           ((uint16_t)0x0F00) </span>
<a name="l06001"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gabd325c27cff1ae3de773d5e205a33f4e">06001</a> <span class="preprocessor">#define SYSCFG_EXTICR4_EXTI15           ((uint16_t)0xF000) </span>
<a name="l06005"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga3ceaa63866465faa8145ce0c5d9a44d0">06005</a> <span class="preprocessor">#define SYSCFG_EXTICR4_EXTI12_PA        ((uint16_t)0x0000) </span>
<a name="l06006"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gad8b00a462533a83c75c588340a2fa710">06006</a> <span class="preprocessor">#define SYSCFG_EXTICR4_EXTI12_PB        ((uint16_t)0x0001) </span>
<a name="l06007"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga4d27668b1fa6b1accde06aa144faa970">06007</a> <span class="preprocessor">#define SYSCFG_EXTICR4_EXTI12_PC        ((uint16_t)0x0002) </span>
<a name="l06008"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaa46ddd43a361d82abcb3cb7779ac74ff">06008</a> <span class="preprocessor">#define SYSCFG_EXTICR4_EXTI12_PD        ((uint16_t)0x0003) </span>
<a name="l06009"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga102ee111e27fd67228c169836dd0849e">06009</a> <span class="preprocessor">#define SYSCFG_EXTICR4_EXTI12_PE        ((uint16_t)0x0004) </span>
<a name="l06010"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gad9785209e7e13fcf9c4f82d57bae0837">06010</a> <span class="preprocessor">#define SYSCFG_EXTICR4_EXTI12_PF        ((uint16_t)0x0005) </span>
<a name="l06011"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga5c78af5f130089bec32d6f782288765c">06011</a> <span class="preprocessor">#define SYSCFG_EXTICR4_EXTI12_PG        ((uint16_t)0x0006) </span>
<a name="l06012"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga6bacbf87e34c3f3af8ad4adf0599ce81">06012</a> <span class="preprocessor">#define SYSCFG_EXTICR3_EXTI12_PH        ((uint16_t)0x0007) </span>
<a name="l06016"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga0514aaa894c9be44ba47c1346756f90b">06016</a> <span class="preprocessor">#define SYSCFG_EXTICR4_EXTI13_PA        ((uint16_t)0x0000) </span>
<a name="l06017"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga34e6776e3ebfecc9e78c5aec77c48eff">06017</a> <span class="preprocessor">#define SYSCFG_EXTICR4_EXTI13_PB        ((uint16_t)0x0010) </span>
<a name="l06018"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga1c7833d4e3c6b7f3878f62a200a6ab14">06018</a> <span class="preprocessor">#define SYSCFG_EXTICR4_EXTI13_PC        ((uint16_t)0x0020) </span>
<a name="l06019"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gabed530f628b3c37281f7a583af1cdb3c">06019</a> <span class="preprocessor">#define SYSCFG_EXTICR4_EXTI13_PD        ((uint16_t)0x0030) </span>
<a name="l06020"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga7dc5424bf39509a989464a81ec0714da">06020</a> <span class="preprocessor">#define SYSCFG_EXTICR4_EXTI13_PE        ((uint16_t)0x0040) </span>
<a name="l06021"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaaf4c995587d7bae6436e6793b8214627">06021</a> <span class="preprocessor">#define SYSCFG_EXTICR4_EXTI13_PF        ((uint16_t)0x0050) </span>
<a name="l06022"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga4dedb6adbf49c40e5a15ad2afc471155">06022</a> <span class="preprocessor">#define SYSCFG_EXTICR4_EXTI13_PG        ((uint16_t)0x0060) </span>
<a name="l06023"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga5088d8b62be3faaf7853907f82ba0084">06023</a> <span class="preprocessor">#define SYSCFG_EXTICR3_EXTI13_PH        ((uint16_t)0x0070) </span>
<a name="l06027"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga7ad140a68e3e4e0406a182a504679ea9">06027</a> <span class="preprocessor">#define SYSCFG_EXTICR4_EXTI14_PA        ((uint16_t)0x0000) </span>
<a name="l06028"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gae5c1b8a0f2b4f79bd868bbb2b4eff617">06028</a> <span class="preprocessor">#define SYSCFG_EXTICR4_EXTI14_PB        ((uint16_t)0x0100) </span>
<a name="l06029"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga8ca668cdd447acb1740566f46de5eb19">06029</a> <span class="preprocessor">#define SYSCFG_EXTICR4_EXTI14_PC        ((uint16_t)0x0200) </span>
<a name="l06030"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga2f20b2bfa9dc8b57a987c127c6dfa6fe">06030</a> <span class="preprocessor">#define SYSCFG_EXTICR4_EXTI14_PD        ((uint16_t)0x0300) </span>
<a name="l06031"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga4c13c49f6d93865ba05361cd86fddabf">06031</a> <span class="preprocessor">#define SYSCFG_EXTICR4_EXTI14_PE        ((uint16_t)0x0400) </span>
<a name="l06032"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga9df1ee6f60db93301acaa9220a591da9">06032</a> <span class="preprocessor">#define SYSCFG_EXTICR4_EXTI14_PF        ((uint16_t)0x0500) </span>
<a name="l06033"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gae8ae4d091bb2c7148188ef430734020a">06033</a> <span class="preprocessor">#define SYSCFG_EXTICR4_EXTI14_PG        ((uint16_t)0x0600) </span>
<a name="l06034"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga460355223eb849c797abfaa3dc1c717e">06034</a> <span class="preprocessor">#define SYSCFG_EXTICR3_EXTI14_PH        ((uint16_t)0x0700) </span>
<a name="l06038"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gae2f28920677dd99f9132ed28f7b1d5e2">06038</a> <span class="preprocessor">#define SYSCFG_EXTICR4_EXTI15_PA        ((uint16_t)0x0000) </span>
<a name="l06039"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga412f44d6a8f8f60420d7e7f8b5635e09">06039</a> <span class="preprocessor">#define SYSCFG_EXTICR4_EXTI15_PB        ((uint16_t)0x1000) </span>
<a name="l06040"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga49778592caef3a176ee82c9b83e25148">06040</a> <span class="preprocessor">#define SYSCFG_EXTICR4_EXTI15_PC        ((uint16_t)0x2000) </span>
<a name="l06041"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gac23e07d92a68cf7f8c3e58b479638885">06041</a> <span class="preprocessor">#define SYSCFG_EXTICR4_EXTI15_PD        ((uint16_t)0x3000) </span>
<a name="l06042"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaefd64bc0ea005d03068f2e9b8f425944">06042</a> <span class="preprocessor">#define SYSCFG_EXTICR4_EXTI15_PE        ((uint16_t)0x4000) </span>
<a name="l06043"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga5e88d51ebabe9f70e5b7c2ad60899d54">06043</a> <span class="preprocessor">#define SYSCFG_EXTICR4_EXTI15_PF        ((uint16_t)0x5000) </span>
<a name="l06044"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga51d341c45e98ccbd82bf7003bfa56e6b">06044</a> <span class="preprocessor">#define SYSCFG_EXTICR4_EXTI15_PG        ((uint16_t)0x6000) </span>
<a name="l06045"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga036482d96f0cabeddf2702777058cfc7">06045</a> <span class="preprocessor">#define SYSCFG_EXTICR3_EXTI15_PH        ((uint16_t)0x7000) </span>
<a name="l06047"></a>06047 <span class="preprocessor"></span><span class="comment">/******************  Bit definition for SYSCFG_CMPCR register  ****************/</span>  
<a name="l06048"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga261292a3a7ca1f767915b2e2ec3a7806">06048</a> <span class="preprocessor">#define SYSCFG_CMPCR_CMP_PD             ((uint32_t)0x00000001) </span>
<a name="l06049"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gae16bcca9b727e68f11467b6b3dad6215">06049</a> <span class="preprocessor">#define SYSCFG_CMPCR_READY              ((uint32_t)0x00000100) </span>
<a name="l06051"></a>06051 <span class="preprocessor"></span><span class="comment">/******************************************************************************/</span>
<a name="l06052"></a>06052 <span class="comment">/*                                                                            */</span>
<a name="l06053"></a>06053 <span class="comment">/*                                    TIM                                     */</span>
<a name="l06054"></a>06054 <span class="comment">/*                                                                            */</span>
<a name="l06055"></a>06055 <span class="comment">/******************************************************************************/</span>
<a name="l06056"></a>06056 <span class="comment">/*******************  Bit definition for TIM_CR1 register  ********************/</span>
<a name="l06057"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga93d86355e5e3b399ed45e1ca83abed2a">06057</a> <span class="preprocessor">#define  TIM_CR1_CEN                         ((uint16_t)0x0001)            </span>
<a name="l06058"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaa4f2a9f0cf7b60e3c623af451f141f3c">06058</a> <span class="preprocessor">#define  TIM_CR1_UDIS                        ((uint16_t)0x0002)            </span>
<a name="l06059"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga06c997c2c23e8bef7ca07579762c113b">06059</a> <span class="preprocessor">#define  TIM_CR1_URS                         ((uint16_t)0x0004)            </span>
<a name="l06060"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga6d3d1488296350af6d36fbbf71905d29">06060</a> <span class="preprocessor">#define  TIM_CR1_OPM                         ((uint16_t)0x0008)            </span>
<a name="l06061"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gacea10770904af189f3aaeb97b45722aa">06061</a> <span class="preprocessor">#define  TIM_CR1_DIR                         ((uint16_t)0x0010)            </span>
<a name="l06063"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga352b3c389bde13dd6049de0afdd874f1">06063</a> <span class="preprocessor">#define  TIM_CR1_CMS                         ((uint16_t)0x0060)            </span>
<a name="l06064"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga83ca6f7810aba73dc8c12f22092d97a2">06064</a> <span class="preprocessor">#define  TIM_CR1_CMS_0                       ((uint16_t)0x0020)            </span>
<a name="l06065"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gab3ee4adcde3c001d3b97d2eae1730ea9">06065</a> <span class="preprocessor">#define  TIM_CR1_CMS_1                       ((uint16_t)0x0040)            </span>
<a name="l06067"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga4a3ad409f6b147cdcbafbfe29102f3fd">06067</a> <span class="preprocessor">#define  TIM_CR1_ARPE                        ((uint16_t)0x0080)            </span>
<a name="l06069"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gacacc4ff7e5b75fd2e4e6b672ccd33a72">06069</a> <span class="preprocessor">#define  TIM_CR1_CKD                         ((uint16_t)0x0300)            </span>
<a name="l06070"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga458d536d82aa3db7d227b0f00b36808f">06070</a> <span class="preprocessor">#define  TIM_CR1_CKD_0                       ((uint16_t)0x0100)            </span>
<a name="l06071"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga7ff2d6c2c350e8b719a8ad49c9a6bcbe">06071</a> <span class="preprocessor">#define  TIM_CR1_CKD_1                       ((uint16_t)0x0200)            </span>
<a name="l06073"></a>06073 <span class="preprocessor"></span><span class="comment">/*******************  Bit definition for TIM_CR2 register  ********************/</span>
<a name="l06074"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaae22c9c1197107d6fa629f419a29541e">06074</a> <span class="preprocessor">#define  TIM_CR2_CCPC                        ((uint16_t)0x0001)            </span>
<a name="l06075"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaf0328c1339b2b1633ef7a8db4c02d0d5">06075</a> <span class="preprocessor">#define  TIM_CR2_CCUS                        ((uint16_t)0x0004)            </span>
<a name="l06076"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gade656832d3ec303a2a7a422638dd560e">06076</a> <span class="preprocessor">#define  TIM_CR2_CCDS                        ((uint16_t)0x0008)            </span>
<a name="l06078"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaaa6987d980e5c4c71c7d0faa1eb97a45">06078</a> <span class="preprocessor">#define  TIM_CR2_MMS                         ((uint16_t)0x0070)            </span>
<a name="l06079"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaf3e55308e84106d6501201e66bd46ab6">06079</a> <span class="preprocessor">#define  TIM_CR2_MMS_0                       ((uint16_t)0x0010)            </span>
<a name="l06080"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga4b1036929b0a4ba5bd5cced9b8e0f4c3">06080</a> <span class="preprocessor">#define  TIM_CR2_MMS_1                       ((uint16_t)0x0020)            </span>
<a name="l06081"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gacb74a815afdd856d51cfcf1ddf3fce6a">06081</a> <span class="preprocessor">#define  TIM_CR2_MMS_2                       ((uint16_t)0x0040)            </span>
<a name="l06083"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gad07504497b70af628fa1aee8fe7ef63c">06083</a> <span class="preprocessor">#define  TIM_CR2_TI1S                        ((uint16_t)0x0080)            </span>
<a name="l06084"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga31b26bf058f88d771c33aff85ec89358">06084</a> <span class="preprocessor">#define  TIM_CR2_OIS1                        ((uint16_t)0x0100)            </span>
<a name="l06085"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gae61f8d54923999fffb6db381e81f2b69">06085</a> <span class="preprocessor">#define  TIM_CR2_OIS1N                       ((uint16_t)0x0200)            </span>
<a name="l06086"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga61467648a433bd887683b9a4760021fa">06086</a> <span class="preprocessor">#define  TIM_CR2_OIS2                        ((uint16_t)0x0400)            </span>
<a name="l06087"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga769146db660b832f3ef26f892b567bd4">06087</a> <span class="preprocessor">#define  TIM_CR2_OIS2N                       ((uint16_t)0x0800)            </span>
<a name="l06088"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gad974d7c91edf6f1bd47e892b3b6f7565">06088</a> <span class="preprocessor">#define  TIM_CR2_OIS3                        ((uint16_t)0x1000)            </span>
<a name="l06089"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga20fb9b62a7e8d114fbd180abd9f8ceae">06089</a> <span class="preprocessor">#define  TIM_CR2_OIS3N                       ((uint16_t)0x2000)            </span>
<a name="l06090"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gad644f2f4b26e46587abedc8d3164e56e">06090</a> <span class="preprocessor">#define  TIM_CR2_OIS4                        ((uint16_t)0x4000)            </span>
<a name="l06092"></a>06092 <span class="preprocessor"></span><span class="comment">/*******************  Bit definition for TIM_SMCR register  *******************/</span>
<a name="l06093"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gae92349731a6107e0f3a251b44a67c7ea">06093</a> <span class="preprocessor">#define  TIM_SMCR_SMS                        ((uint16_t)0x0007)            </span>
<a name="l06094"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga7d1ebece401aeb12abd466d2eafa78b2">06094</a> <span class="preprocessor">#define  TIM_SMCR_SMS_0                      ((uint16_t)0x0001)            </span>
<a name="l06095"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaa980a3121ab6cda5a4a42b959da8421e">06095</a> <span class="preprocessor">#define  TIM_SMCR_SMS_1                      ((uint16_t)0x0002)            </span>
<a name="l06096"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga63847fc3c71f582403e6301b1229c3ed">06096</a> <span class="preprocessor">#define  TIM_SMCR_SMS_2                      ((uint16_t)0x0004)            </span>
<a name="l06098"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga8680e719bca2b672d850504220ae51fc">06098</a> <span class="preprocessor">#define  TIM_SMCR_TS                         ((uint16_t)0x0070)            </span>
<a name="l06099"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga8d1f040f9259acb3c2fba7b0c7eb3d96">06099</a> <span class="preprocessor">#define  TIM_SMCR_TS_0                       ((uint16_t)0x0010)            </span>
<a name="l06100"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gacb82212fcc89166a43ff97542da9182d">06100</a> <span class="preprocessor">#define  TIM_SMCR_TS_1                       ((uint16_t)0x0020)            </span>
<a name="l06101"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gacf0dbaf4a2ec8759f283f82a958ef6a8">06101</a> <span class="preprocessor">#define  TIM_SMCR_TS_2                       ((uint16_t)0x0040)            </span>
<a name="l06103"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga52101db4ca2c7b3003f1b16a49b2032c">06103</a> <span class="preprocessor">#define  TIM_SMCR_MSM                        ((uint16_t)0x0080)            </span>
<a name="l06105"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gae2ed8b32d9eb8eea251bd1dac4f34668">06105</a> <span class="preprocessor">#define  TIM_SMCR_ETF                        ((uint16_t)0x0F00)            </span>
<a name="l06106"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga43745c2894cfc1e5ee619ac85d8d5a62">06106</a> <span class="preprocessor">#define  TIM_SMCR_ETF_0                      ((uint16_t)0x0100)            </span>
<a name="l06107"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga661e6cce23553cf0ad3a60d8573b9a2c">06107</a> <span class="preprocessor">#define  TIM_SMCR_ETF_1                      ((uint16_t)0x0200)            </span>
<a name="l06108"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gafb5528381fb64ffbcc719de478391ae2">06108</a> <span class="preprocessor">#define  TIM_SMCR_ETF_2                      ((uint16_t)0x0400)            </span>
<a name="l06109"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga6082700946fc61a6f9d6209e258fcc14">06109</a> <span class="preprocessor">#define  TIM_SMCR_ETF_3                      ((uint16_t)0x0800)            </span>
<a name="l06111"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga0ebb9e631876435e276211d88e797386">06111</a> <span class="preprocessor">#define  TIM_SMCR_ETPS                       ((uint16_t)0x3000)            </span>
<a name="l06112"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga00b43cd09557a69ed10471ed76b228d8">06112</a> <span class="preprocessor">#define  TIM_SMCR_ETPS_0                     ((uint16_t)0x1000)            </span>
<a name="l06113"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gabf12f04862dbc92ca238d1518b27b16b">06113</a> <span class="preprocessor">#define  TIM_SMCR_ETPS_1                     ((uint16_t)0x2000)            </span>
<a name="l06115"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga331a1d5f39d5f47b5409054e693fc651">06115</a> <span class="preprocessor">#define  TIM_SMCR_ECE                        ((uint16_t)0x4000)            </span>
<a name="l06116"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga2a5f335c3d7a4f82d1e91dc1511e3322">06116</a> <span class="preprocessor">#define  TIM_SMCR_ETP                        ((uint16_t)0x8000)            </span>
<a name="l06118"></a>06118 <span class="preprocessor"></span><span class="comment">/*******************  Bit definition for TIM_DIER register  *******************/</span>
<a name="l06119"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga5c6d3e0495e6c06da4bdd0ad8995a32b">06119</a> <span class="preprocessor">#define  TIM_DIER_UIE                        ((uint16_t)0x0001)            </span>
<a name="l06120"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga1ba7f7ca97eeaf6cc23cd6765c6bf678">06120</a> <span class="preprocessor">#define  TIM_DIER_CC1IE                      ((uint16_t)0x0002)            </span>
<a name="l06121"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga757c59b690770adebf33e20d3d9dec15">06121</a> <span class="preprocessor">#define  TIM_DIER_CC2IE                      ((uint16_t)0x0004)            </span>
<a name="l06122"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga4edf003f04bcf250bddf5ed284201c2e">06122</a> <span class="preprocessor">#define  TIM_DIER_CC3IE                      ((uint16_t)0x0008)            </span>
<a name="l06123"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga6ad0f562a014572793b49fe87184338b">06123</a> <span class="preprocessor">#define  TIM_DIER_CC4IE                      ((uint16_t)0x0010)            </span>
<a name="l06124"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gade8a374e04740aac1ece248b868522fe">06124</a> <span class="preprocessor">#define  TIM_DIER_COMIE                      ((uint16_t)0x0020)            </span>
<a name="l06125"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaa755fef2c4e96c63f2ea1cd9a32f956a">06125</a> <span class="preprocessor">#define  TIM_DIER_TIE                        ((uint16_t)0x0040)            </span>
<a name="l06126"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga1fcb0d6d9fb7486a5901032fd81aef6a">06126</a> <span class="preprocessor">#define  TIM_DIER_BIE                        ((uint16_t)0x0080)            </span>
<a name="l06127"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gab9f47792b1c2f123464a2955f445c811">06127</a> <span class="preprocessor">#define  TIM_DIER_UDE                        ((uint16_t)0x0100)            </span>
<a name="l06128"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gae181bb16ec916aba8ba86f58f745fdfd">06128</a> <span class="preprocessor">#define  TIM_DIER_CC1DE                      ((uint16_t)0x0200)            </span>
<a name="l06129"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga58f97064991095b28c91028ca3cca28e">06129</a> <span class="preprocessor">#define  TIM_DIER_CC2DE                      ((uint16_t)0x0400)            </span>
<a name="l06130"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga1567bff5dc0564b26a8b3cff1f0fe0a4">06130</a> <span class="preprocessor">#define  TIM_DIER_CC3DE                      ((uint16_t)0x0800)            </span>
<a name="l06131"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaaba034412c54fa07024e516492748614">06131</a> <span class="preprocessor">#define  TIM_DIER_CC4DE                      ((uint16_t)0x1000)            </span>
<a name="l06132"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga79c3fab9d33de953a0a7f7d6516c73bc">06132</a> <span class="preprocessor">#define  TIM_DIER_COMDE                      ((uint16_t)0x2000)            </span>
<a name="l06133"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga5a752d4295f100708df9b8be5a7f439d">06133</a> <span class="preprocessor">#define  TIM_DIER_TDE                        ((uint16_t)0x4000)            </span>
<a name="l06135"></a>06135 <span class="preprocessor"></span><span class="comment">/********************  Bit definition for TIM_SR register  ********************/</span>
<a name="l06136"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gac8c03fabc10654d2a3f76ea40fcdbde6">06136</a> <span class="preprocessor">#define  TIM_SR_UIF                          ((uint16_t)0x0001)            </span>
<a name="l06137"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga449a61344a97608d85384c29f003c0e9">06137</a> <span class="preprocessor">#define  TIM_SR_CC1IF                        ((uint16_t)0x0002)            </span>
<a name="l06138"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga25a48bf099467169aa50464fbf462bd8">06138</a> <span class="preprocessor">#define  TIM_SR_CC2IF                        ((uint16_t)0x0004)            </span>
<a name="l06139"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gad3cf234a1059c0a04799e88382cdc0f2">06139</a> <span class="preprocessor">#define  TIM_SR_CC3IF                        ((uint16_t)0x0008)            </span>
<a name="l06140"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gacade8a06303bf216bfb03140c7e16cac">06140</a> <span class="preprocessor">#define  TIM_SR_CC4IF                        ((uint16_t)0x0010)            </span>
<a name="l06141"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga91775c029171c4585e9cca6ebf1cd57a">06141</a> <span class="preprocessor">#define  TIM_SR_COMIF                        ((uint16_t)0x0020)            </span>
<a name="l06142"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga7c8b16f3ced6ec03e9001276b134846e">06142</a> <span class="preprocessor">#define  TIM_SR_TIF                          ((uint16_t)0x0040)            </span>
<a name="l06143"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga6d52cd5a57c9a26b0d993c93d9875097">06143</a> <span class="preprocessor">#define  TIM_SR_BIF                          ((uint16_t)0x0080)            </span>
<a name="l06144"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga819c4b27f8fa99b537c4407521f9780c">06144</a> <span class="preprocessor">#define  TIM_SR_CC1OF                        ((uint16_t)0x0200)            </span>
<a name="l06145"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga3b7798da5863d559ea9a642af6658050">06145</a> <span class="preprocessor">#define  TIM_SR_CC2OF                        ((uint16_t)0x0400)            </span>
<a name="l06146"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaf7a2d4c831eb641ba082156e41d03358">06146</a> <span class="preprocessor">#define  TIM_SR_CC3OF                        ((uint16_t)0x0800)            </span>
<a name="l06147"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga81ba979e8309b66808e06e4de34bc740">06147</a> <span class="preprocessor">#define  TIM_SR_CC4OF                        ((uint16_t)0x1000)            </span>
<a name="l06149"></a>06149 <span class="preprocessor"></span><span class="comment">/*******************  Bit definition for TIM_EGR register  ********************/</span>
<a name="l06150"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga16f52a8e9aad153223405b965566ae91">06150</a> <span class="preprocessor">#define  TIM_EGR_UG                          ((uint8_t)0x01)               </span>
<a name="l06151"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga0a1318609761df5de5213e9e75b5aa6a">06151</a> <span class="preprocessor">#define  TIM_EGR_CC1G                        ((uint8_t)0x02)               </span>
<a name="l06152"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga5423de00e86aeb8a4657a509af485055">06152</a> <span class="preprocessor">#define  TIM_EGR_CC2G                        ((uint8_t)0x04)               </span>
<a name="l06153"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga064d2030abccc099ded418fd81d6aa07">06153</a> <span class="preprocessor">#define  TIM_EGR_CC3G                        ((uint8_t)0x08)               </span>
<a name="l06154"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga1c4e5555dd3be8ab1e631d1053f4a305">06154</a> <span class="preprocessor">#define  TIM_EGR_CC4G                        ((uint8_t)0x10)               </span>
<a name="l06155"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gadb06f8bb364307695c7d6a028391de7b">06155</a> <span class="preprocessor">#define  TIM_EGR_COMG                        ((uint8_t)0x20)               </span>
<a name="l06156"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga2eabface433d6adaa2dee3df49852585">06156</a> <span class="preprocessor">#define  TIM_EGR_TG                          ((uint8_t)0x40)               </span>
<a name="l06157"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga08c5635a0ac0ce5618485319a4fa0f18">06157</a> <span class="preprocessor">#define  TIM_EGR_BG                          ((uint8_t)0x80)               </span>
<a name="l06159"></a>06159 <span class="preprocessor"></span><span class="comment">/******************  Bit definition for TIM_CCMR1 register  *******************/</span>
<a name="l06160"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga95291df1eaf532c5c996d176648938eb">06160</a> <span class="preprocessor">#define  TIM_CCMR1_CC1S                      ((uint16_t)0x0003)            </span>
<a name="l06161"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga1e4968b5500d58d1aebce888da31eb5d">06161</a> <span class="preprocessor">#define  TIM_CCMR1_CC1S_0                    ((uint16_t)0x0001)            </span>
<a name="l06162"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga299207b757f31c9c02471ab5f4f59dbe">06162</a> <span class="preprocessor">#define  TIM_CCMR1_CC1S_1                    ((uint16_t)0x0002)            </span>
<a name="l06164"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gab9c5878e85ce02c22d8a374deebd1b6e">06164</a> <span class="preprocessor">#define  TIM_CCMR1_OC1FE                     ((uint16_t)0x0004)            </span>
<a name="l06165"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga1aa54ddf87a4b339881a8d5368ec80eb">06165</a> <span class="preprocessor">#define  TIM_CCMR1_OC1PE                     ((uint16_t)0x0008)            </span>
<a name="l06167"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga6ddb3dc889733e71d812baa3873cb13b">06167</a> <span class="preprocessor">#define  TIM_CCMR1_OC1M                      ((uint16_t)0x0070)            </span>
<a name="l06168"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga410a4752a98081bad8ab3f72b28e7c5f">06168</a> <span class="preprocessor">#define  TIM_CCMR1_OC1M_0                    ((uint16_t)0x0010)            </span>
<a name="l06169"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga8b5f6ec25063483641d6dc065d96d2b5">06169</a> <span class="preprocessor">#define  TIM_CCMR1_OC1M_1                    ((uint16_t)0x0020)            </span>
<a name="l06170"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gac024f6b9972b940925ab5786ee38701b">06170</a> <span class="preprocessor">#define  TIM_CCMR1_OC1M_2                    ((uint16_t)0x0040)            </span>
<a name="l06172"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga8f44c50cf9928d2afab014e2ca29baba">06172</a> <span class="preprocessor">#define  TIM_CCMR1_OC1CE                     ((uint16_t)0x0080)            </span>
<a name="l06174"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gacdb0986b78bea5b53ea61e4ddd667cbf">06174</a> <span class="preprocessor">#define  TIM_CCMR1_CC2S                      ((uint16_t)0x0300)            </span>
<a name="l06175"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga52bb0e50c11c35dcf42aeff7f1c22874">06175</a> <span class="preprocessor">#define  TIM_CCMR1_CC2S_0                    ((uint16_t)0x0100)            </span>
<a name="l06176"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga78303c37fdbe0be80f5fc7d21e9eba45">06176</a> <span class="preprocessor">#define  TIM_CCMR1_CC2S_1                    ((uint16_t)0x0200)            </span>
<a name="l06178"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga3bf610cf77c3c6c936ce7c4f85992e6c">06178</a> <span class="preprocessor">#define  TIM_CCMR1_OC2FE                     ((uint16_t)0x0400)            </span>
<a name="l06179"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gabddbf508732039730125ab3e87e9d370">06179</a> <span class="preprocessor">#define  TIM_CCMR1_OC2PE                     ((uint16_t)0x0800)            </span>
<a name="l06181"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga2326bafe64ba2ebdde908d66219eaa6f">06181</a> <span class="preprocessor">#define  TIM_CCMR1_OC2M                      ((uint16_t)0x7000)            </span>
<a name="l06182"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gadbb68b91da16ffd509a6c7a2a397083c">06182</a> <span class="preprocessor">#define  TIM_CCMR1_OC2M_0                    ((uint16_t)0x1000)            </span>
<a name="l06183"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaedb673b7e2c016191579de704eb842e4">06183</a> <span class="preprocessor">#define  TIM_CCMR1_OC2M_1                    ((uint16_t)0x2000)            </span>
<a name="l06184"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gad039a41e5fe97ddf904a0f9f95eb539e">06184</a> <span class="preprocessor">#define  TIM_CCMR1_OC2M_2                    ((uint16_t)0x4000)            </span>
<a name="l06186"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga19a8dd4ea04d262ec4e97b5c7a8677a5">06186</a> <span class="preprocessor">#define  TIM_CCMR1_OC2CE                     ((uint16_t)0x8000)            </span>
<a name="l06188"></a>06188 <span class="preprocessor"></span><span class="comment">/*----------------------------------------------------------------------------*/</span>
<a name="l06189"></a>06189 
<a name="l06190"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gab46b7186665f5308cd2ca52acfb63e72">06190</a> <span class="preprocessor">#define  TIM_CCMR1_IC1PSC                    ((uint16_t)0x000C)            </span>
<a name="l06191"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga05673358a44aeaa56daefca67341b29d">06191</a> <span class="preprocessor">#define  TIM_CCMR1_IC1PSC_0                  ((uint16_t)0x0004)            </span>
<a name="l06192"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaf42b75da9b2f127dca98b6ca616f7add">06192</a> <span class="preprocessor">#define  TIM_CCMR1_IC1PSC_1                  ((uint16_t)0x0008)            </span>
<a name="l06194"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gab0ee123675d8b8f98b5a6eeeccf37912">06194</a> <span class="preprocessor">#define  TIM_CCMR1_IC1F                      ((uint16_t)0x00F0)            </span>
<a name="l06195"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga7dde4afee556d2d8d22885f191da65a6">06195</a> <span class="preprocessor">#define  TIM_CCMR1_IC1F_0                    ((uint16_t)0x0010)            </span>
<a name="l06196"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga201491465e6864088210bccb8491be84">06196</a> <span class="preprocessor">#define  TIM_CCMR1_IC1F_1                    ((uint16_t)0x0020)            </span>
<a name="l06197"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gabaa55ab1e0109b055cabef579c32d67b">06197</a> <span class="preprocessor">#define  TIM_CCMR1_IC1F_2                    ((uint16_t)0x0040)            </span>
<a name="l06198"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga23da95530eb6d6451c7c9e451a580f42">06198</a> <span class="preprocessor">#define  TIM_CCMR1_IC1F_3                    ((uint16_t)0x0080)            </span>
<a name="l06200"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga5e8e704f9ce5742f45e15e3b3126aa9d">06200</a> <span class="preprocessor">#define  TIM_CCMR1_IC2PSC                    ((uint16_t)0x0C00)            </span>
<a name="l06201"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga39206b27b5b1c5941b2a14ee8e2f1223">06201</a> <span class="preprocessor">#define  TIM_CCMR1_IC2PSC_0                  ((uint16_t)0x0400)            </span>
<a name="l06202"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gae861d74943f3c045421f9fdc8b966841">06202</a> <span class="preprocessor">#define  TIM_CCMR1_IC2PSC_1                  ((uint16_t)0x0800)            </span>
<a name="l06204"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga2b942752d686c23323880ff576e7dffb">06204</a> <span class="preprocessor">#define  TIM_CCMR1_IC2F                      ((uint16_t)0xF000)            </span>
<a name="l06205"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga5d75acd7072f28844074702683d8493f">06205</a> <span class="preprocessor">#define  TIM_CCMR1_IC2F_0                    ((uint16_t)0x1000)            </span>
<a name="l06206"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga40e49318b54b16bda6fd7feea7c9a7dd">06206</a> <span class="preprocessor">#define  TIM_CCMR1_IC2F_1                    ((uint16_t)0x2000)            </span>
<a name="l06207"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga932148c784f5cbee4dfcafcbadaf0107">06207</a> <span class="preprocessor">#define  TIM_CCMR1_IC2F_2                    ((uint16_t)0x4000)            </span>
<a name="l06208"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gafece48b6f595ef9717d523fa23cea1e8">06208</a> <span class="preprocessor">#define  TIM_CCMR1_IC2F_3                    ((uint16_t)0x8000)            </span>
<a name="l06210"></a>06210 <span class="preprocessor"></span><span class="comment">/******************  Bit definition for TIM_CCMR2 register  *******************/</span>
<a name="l06211"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga2eabcc7e322b02c9c406b3ff70308260">06211</a> <span class="preprocessor">#define  TIM_CCMR2_CC3S                      ((uint16_t)0x0003)            </span>
<a name="l06212"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga68c04aea2e89f1e89bd323d6d6e5e6c0">06212</a> <span class="preprocessor">#define  TIM_CCMR2_CC3S_0                    ((uint16_t)0x0001)            </span>
<a name="l06213"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga4bed6648aad6e8d16196246b355452dc">06213</a> <span class="preprocessor">#define  TIM_CCMR2_CC3S_1                    ((uint16_t)0x0002)            </span>
<a name="l06215"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gae6d8d2847058747ce23a648668ce4dba">06215</a> <span class="preprocessor">#define  TIM_CCMR2_OC3FE                     ((uint16_t)0x0004)            </span>
<a name="l06216"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga276fd2250d2b085b73ef51cb4c099d24">06216</a> <span class="preprocessor">#define  TIM_CCMR2_OC3PE                     ((uint16_t)0x0008)            </span>
<a name="l06218"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga52095cae524adb237339bfee92e8168a">06218</a> <span class="preprocessor">#define  TIM_CCMR2_OC3M                      ((uint16_t)0x0070)            </span>
<a name="l06219"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga899b26ffa9c5f30f143306b8598a537f">06219</a> <span class="preprocessor">#define  TIM_CCMR2_OC3M_0                    ((uint16_t)0x0010)            </span>
<a name="l06220"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga91476ae2cc3449facafcad82569e14f8">06220</a> <span class="preprocessor">#define  TIM_CCMR2_OC3M_1                    ((uint16_t)0x0020)            </span>
<a name="l06221"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga20394da7afcada6c3fc455b05004cff5">06221</a> <span class="preprocessor">#define  TIM_CCMR2_OC3M_2                    ((uint16_t)0x0040)            </span>
<a name="l06223"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga4209d414df704ce96c54abb2ea2df66a">06223</a> <span class="preprocessor">#define  TIM_CCMR2_OC3CE                     ((uint16_t)0x0080)            </span>
<a name="l06225"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga294e216b50edd1c2f891143e1f971048">06225</a> <span class="preprocessor">#define  TIM_CCMR2_CC4S                      ((uint16_t)0x0300)            </span>
<a name="l06226"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gabebaa6bffd90b32563bd0fc1ff4a9499">06226</a> <span class="preprocessor">#define  TIM_CCMR2_CC4S_0                    ((uint16_t)0x0100)            </span>
<a name="l06227"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga6386ec77a3a451954325a1512d44f893">06227</a> <span class="preprocessor">#define  TIM_CCMR2_CC4S_1                    ((uint16_t)0x0200)            </span>
<a name="l06229"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga70dc197250c2699d470aea1a7a42ad57">06229</a> <span class="preprocessor">#define  TIM_CCMR2_OC4FE                     ((uint16_t)0x0400)            </span>
<a name="l06230"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga3e951cd3f6593e321cf79b662a1deaaa">06230</a> <span class="preprocessor">#define  TIM_CCMR2_OC4PE                     ((uint16_t)0x0800)            </span>
<a name="l06232"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gacbed61ff3ba57c7fe6d3386ce3b7af2b">06232</a> <span class="preprocessor">#define  TIM_CCMR2_OC4M                      ((uint16_t)0x7000)            </span>
<a name="l06233"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gad866f52cce9ce32e3c0d181007b82de5">06233</a> <span class="preprocessor">#define  TIM_CCMR2_OC4M_0                    ((uint16_t)0x1000)            </span>
<a name="l06234"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gafd97b1c86dd4953f3382fea317d165af">06234</a> <span class="preprocessor">#define  TIM_CCMR2_OC4M_1                    ((uint16_t)0x2000)            </span>
<a name="l06235"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga431e5cdc0f3dc02fa5a54aa5193ddbab">06235</a> <span class="preprocessor">#define  TIM_CCMR2_OC4M_2                    ((uint16_t)0x4000)            </span>
<a name="l06237"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga1447dfe94bdd234382bb1f43307ea5c3">06237</a> <span class="preprocessor">#define  TIM_CCMR2_OC4CE                     ((uint16_t)0x8000)            </span>
<a name="l06239"></a>06239 <span class="preprocessor"></span><span class="comment">/*----------------------------------------------------------------------------*/</span>
<a name="l06240"></a>06240 
<a name="l06241"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gafc3d11f2e968752bc9ec7131c986c3a6">06241</a> <span class="preprocessor">#define  TIM_CCMR2_IC3PSC                    ((uint16_t)0x000C)            </span>
<a name="l06242"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga588513395cbf8be6f4749c140fbf811c">06242</a> <span class="preprocessor">#define  TIM_CCMR2_IC3PSC_0                  ((uint16_t)0x0004)            </span>
<a name="l06243"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gacd27b9bdcc161c90dc1712074a66f29d">06243</a> <span class="preprocessor">#define  TIM_CCMR2_IC3PSC_1                  ((uint16_t)0x0008)            </span>
<a name="l06245"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gad218af6bd1de72891e1b85d582b766cd">06245</a> <span class="preprocessor">#define  TIM_CCMR2_IC3F                      ((uint16_t)0x00F0)            </span>
<a name="l06246"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga31d5450ebc9ac6ea833a2b341ceea061">06246</a> <span class="preprocessor">#define  TIM_CCMR2_IC3F_0                    ((uint16_t)0x0010)            </span>
<a name="l06247"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga26f92a3f831685d6df7ab69e68181849">06247</a> <span class="preprocessor">#define  TIM_CCMR2_IC3F_1                    ((uint16_t)0x0020)            </span>
<a name="l06248"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga5e7d7a3c2686a6e31adc1adf2ce65df9">06248</a> <span class="preprocessor">#define  TIM_CCMR2_IC3F_2                    ((uint16_t)0x0040)            </span>
<a name="l06249"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga9696c3da027f2b292d077f1ab4cdd14b">06249</a> <span class="preprocessor">#define  TIM_CCMR2_IC3F_3                    ((uint16_t)0x0080)            </span>
<a name="l06251"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga6fd7591e2de10272f7fafb08cdd1b7b0">06251</a> <span class="preprocessor">#define  TIM_CCMR2_IC4PSC                    ((uint16_t)0x0C00)            </span>
<a name="l06252"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga80f7d206409bc551eab06819e17451e4">06252</a> <span class="preprocessor">#define  TIM_CCMR2_IC4PSC_0                  ((uint16_t)0x0400)            </span>
<a name="l06253"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaf6690f5e98e02addd5e75643767c6d66">06253</a> <span class="preprocessor">#define  TIM_CCMR2_IC4PSC_1                  ((uint16_t)0x0800)            </span>
<a name="l06255"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gad51653fd06a591294d432385e794a19e">06255</a> <span class="preprocessor">#define  TIM_CCMR2_IC4F                      ((uint16_t)0xF000)            </span>
<a name="l06256"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga7d5fc8b9a6ea27582cb6c25f9654888c">06256</a> <span class="preprocessor">#define  TIM_CCMR2_IC4F_0                    ((uint16_t)0x1000)            </span>
<a name="l06257"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gac4dcc1562c0c017493e4ee6b32354e85">06257</a> <span class="preprocessor">#define  TIM_CCMR2_IC4F_1                    ((uint16_t)0x2000)            </span>
<a name="l06258"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga2b96de7db8b71ac7e414f247b871a53c">06258</a> <span class="preprocessor">#define  TIM_CCMR2_IC4F_2                    ((uint16_t)0x4000)            </span>
<a name="l06259"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga25d0f55e5b751f2caed6a943f5682a09">06259</a> <span class="preprocessor">#define  TIM_CCMR2_IC4F_3                    ((uint16_t)0x8000)            </span>
<a name="l06261"></a>06261 <span class="preprocessor"></span><span class="comment">/*******************  Bit definition for TIM_CCER register  *******************/</span>
<a name="l06262"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga3f494b9881e7b97bb2d79f7ad4e79937">06262</a> <span class="preprocessor">#define  TIM_CCER_CC1E                       ((uint16_t)0x0001)            </span>
<a name="l06263"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga0ca0aedba14241caff739afb3c3ee291">06263</a> <span class="preprocessor">#define  TIM_CCER_CC1P                       ((uint16_t)0x0002)            </span>
<a name="l06264"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga813056b3f90a13c4432aeba55f28957e">06264</a> <span class="preprocessor">#define  TIM_CCER_CC1NE                      ((uint16_t)0x0004)            </span>
<a name="l06265"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga403fc501d4d8de6cabee6b07acb81a36">06265</a> <span class="preprocessor">#define  TIM_CCER_CC1NP                      ((uint16_t)0x0008)            </span>
<a name="l06266"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga76392a4d63674cd0db0a55762458f16c">06266</a> <span class="preprocessor">#define  TIM_CCER_CC2E                       ((uint16_t)0x0010)            </span>
<a name="l06267"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga3136c6e776c6066509d298b6a9b34912">06267</a> <span class="preprocessor">#define  TIM_CCER_CC2P                       ((uint16_t)0x0020)            </span>
<a name="l06268"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga6a784649120eddec31998f34323d4156">06268</a> <span class="preprocessor">#define  TIM_CCER_CC2NE                      ((uint16_t)0x0040)            </span>
<a name="l06269"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga387de559d8b16b16f3934fddd2aa969f">06269</a> <span class="preprocessor">#define  TIM_CCER_CC2NP                      ((uint16_t)0x0080)            </span>
<a name="l06270"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga1da114e666b61f09cf25f50cdaa7f81f">06270</a> <span class="preprocessor">#define  TIM_CCER_CC3E                       ((uint16_t)0x0100)            </span>
<a name="l06271"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga6220a5cd34c7a7a39e10c854aa00d2e5">06271</a> <span class="preprocessor">#define  TIM_CCER_CC3P                       ((uint16_t)0x0200)            </span>
<a name="l06272"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gad46cce61d3bd83b64257ba75e54ee1aa">06272</a> <span class="preprocessor">#define  TIM_CCER_CC3NE                      ((uint16_t)0x0400)            </span>
<a name="l06273"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga4029686d3307111d3f9f4400e29e4521">06273</a> <span class="preprocessor">#define  TIM_CCER_CC3NP                      ((uint16_t)0x0800)            </span>
<a name="l06274"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga940b041ab5975311f42f26d314a4b621">06274</a> <span class="preprocessor">#define  TIM_CCER_CC4E                       ((uint16_t)0x1000)            </span>
<a name="l06275"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga3faf23dc47e1b0877352d7f5a00f72e1">06275</a> <span class="preprocessor">#define  TIM_CCER_CC4P                       ((uint16_t)0x2000)            </span>
<a name="l06276"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga41b88bff3f38cec0617ce66fa5aef260">06276</a> <span class="preprocessor">#define  TIM_CCER_CC4NP                      ((uint16_t)0x8000)            </span>
<a name="l06278"></a>06278 <span class="preprocessor"></span><span class="comment">/*******************  Bit definition for TIM_CNT register  ********************/</span>
<a name="l06279"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga8bc45c0315de82c1c3a38a243bcd00fc">06279</a> <span class="preprocessor">#define  TIM_CNT_CNT                         ((uint16_t)0xFFFF)            </span>
<a name="l06281"></a>06281 <span class="preprocessor"></span><span class="comment">/*******************  Bit definition for TIM_PSC register  ********************/</span>
<a name="l06282"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaefb85e4000ddab0ada67c5964810da35">06282</a> <span class="preprocessor">#define  TIM_PSC_PSC                         ((uint16_t)0xFFFF)            </span>
<a name="l06284"></a>06284 <span class="preprocessor"></span><span class="comment">/*******************  Bit definition for TIM_ARR register  ********************/</span>
<a name="l06285"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gace50256fdecc38f641050a4a3266e4d9">06285</a> <span class="preprocessor">#define  TIM_ARR_ARR                         ((uint16_t)0xFFFF)            </span>
<a name="l06287"></a>06287 <span class="preprocessor"></span><span class="comment">/*******************  Bit definition for TIM_RCR register  ********************/</span>
<a name="l06288"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gadcef8f28580e36cdfda3be1f7561afc7">06288</a> <span class="preprocessor">#define  TIM_RCR_REP                         ((uint8_t)0xFF)               </span>
<a name="l06290"></a>06290 <span class="preprocessor"></span><span class="comment">/*******************  Bit definition for TIM_CCR1 register  *******************/</span>
<a name="l06291"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gac927cc11eff415210dcf94657d8dfbe0">06291</a> <span class="preprocessor">#define  TIM_CCR1_CCR1                       ((uint16_t)0xFFFF)            </span>
<a name="l06293"></a>06293 <span class="preprocessor"></span><span class="comment">/*******************  Bit definition for TIM_CCR2 register  *******************/</span>
<a name="l06294"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga751e5efd90bdd1fd5f38609f3f5762ba">06294</a> <span class="preprocessor">#define  TIM_CCR2_CCR2                       ((uint16_t)0xFFFF)            </span>
<a name="l06296"></a>06296 <span class="preprocessor"></span><span class="comment">/*******************  Bit definition for TIM_CCR3 register  *******************/</span>
<a name="l06297"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga4e85064d37d387851e95c5c1f35315a1">06297</a> <span class="preprocessor">#define  TIM_CCR3_CCR3                       ((uint16_t)0xFFFF)            </span>
<a name="l06299"></a>06299 <span class="preprocessor"></span><span class="comment">/*******************  Bit definition for TIM_CCR4 register  *******************/</span>
<a name="l06300"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga15c9dd67a6701b5498926ae536773eca">06300</a> <span class="preprocessor">#define  TIM_CCR4_CCR4                       ((uint16_t)0xFFFF)            </span>
<a name="l06302"></a>06302 <span class="preprocessor"></span><span class="comment">/*******************  Bit definition for TIM_BDTR register  *******************/</span>
<a name="l06303"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gabcf985e9c78f15e1e44b2bc4d2bafc67">06303</a> <span class="preprocessor">#define  TIM_BDTR_DTG                        ((uint16_t)0x00FF)            </span>
<a name="l06304"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga4b575cca31b0e22ef1d5b842aa162bfc">06304</a> <span class="preprocessor">#define  TIM_BDTR_DTG_0                      ((uint16_t)0x0001)            </span>
<a name="l06305"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga0f33ae1e9b7847a60032a60d0cc7f81d">06305</a> <span class="preprocessor">#define  TIM_BDTR_DTG_1                      ((uint16_t)0x0002)            </span>
<a name="l06306"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga2f06a132eba960bd6cc972e3580d537c">06306</a> <span class="preprocessor">#define  TIM_BDTR_DTG_2                      ((uint16_t)0x0004)            </span>
<a name="l06307"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gae7868643a65285fc7132f040c8950f43">06307</a> <span class="preprocessor">#define  TIM_BDTR_DTG_3                      ((uint16_t)0x0008)            </span>
<a name="l06308"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga503b44e30a5fb77c34630d1faca70213">06308</a> <span class="preprocessor">#define  TIM_BDTR_DTG_4                      ((uint16_t)0x0010)            </span>
<a name="l06309"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga83a12ecb0a8dd21bc164d9a345ea564f">06309</a> <span class="preprocessor">#define  TIM_BDTR_DTG_5                      ((uint16_t)0x0020)            </span>
<a name="l06310"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaf7d418cbd0db89991522cb6be34a017e">06310</a> <span class="preprocessor">#define  TIM_BDTR_DTG_6                      ((uint16_t)0x0040)            </span>
<a name="l06311"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gac945c8bcf5567912a88eb2acee53c45b">06311</a> <span class="preprocessor">#define  TIM_BDTR_DTG_7                      ((uint16_t)0x0080)            </span>
<a name="l06313"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga7e4215d17f0548dfcf0b15fe4d0f4651">06313</a> <span class="preprocessor">#define  TIM_BDTR_LOCK                       ((uint16_t)0x0300)            </span>
<a name="l06314"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gabbd1736c8172e7cd098bb591264b07bf">06314</a> <span class="preprocessor">#define  TIM_BDTR_LOCK_0                     ((uint16_t)0x0100)            </span>
<a name="l06315"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga756df80ff8c34399435f52dca18e6eee">06315</a> <span class="preprocessor">#define  TIM_BDTR_LOCK_1                     ((uint16_t)0x0200)            </span>
<a name="l06317"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gab1cf04e70ccf3d4aba5afcf2496a411a">06317</a> <span class="preprocessor">#define  TIM_BDTR_OSSI                       ((uint16_t)0x0400)            </span>
<a name="l06318"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaf9435f36d53c6be1107e57ab6a82c16e">06318</a> <span class="preprocessor">#define  TIM_BDTR_OSSR                       ((uint16_t)0x0800)            </span>
<a name="l06319"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga74250b040dd9fd9c09dcc54cdd6d86d8">06319</a> <span class="preprocessor">#define  TIM_BDTR_BKE                        ((uint16_t)0x1000)            </span>
<a name="l06320"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga3247abbbf0d00260be051d176d88020e">06320</a> <span class="preprocessor">#define  TIM_BDTR_BKP                        ((uint16_t)0x2000)            </span>
<a name="l06321"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga59f15008050f91fa3ecc9eaaa971a509">06321</a> <span class="preprocessor">#define  TIM_BDTR_AOE                        ((uint16_t)0x4000)            </span>
<a name="l06322"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga277a096614829feba2d0a4fbb7d3dffc">06322</a> <span class="preprocessor">#define  TIM_BDTR_MOE                        ((uint16_t)0x8000)            </span>
<a name="l06324"></a>06324 <span class="preprocessor"></span><span class="comment">/*******************  Bit definition for TIM_DCR register  ********************/</span>
<a name="l06325"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gabf9051ecac123cd89f9d2a835e4cde2e">06325</a> <span class="preprocessor">#define  TIM_DCR_DBA                         ((uint16_t)0x001F)            </span>
<a name="l06326"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaaaf610e5fe4bb4b10736242df3b62bba">06326</a> <span class="preprocessor">#define  TIM_DCR_DBA_0                       ((uint16_t)0x0001)            </span>
<a name="l06327"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga9a0185643c163930e30f0a1cf5fe364e">06327</a> <span class="preprocessor">#define  TIM_DCR_DBA_1                       ((uint16_t)0x0002)            </span>
<a name="l06328"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaaa5a89b93b97b0968a7d5563a18ab9d1">06328</a> <span class="preprocessor">#define  TIM_DCR_DBA_2                       ((uint16_t)0x0004)            </span>
<a name="l06329"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga105f44ff18cbbd4ff4d60368c9184430">06329</a> <span class="preprocessor">#define  TIM_DCR_DBA_3                       ((uint16_t)0x0008)            </span>
<a name="l06330"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gabe1bc4b6dd7265dee2857f23d835b2dc">06330</a> <span class="preprocessor">#define  TIM_DCR_DBA_4                       ((uint16_t)0x0010)            </span>
<a name="l06332"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gab9e197a78484567d4c6093c28265f3eb">06332</a> <span class="preprocessor">#define  TIM_DCR_DBL                         ((uint16_t)0x1F00)            </span>
<a name="l06333"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga677195c0b4892bb6717564c0528126a9">06333</a> <span class="preprocessor">#define  TIM_DCR_DBL_0                       ((uint16_t)0x0100)            </span>
<a name="l06334"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gad427ba987877e491f7a2be60e320dbea">06334</a> <span class="preprocessor">#define  TIM_DCR_DBL_1                       ((uint16_t)0x0200)            </span>
<a name="l06335"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga369926f2a8ca5cf635ded9bb4619189c">06335</a> <span class="preprocessor">#define  TIM_DCR_DBL_2                       ((uint16_t)0x0400)            </span>
<a name="l06336"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga7f1ec849c41d1abd46c528a4ac378c03">06336</a> <span class="preprocessor">#define  TIM_DCR_DBL_3                       ((uint16_t)0x0800)            </span>
<a name="l06337"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga607d7b87b1b4bf167aabad36f922a8f9">06337</a> <span class="preprocessor">#define  TIM_DCR_DBL_4                       ((uint16_t)0x1000)            </span>
<a name="l06339"></a>06339 <span class="preprocessor"></span><span class="comment">/*******************  Bit definition for TIM_DMAR register  *******************/</span>
<a name="l06340"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga1afa2fc02bcd75c15122c4eb87d6cf83">06340</a> <span class="preprocessor">#define  TIM_DMAR_DMAB                       ((uint16_t)0xFFFF)            </span>
<a name="l06342"></a>06342 <span class="preprocessor"></span><span class="comment">/*******************  Bit definition for TIM_OR register  *********************/</span>
<a name="l06343"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga2916847c3545c06578d7ba8c381a4c20">06343</a> <span class="preprocessor">#define TIM_OR_TI4_RMP                       ((uint16_t)0x00C0)            </span>
<a name="l06344"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga9aea4f8a0abedbf08bb1e686933c1120">06344</a> <span class="preprocessor">#define TIM_OR_TI4_RMP_0                     ((uint16_t)0x0040)            </span>
<a name="l06345"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaa2a46aa18f15f2074b93233a18e85629">06345</a> <span class="preprocessor">#define TIM_OR_TI4_RMP_1                     ((uint16_t)0x0080)            </span>
<a name="l06346"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga4f413eac7f503dfddc9a9914efa555ac">06346</a> <span class="preprocessor">#define TIM_OR_ITR1_RMP                      ((uint16_t)0x0C00)            </span>
<a name="l06347"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gad7141f22c81a83134d9bb35cdeca5549">06347</a> <span class="preprocessor">#define TIM_OR_ITR1_RMP_0                    ((uint16_t)0x0400)            </span>
<a name="l06348"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga7ba54d02d962d04d2bdf16df11c7ccd0">06348</a> <span class="preprocessor">#define TIM_OR_ITR1_RMP_1                    ((uint16_t)0x0800)            </span>
<a name="l06351"></a>06351 <span class="preprocessor"></span><span class="comment">/******************************************************************************/</span>
<a name="l06352"></a>06352 <span class="comment">/*                                                                            */</span>
<a name="l06353"></a>06353 <span class="comment">/*         Universal Synchronous Asynchronous Receiver Transmitter            */</span>
<a name="l06354"></a>06354 <span class="comment">/*                                                                            */</span>
<a name="l06355"></a>06355 <span class="comment">/******************************************************************************/</span>
<a name="l06356"></a>06356 <span class="comment">/*******************  Bit definition for USART_SR register  *******************/</span>
<a name="l06357"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gac88be3484245af8c1b271ae5c1b97a14">06357</a> <span class="preprocessor">#define  USART_SR_PE                         ((uint16_t)0x0001)            </span>
<a name="l06358"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga9eb6fd3f820bd12e0b5a981de1894804">06358</a> <span class="preprocessor">#define  USART_SR_FE                         ((uint16_t)0x0002)            </span>
<a name="l06359"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga8938468c5666a8305ade6d80d467c572">06359</a> <span class="preprocessor">#define  USART_SR_NE                         ((uint16_t)0x0004)            </span>
<a name="l06360"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga4560fc7a60df4bdf402fc7219ae7b558">06360</a> <span class="preprocessor">#define  USART_SR_ORE                        ((uint16_t)0x0008)            </span>
<a name="l06361"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga336fa8c9965ce18c10972ac80ded611f">06361</a> <span class="preprocessor">#define  USART_SR_IDLE                       ((uint16_t)0x0010)            </span>
<a name="l06362"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaa0c99e2bb265b3d58a91aca7a93f7836">06362</a> <span class="preprocessor">#define  USART_SR_RXNE                       ((uint16_t)0x0020)            </span>
<a name="l06363"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga76229b05ac37a5a688e6ba45851a29f1">06363</a> <span class="preprocessor">#define  USART_SR_TC                         ((uint16_t)0x0040)            </span>
<a name="l06364"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga65e9cddf0890113d405342f1d8b5b980">06364</a> <span class="preprocessor">#define  USART_SR_TXE                        ((uint16_t)0x0080)            </span>
<a name="l06365"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga5b868b59576f42421226d35628c6b628">06365</a> <span class="preprocessor">#define  USART_SR_LBD                        ((uint16_t)0x0100)            </span>
<a name="l06366"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga9250ae2793db0541e6c4bb8837424541">06366</a> <span class="preprocessor">#define  USART_SR_CTS                        ((uint16_t)0x0200)            </span>
<a name="l06368"></a>06368 <span class="preprocessor"></span><span class="comment">/*******************  Bit definition for USART_DR register  *******************/</span>
<a name="l06369"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gad84ad1e1d0202b41021e2d6e40486bff">06369</a> <span class="preprocessor">#define  USART_DR_DR                         ((uint16_t)0x01FF)            </span>
<a name="l06371"></a>06371 <span class="preprocessor"></span><span class="comment">/******************  Bit definition for USART_BRR register  *******************/</span>
<a name="l06372"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga9dfae31be4ec2c8a3b0905eff30c7046">06372</a> <span class="preprocessor">#define  USART_BRR_DIV_Fraction              ((uint16_t)0x000F)            </span>
<a name="l06373"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga60cfa3802798306b86231f828ed2e71e">06373</a> <span class="preprocessor">#define  USART_BRR_DIV_Mantissa              ((uint16_t)0xFFF0)            </span>
<a name="l06375"></a>06375 <span class="preprocessor"></span><span class="comment">/******************  Bit definition for USART_CR1 register  *******************/</span>
<a name="l06376"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gac457c519baa28359ab7959fbe0c5cda1">06376</a> <span class="preprocessor">#define  USART_CR1_SBK                       ((uint16_t)0x0001)            </span>
<a name="l06377"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaa7d61ab5a4e2beaa3f591c56bd15a27b">06377</a> <span class="preprocessor">#define  USART_CR1_RWU                       ((uint16_t)0x0002)            </span>
<a name="l06378"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gada0d5d407a22264de847bc1b40a17aeb">06378</a> <span class="preprocessor">#define  USART_CR1_RE                        ((uint16_t)0x0004)            </span>
<a name="l06379"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gade7f090b04fd78b755b43357ecaa9622">06379</a> <span class="preprocessor">#define  USART_CR1_TE                        ((uint16_t)0x0008)            </span>
<a name="l06380"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga5221d09eebd12445a20f221bf98066f8">06380</a> <span class="preprocessor">#define  USART_CR1_IDLEIE                    ((uint16_t)0x0010)            </span>
<a name="l06381"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga91118f867adfdb2e805beea86666de04">06381</a> <span class="preprocessor">#define  USART_CR1_RXNEIE                    ((uint16_t)0x0020)            </span>
<a name="l06382"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaa17130690a1ca95b972429eb64d4254e">06382</a> <span class="preprocessor">#define  USART_CR1_TCIE                      ((uint16_t)0x0040)            </span>
<a name="l06383"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga70422871d15f974b464365e7fe1877e9">06383</a> <span class="preprocessor">#define  USART_CR1_TXEIE                     ((uint16_t)0x0080)            </span>
<a name="l06384"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga27405d413b6d355ccdb076d52fef6875">06384</a> <span class="preprocessor">#define  USART_CR1_PEIE                      ((uint16_t)0x0100)            </span>
<a name="l06385"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga2e159d36ab2c93a2c1942df60e9eebbe">06385</a> <span class="preprocessor">#define  USART_CR1_PS                        ((uint16_t)0x0200)            </span>
<a name="l06386"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga60f8fcf084f9a8514efafb617c70b074">06386</a> <span class="preprocessor">#define  USART_CR1_PCE                       ((uint16_t)0x0400)            </span>
<a name="l06387"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gad831dfc169fcf14b7284984dbecf322d">06387</a> <span class="preprocessor">#define  USART_CR1_WAKE                      ((uint16_t)0x0800)            </span>
<a name="l06388"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga95f0288b9c6aaeca7cb6550a2e6833e2">06388</a> <span class="preprocessor">#define  USART_CR1_M                         ((uint16_t)0x1000)            </span>
<a name="l06389"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga2bb650676aaae4a5203f372d497d5947">06389</a> <span class="preprocessor">#define  USART_CR1_UE                        ((uint16_t)0x2000)            </span>
<a name="l06390"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaed6caeb0cb48f1a7b34090f31a92a8e2">06390</a> <span class="preprocessor">#define  USART_CR1_OVER8                     ((uint16_t)0x8000)            </span>
<a name="l06392"></a>06392 <span class="preprocessor"></span><span class="comment">/******************  Bit definition for USART_CR2 register  *******************/</span>
<a name="l06393"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga3ee77fac25142271ad56d49685e518b3">06393</a> <span class="preprocessor">#define  USART_CR2_ADD                       ((uint16_t)0x000F)            </span>
<a name="l06394"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga7f9bc41700717fd93548e0e95b6072ed">06394</a> <span class="preprocessor">#define  USART_CR2_LBDL                      ((uint16_t)0x0020)            </span>
<a name="l06395"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaa02ef5d22553f028ea48e5d9f08192b4">06395</a> <span class="preprocessor">#define  USART_CR2_LBDIE                     ((uint16_t)0x0040)            </span>
<a name="l06396"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga4a62e93ae7864e89622bdd92508b615e">06396</a> <span class="preprocessor">#define  USART_CR2_LBCL                      ((uint16_t)0x0100)            </span>
<a name="l06397"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga362976ce813e58310399d113d2cf09cb">06397</a> <span class="preprocessor">#define  USART_CR2_CPHA                      ((uint16_t)0x0200)            </span>
<a name="l06398"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gafbb4336ac93d94d4e78f9fb7b3a0dc68">06398</a> <span class="preprocessor">#define  USART_CR2_CPOL                      ((uint16_t)0x0400)            </span>
<a name="l06399"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga42a396cde02ffa0c4d3fd9817b6af853">06399</a> <span class="preprocessor">#define  USART_CR2_CLKEN                     ((uint16_t)0x0800)            </span>
<a name="l06401"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaf993e483318ebcecffd18649de766dc6">06401</a> <span class="preprocessor">#define  USART_CR2_STOP                      ((uint16_t)0x3000)            </span>
<a name="l06402"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaee6ee01c6e5325b378b2209ef20d0a61">06402</a> <span class="preprocessor">#define  USART_CR2_STOP_0                    ((uint16_t)0x1000)            </span>
<a name="l06403"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga2b24d14f0e5d1c76c878b08aad44d02b">06403</a> <span class="preprocessor">#define  USART_CR2_STOP_1                    ((uint16_t)0x2000)            </span>
<a name="l06405"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gac8931efa62c29d92f5c0ec5a05f907ef">06405</a> <span class="preprocessor">#define  USART_CR2_LINEN                     ((uint16_t)0x4000)            </span>
<a name="l06407"></a>06407 <span class="preprocessor"></span><span class="comment">/******************  Bit definition for USART_CR3 register  *******************/</span>
<a name="l06408"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaaed1a39c551b1641128f81893ff558d0">06408</a> <span class="preprocessor">#define  USART_CR3_EIE                       ((uint16_t)0x0001)            </span>
<a name="l06409"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga31c66373bfbae7724c836ac63b8411dd">06409</a> <span class="preprocessor">#define  USART_CR3_IREN                      ((uint16_t)0x0002)            </span>
<a name="l06410"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga22af8d399f1adda62e31186f0309af80">06410</a> <span class="preprocessor">#define  USART_CR3_IRLP                      ((uint16_t)0x0004)            </span>
<a name="l06411"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gac71129810fab0b46d91161a39e3f8d01">06411</a> <span class="preprocessor">#define  USART_CR3_HDSEL                     ((uint16_t)0x0008)            </span>
<a name="l06412"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga3f3b70b2ee9ff0b59e952fd7ab04373c">06412</a> <span class="preprocessor">#define  USART_CR3_NACK                      ((uint16_t)0x0010)            </span>
<a name="l06413"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga9180b9249a26988f71d4bb2b0c3eec27">06413</a> <span class="preprocessor">#define  USART_CR3_SCEN                      ((uint16_t)0x0020)            </span>
<a name="l06414"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaff130f15493c765353ec2fd605667c5a">06414</a> <span class="preprocessor">#define  USART_CR3_DMAR                      ((uint16_t)0x0040)            </span>
<a name="l06415"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga5bb515d3814d448f84e2c98bf44f3993">06415</a> <span class="preprocessor">#define  USART_CR3_DMAT                      ((uint16_t)0x0080)            </span>
<a name="l06416"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga7c5d6fcd84a4728cda578a0339b4cac2">06416</a> <span class="preprocessor">#define  USART_CR3_RTSE                      ((uint16_t)0x0100)            </span>
<a name="l06417"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaa125f026b1ca2d76eab48b191baed265">06417</a> <span class="preprocessor">#define  USART_CR3_CTSE                      ((uint16_t)0x0200)            </span>
<a name="l06418"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga636d5ec2e9556949fc68d13ad45a1e90">06418</a> <span class="preprocessor">#define  USART_CR3_CTSIE                     ((uint16_t)0x0400)            </span>
<a name="l06419"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga9a96fb1a7beab602cbc8cb0393593826">06419</a> <span class="preprocessor">#define  USART_CR3_ONEBIT                    ((uint16_t)0x0800)            </span>
<a name="l06421"></a>06421 <span class="preprocessor"></span><span class="comment">/******************  Bit definition for USART_GTPR register  ******************/</span>
<a name="l06422"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaa0b423f0f4baf7d510ea70477e5c9203">06422</a> <span class="preprocessor">#define  USART_GTPR_PSC                      ((uint16_t)0x00FF)            </span>
<a name="l06423"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga2c49c90d83a0e3746b56b2a0a3b0ddcb">06423</a> <span class="preprocessor">#define  USART_GTPR_PSC_0                    ((uint16_t)0x0001)            </span>
<a name="l06424"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga8eab5000ab993991d0da8ffbd386c92b">06424</a> <span class="preprocessor">#define  USART_GTPR_PSC_1                    ((uint16_t)0x0002)            </span>
<a name="l06425"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga9d74604b6e1ab08a45ea4fe6b3f6b5cd">06425</a> <span class="preprocessor">#define  USART_GTPR_PSC_2                    ((uint16_t)0x0004)            </span>
<a name="l06426"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga1b6b237fcac675f8f047c4ff64248486">06426</a> <span class="preprocessor">#define  USART_GTPR_PSC_3                    ((uint16_t)0x0008)            </span>
<a name="l06427"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gad1c0e92df8edb974008b3d37d12f655a">06427</a> <span class="preprocessor">#define  USART_GTPR_PSC_4                    ((uint16_t)0x0010)            </span>
<a name="l06428"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga12dda4877432bc181c9684b0830b1b7b">06428</a> <span class="preprocessor">#define  USART_GTPR_PSC_5                    ((uint16_t)0x0020)            </span>
<a name="l06429"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga045e834b03e7a06b2005a13923af424a">06429</a> <span class="preprocessor">#define  USART_GTPR_PSC_6                    ((uint16_t)0x0040)            </span>
<a name="l06430"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gad3da67d3c9c3abf436098a86477d2dfc">06430</a> <span class="preprocessor">#define  USART_GTPR_PSC_7                    ((uint16_t)0x0080)            </span>
<a name="l06432"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga8e927fad0bfa430f54007e158e01f43b">06432</a> <span class="preprocessor">#define  USART_GTPR_GT                       ((uint16_t)0xFF00)            </span>
<a name="l06434"></a>06434 <span class="preprocessor"></span><span class="comment">/******************************************************************************/</span>
<a name="l06435"></a>06435 <span class="comment">/*                                                                            */</span>
<a name="l06436"></a>06436 <span class="comment">/*                            Window WATCHDOG                                 */</span>
<a name="l06437"></a>06437 <span class="comment">/*                                                                            */</span>
<a name="l06438"></a>06438 <span class="comment">/******************************************************************************/</span>
<a name="l06439"></a>06439 <span class="comment">/*******************  Bit definition for WWDG_CR register  ********************/</span>
<a name="l06440"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga400774feb33ed7544d57d6a0a76e0f70">06440</a> <span class="preprocessor">#define  WWDG_CR_T                           ((uint8_t)0x7F)               </span>
<a name="l06441"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga4d510237467b8e10ca1001574671ad8e">06441</a> <span class="preprocessor">#define  WWDG_CR_T0                          ((uint8_t)0x01)               </span>
<a name="l06442"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaed4b5d3f4d2e0540058fd2253a8feb95">06442</a> <span class="preprocessor">#define  WWDG_CR_T1                          ((uint8_t)0x02)               </span>
<a name="l06443"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaa4e9559da387f10bac2dc8ab0d4f6e6c">06443</a> <span class="preprocessor">#define  WWDG_CR_T2                          ((uint8_t)0x04)               </span>
<a name="l06444"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gab1e344f4a12c60e57cb643511379b261">06444</a> <span class="preprocessor">#define  WWDG_CR_T3                          ((uint8_t)0x08)               </span>
<a name="l06445"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaf1f89d17eb4b3bb1b67c2b0185061e45">06445</a> <span class="preprocessor">#define  WWDG_CR_T4                          ((uint8_t)0x10)               </span>
<a name="l06446"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gadc9870e0e3a5c171b9c1db817afcf0ee">06446</a> <span class="preprocessor">#define  WWDG_CR_T5                          ((uint8_t)0x20)               </span>
<a name="l06447"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gab3a493575c9a7c6006a3af9d13399268">06447</a> <span class="preprocessor">#define  WWDG_CR_T6                          ((uint8_t)0x40)               </span>
<a name="l06449"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gab647e9997b8b8e67de72af1aaea3f52f">06449</a> <span class="preprocessor">#define  WWDG_CR_WDGA                        ((uint8_t)0x80)               </span>
<a name="l06451"></a>06451 <span class="preprocessor"></span><span class="comment">/*******************  Bit definition for WWDG_CFR register  *******************/</span>
<a name="l06452"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gabfbb9991bd6a3699399ca569c71fe8c9">06452</a> <span class="preprocessor">#define  WWDG_CFR_W                          ((uint16_t)0x007F)            </span>
<a name="l06453"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gae37e08098d003f44eb8770a9d9bd40d0">06453</a> <span class="preprocessor">#define  WWDG_CFR_W0                         ((uint16_t)0x0001)            </span>
<a name="l06454"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga698b68239773862647ef5f9d963b80c4">06454</a> <span class="preprocessor">#define  WWDG_CFR_W1                         ((uint16_t)0x0002)            </span>
<a name="l06455"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga166845425e89d01552bac0baeec686d9">06455</a> <span class="preprocessor">#define  WWDG_CFR_W2                         ((uint16_t)0x0004)            </span>
<a name="l06456"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga344253edc9710aa6db6047b76cce723b">06456</a> <span class="preprocessor">#define  WWDG_CFR_W3                         ((uint16_t)0x0008)            </span>
<a name="l06457"></a><a class="code" href="group___peripheral___registers___bits___definition.html#gaec3a0817a2dcde78414d02c0cb5d201d">06457</a> <span class="preprocessor">#define  WWDG_CFR_W4                         ((uint16_t)0x0010)            </span>
<a name="l06458"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga8032c21626b10fcf5cd8ad36bc051663">06458</a> <span class="preprocessor">#define  WWDG_CFR_W5                         ((uint16_t)0x0020)            </span>
<a name="l06459"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga106cdb96da03ce192628f54cefcbec2f">06459</a> <span class="preprocessor">#define  WWDG_CFR_W6                         ((uint16_t)0x0040)            </span>
<a name="l06461"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga067b1d8238f1d5613481aba71a946638">06461</a> <span class="preprocessor">#define  WWDG_CFR_WDGTB                      ((uint16_t)0x0180)            </span>
<a name="l06462"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga4858525604534e493b8a09e0b04ace61">06462</a> <span class="preprocessor">#define  WWDG_CFR_WDGTB0                     ((uint16_t)0x0080)            </span>
<a name="l06463"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga9d53e6fa74c43522ebacd6dd6f450d33">06463</a> <span class="preprocessor">#define  WWDG_CFR_WDGTB1                     ((uint16_t)0x0100)            </span>
<a name="l06465"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga931941dc5d795502371ac5dd8fbac1e9">06465</a> <span class="preprocessor">#define  WWDG_CFR_EWI                        ((uint16_t)0x0200)            </span>
<a name="l06467"></a>06467 <span class="preprocessor"></span><span class="comment">/*******************  Bit definition for WWDG_SR register  ********************/</span>
<a name="l06468"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga96cf9ddd91b6079c5aceef6f3e857b69">06468</a> <span class="preprocessor">#define  WWDG_SR_EWIF                        ((uint8_t)0x01)               </span>
<a name="l06471"></a>06471 <span class="preprocessor"></span><span class="comment">/******************************************************************************/</span>
<a name="l06472"></a>06472 <span class="comment">/*                                                                            */</span>
<a name="l06473"></a>06473 <span class="comment">/*                                DBG                                         */</span>
<a name="l06474"></a>06474 <span class="comment">/*                                                                            */</span>
<a name="l06475"></a>06475 <span class="comment">/******************************************************************************/</span>
<a name="l06476"></a>06476 <span class="comment">/********************  Bit definition for DBGMCU_IDCODE register  *************/</span>
<a name="l06477"></a>06477 <span class="preprocessor">#define  DBGMCU_IDCODE_DEV_ID                ((uint32_t)0x00000FFF)</span>
<a name="l06478"></a>06478 <span class="preprocessor"></span><span class="preprocessor">#define  DBGMCU_IDCODE_REV_ID                ((uint32_t)0xFFFF0000)</span>
<a name="l06479"></a>06479 <span class="preprocessor"></span>
<a name="l06480"></a>06480 <span class="comment">/********************  Bit definition for DBGMCU_CR register  *****************/</span>
<a name="l06481"></a>06481 <span class="preprocessor">#define  DBGMCU_CR_DBG_SLEEP                 ((uint32_t)0x00000001)</span>
<a name="l06482"></a>06482 <span class="preprocessor"></span><span class="preprocessor">#define  DBGMCU_CR_DBG_STOP                  ((uint32_t)0x00000002)</span>
<a name="l06483"></a>06483 <span class="preprocessor"></span><span class="preprocessor">#define  DBGMCU_CR_DBG_STANDBY               ((uint32_t)0x00000004)</span>
<a name="l06484"></a>06484 <span class="preprocessor"></span><span class="preprocessor">#define  DBGMCU_CR_TRACE_IOEN                ((uint32_t)0x00000020)</span>
<a name="l06485"></a>06485 <span class="preprocessor"></span>
<a name="l06486"></a>06486 <span class="preprocessor">#define  DBGMCU_CR_TRACE_MODE                ((uint32_t)0x000000C0)</span>
<a name="l06487"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga2d41a4027853783633d929a43f8d6d85">06487</a> <span class="preprocessor"></span><span class="preprocessor">#define  DBGMCU_CR_TRACE_MODE_0              ((uint32_t)0x00000040)</span>
<a name="l06488"></a><a class="code" href="group___peripheral___registers___bits___definition.html#ga7ba3a830051b53d43d850768242c503e">06488</a> <span class="preprocessor">#define  DBGMCU_CR_TRACE_MODE_1              ((uint32_t)0x00000080)</span>
<a name="l06490"></a>06490 <span class="preprocessor"></span><span class="comment">/********************  Bit definition for DBGMCU_APB1_FZ register  ************/</span>
<a name="l06491"></a>06491 <span class="preprocessor">#define  DBGMCU_APB1_FZ_DBG_TIM2_STOP            ((uint32_t)0x00000001)</span>
<a name="l06492"></a>06492 <span class="preprocessor"></span><span class="preprocessor">#define  DBGMCU_APB1_FZ_DBG_TIM3_STOP            ((uint32_t)0x00000002)</span>
<a name="l06493"></a>06493 <span class="preprocessor"></span><span class="preprocessor">#define  DBGMCU_APB1_FZ_DBG_TIM4_STOP            ((uint32_t)0x00000004)</span>
<a name="l06494"></a>06494 <span class="preprocessor"></span><span class="preprocessor">#define  DBGMCU_APB1_FZ_DBG_TIM5_STOP            ((uint32_t)0x00000008)</span>
<a name="l06495"></a>06495 <span class="preprocessor"></span><span class="preprocessor">#define  DBGMCU_APB1_FZ_DBG_TIM6_STOP            ((uint32_t)0x00000010)</span>
<a name="l06496"></a>06496 <span class="preprocessor"></span><span class="preprocessor">#define  DBGMCU_APB1_FZ_DBG_TIM7_STOP            ((uint32_t)0x00000020)</span>
<a name="l06497"></a>06497 <span class="preprocessor"></span><span class="preprocessor">#define  DBGMCU_APB1_FZ_DBG_TIM12_STOP           ((uint32_t)0x00000040)</span>
<a name="l06498"></a>06498 <span class="preprocessor"></span><span class="preprocessor">#define  DBGMCU_APB1_FZ_DBG_TIM13_STOP           ((uint32_t)0x00000080)</span>
<a name="l06499"></a>06499 <span class="preprocessor"></span><span class="preprocessor">#define  DBGMCU_APB1_FZ_DBG_TIM14_STOP           ((uint32_t)0x00000100)</span>
<a name="l06500"></a>06500 <span class="preprocessor"></span><span class="preprocessor">#define  DBGMCU_APB1_FZ_DBG_RTC_STOP             ((uint32_t)0x00000400)</span>
<a name="l06501"></a>06501 <span class="preprocessor"></span><span class="preprocessor">#define  DBGMCU_APB1_FZ_DBG_WWDG_STOP            ((uint32_t)0x00000800)</span>
<a name="l06502"></a>06502 <span class="preprocessor"></span><span class="preprocessor">#define  DBGMCU_APB1_FZ_DBG_IWDG_STOP            ((uint32_t)0x00001000)</span>
<a name="l06503"></a>06503 <span class="preprocessor"></span><span class="preprocessor">#define  DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT   ((uint32_t)0x00200000)</span>
<a name="l06504"></a>06504 <span class="preprocessor"></span><span class="preprocessor">#define  DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT   ((uint32_t)0x00400000)</span>
<a name="l06505"></a>06505 <span class="preprocessor"></span><span class="preprocessor">#define  DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT   ((uint32_t)0x00800000)</span>
<a name="l06506"></a>06506 <span class="preprocessor"></span><span class="preprocessor">#define  DBGMCU_APB1_FZ_DBG_CAN1_STOP            ((uint32_t)0x02000000)</span>
<a name="l06507"></a>06507 <span class="preprocessor"></span><span class="preprocessor">#define  DBGMCU_APB1_FZ_DBG_CAN2_STOP            ((uint32_t)0x04000000)</span>
<a name="l06508"></a>06508 <span class="preprocessor"></span><span class="comment">/* Old IWDGSTOP bit definition, maintained for legacy purpose */</span>
<a name="l06509"></a>06509 <span class="preprocessor">#define  DBGMCU_APB1_FZ_DBG_IWDEG_STOP           DBGMCU_APB1_FZ_DBG_IWDG_STOP</span>
<a name="l06510"></a>06510 <span class="preprocessor"></span>
<a name="l06511"></a>06511 <span class="comment">/********************  Bit definition for DBGMCU_APB2_FZ register  ************/</span>
<a name="l06512"></a>06512 <span class="preprocessor">#define  DBGMCU_APB1_FZ_DBG_TIM1_STOP        ((uint32_t)0x00000001)</span>
<a name="l06513"></a>06513 <span class="preprocessor"></span><span class="preprocessor">#define  DBGMCU_APB1_FZ_DBG_TIM8_STOP        ((uint32_t)0x00000002)</span>
<a name="l06514"></a>06514 <span class="preprocessor"></span><span class="preprocessor">#define  DBGMCU_APB1_FZ_DBG_TIM9_STOP        ((uint32_t)0x00010000)</span>
<a name="l06515"></a>06515 <span class="preprocessor"></span><span class="preprocessor">#define  DBGMCU_APB1_FZ_DBG_TIM10_STOP       ((uint32_t)0x00020000)</span>
<a name="l06516"></a>06516 <span class="preprocessor"></span><span class="preprocessor">#define  DBGMCU_APB1_FZ_DBG_TIM11_STOP       ((uint32_t)0x00040000)</span>
<a name="l06517"></a>06517 <span class="preprocessor"></span>
<a name="l06518"></a>06518 <span class="comment">/******************************************************************************/</span>
<a name="l06519"></a>06519 <span class="comment">/*                                                                            */</span>
<a name="l06520"></a>06520 <span class="comment">/*                Ethernet MAC Registers bits definitions                     */</span>
<a name="l06521"></a>06521 <span class="comment">/*                                                                            */</span>
<a name="l06522"></a>06522 <span class="comment">/******************************************************************************/</span>
<a name="l06523"></a>06523 <span class="comment">/* Bit definition for Ethernet MAC Control Register register */</span>
<a name="l06524"></a>06524 <span class="preprocessor">#define ETH_MACCR_WD      ((uint32_t)0x00800000)  </span><span class="comment">/* Watchdog disable */</span>
<a name="l06525"></a>06525 <span class="preprocessor">#define ETH_MACCR_JD      ((uint32_t)0x00400000)  </span><span class="comment">/* Jabber disable */</span>
<a name="l06526"></a>06526 <span class="preprocessor">#define ETH_MACCR_IFG     ((uint32_t)0x000E0000)  </span><span class="comment">/* Inter-frame gap */</span>
<a name="l06527"></a>06527 <span class="preprocessor">#define ETH_MACCR_IFG_96Bit     ((uint32_t)0x00000000)  </span><span class="comment">/* Minimum IFG between frames during transmission is 96Bit */</span>
<a name="l06528"></a>06528 <span class="preprocessor">  #define ETH_MACCR_IFG_88Bit     ((uint32_t)0x00020000)  </span><span class="comment">/* Minimum IFG between frames during transmission is 88Bit */</span>
<a name="l06529"></a>06529 <span class="preprocessor">  #define ETH_MACCR_IFG_80Bit     ((uint32_t)0x00040000)  </span><span class="comment">/* Minimum IFG between frames during transmission is 80Bit */</span>
<a name="l06530"></a>06530 <span class="preprocessor">  #define ETH_MACCR_IFG_72Bit     ((uint32_t)0x00060000)  </span><span class="comment">/* Minimum IFG between frames during transmission is 72Bit */</span>
<a name="l06531"></a>06531 <span class="preprocessor">  #define ETH_MACCR_IFG_64Bit     ((uint32_t)0x00080000)  </span><span class="comment">/* Minimum IFG between frames during transmission is 64Bit */</span>        
<a name="l06532"></a>06532 <span class="preprocessor">  #define ETH_MACCR_IFG_56Bit     ((uint32_t)0x000A0000)  </span><span class="comment">/* Minimum IFG between frames during transmission is 56Bit */</span>
<a name="l06533"></a>06533 <span class="preprocessor">  #define ETH_MACCR_IFG_48Bit     ((uint32_t)0x000C0000)  </span><span class="comment">/* Minimum IFG between frames during transmission is 48Bit */</span>
<a name="l06534"></a>06534 <span class="preprocessor">  #define ETH_MACCR_IFG_40Bit     ((uint32_t)0x000E0000)  </span><span class="comment">/* Minimum IFG between frames during transmission is 40Bit */</span>              
<a name="l06535"></a>06535 <span class="preprocessor">#define ETH_MACCR_CSD     ((uint32_t)0x00010000)  </span><span class="comment">/* Carrier sense disable (during transmission) */</span>
<a name="l06536"></a>06536 <span class="preprocessor">#define ETH_MACCR_FES     ((uint32_t)0x00004000)  </span><span class="comment">/* Fast ethernet speed */</span>
<a name="l06537"></a>06537 <span class="preprocessor">#define ETH_MACCR_ROD     ((uint32_t)0x00002000)  </span><span class="comment">/* Receive own disable */</span>
<a name="l06538"></a>06538 <span class="preprocessor">#define ETH_MACCR_LM      ((uint32_t)0x00001000)  </span><span class="comment">/* loopback mode */</span>
<a name="l06539"></a>06539 <span class="preprocessor">#define ETH_MACCR_DM      ((uint32_t)0x00000800)  </span><span class="comment">/* Duplex mode */</span>
<a name="l06540"></a>06540 <span class="preprocessor">#define ETH_MACCR_IPCO    ((uint32_t)0x00000400)  </span><span class="comment">/* IP Checksum offload */</span>
<a name="l06541"></a>06541 <span class="preprocessor">#define ETH_MACCR_RD      ((uint32_t)0x00000200)  </span><span class="comment">/* Retry disable */</span>
<a name="l06542"></a>06542 <span class="preprocessor">#define ETH_MACCR_APCS    ((uint32_t)0x00000080)  </span><span class="comment">/* Automatic Pad/CRC stripping */</span>
<a name="l06543"></a>06543 <span class="preprocessor">#define ETH_MACCR_BL      ((uint32_t)0x00000060)  </span><span class="comment">/* Back-off limit: random integer number (r) of slot time delays before rescheduling</span>
<a name="l06544"></a>06544 <span class="comment">                                                       a transmission attempt during retries after a collision: 0 =&lt; r &lt;2^k */</span>
<a name="l06545"></a>06545 <span class="preprocessor">  #define ETH_MACCR_BL_10    ((uint32_t)0x00000000)  </span><span class="comment">/* k = min (n, 10) */</span>
<a name="l06546"></a>06546 <span class="preprocessor">  #define ETH_MACCR_BL_8     ((uint32_t)0x00000020)  </span><span class="comment">/* k = min (n, 8) */</span>
<a name="l06547"></a>06547 <span class="preprocessor">  #define ETH_MACCR_BL_4     ((uint32_t)0x00000040)  </span><span class="comment">/* k = min (n, 4) */</span>
<a name="l06548"></a>06548 <span class="preprocessor">  #define ETH_MACCR_BL_1     ((uint32_t)0x00000060)  </span><span class="comment">/* k = min (n, 1) */</span> 
<a name="l06549"></a>06549 <span class="preprocessor">#define ETH_MACCR_DC      ((uint32_t)0x00000010)  </span><span class="comment">/* Defferal check */</span>
<a name="l06550"></a>06550 <span class="preprocessor">#define ETH_MACCR_TE      ((uint32_t)0x00000008)  </span><span class="comment">/* Transmitter enable */</span>
<a name="l06551"></a>06551 <span class="preprocessor">#define ETH_MACCR_RE      ((uint32_t)0x00000004)  </span><span class="comment">/* Receiver enable */</span>
<a name="l06552"></a>06552 
<a name="l06553"></a>06553 <span class="comment">/* Bit definition for Ethernet MAC Frame Filter Register */</span>
<a name="l06554"></a>06554 <span class="preprocessor">#define ETH_MACFFR_RA     ((uint32_t)0x80000000)  </span><span class="comment">/* Receive all */</span> 
<a name="l06555"></a>06555 <span class="preprocessor">#define ETH_MACFFR_HPF    ((uint32_t)0x00000400)  </span><span class="comment">/* Hash or perfect filter */</span> 
<a name="l06556"></a>06556 <span class="preprocessor">#define ETH_MACFFR_SAF    ((uint32_t)0x00000200)  </span><span class="comment">/* Source address filter enable */</span> 
<a name="l06557"></a>06557 <span class="preprocessor">#define ETH_MACFFR_SAIF   ((uint32_t)0x00000100)  </span><span class="comment">/* SA inverse filtering */</span> 
<a name="l06558"></a>06558 <span class="preprocessor">#define ETH_MACFFR_PCF    ((uint32_t)0x000000C0)  </span><span class="comment">/* Pass control frames: 3 cases */</span>
<a name="l06559"></a>06559 <span class="preprocessor">  #define ETH_MACFFR_PCF_BlockAll                ((uint32_t)0x00000040)  </span><span class="comment">/* MAC filters all control frames from reaching the application */</span>
<a name="l06560"></a>06560 <span class="preprocessor">  #define ETH_MACFFR_PCF_ForwardAll              ((uint32_t)0x00000080)  </span><span class="comment">/* MAC forwards all control frames to application even if they fail the Address Filter */</span>
<a name="l06561"></a>06561 <span class="preprocessor">  #define ETH_MACFFR_PCF_ForwardPassedAddrFilter ((uint32_t)0x000000C0)  </span><span class="comment">/* MAC forwards control frames that pass the Address Filter. */</span> 
<a name="l06562"></a>06562 <span class="preprocessor">#define ETH_MACFFR_BFD    ((uint32_t)0x00000020)  </span><span class="comment">/* Broadcast frame disable */</span> 
<a name="l06563"></a>06563 <span class="preprocessor">#define ETH_MACFFR_PAM    ((uint32_t)0x00000010)  </span><span class="comment">/* Pass all mutlicast */</span> 
<a name="l06564"></a>06564 <span class="preprocessor">#define ETH_MACFFR_DAIF   ((uint32_t)0x00000008)  </span><span class="comment">/* DA Inverse filtering */</span> 
<a name="l06565"></a>06565 <span class="preprocessor">#define ETH_MACFFR_HM     ((uint32_t)0x00000004)  </span><span class="comment">/* Hash multicast */</span> 
<a name="l06566"></a>06566 <span class="preprocessor">#define ETH_MACFFR_HU     ((uint32_t)0x00000002)  </span><span class="comment">/* Hash unicast */</span>
<a name="l06567"></a>06567 <span class="preprocessor">#define ETH_MACFFR_PM     ((uint32_t)0x00000001)  </span><span class="comment">/* Promiscuous mode */</span>
<a name="l06568"></a>06568 
<a name="l06569"></a>06569 <span class="comment">/* Bit definition for Ethernet MAC Hash Table High Register */</span>
<a name="l06570"></a>06570 <span class="preprocessor">#define ETH_MACHTHR_HTH   ((uint32_t)0xFFFFFFFF)  </span><span class="comment">/* Hash table high */</span>
<a name="l06571"></a>06571 
<a name="l06572"></a>06572 <span class="comment">/* Bit definition for Ethernet MAC Hash Table Low Register */</span>
<a name="l06573"></a>06573 <span class="preprocessor">#define ETH_MACHTLR_HTL   ((uint32_t)0xFFFFFFFF)  </span><span class="comment">/* Hash table low */</span>
<a name="l06574"></a>06574 
<a name="l06575"></a>06575 <span class="comment">/* Bit definition for Ethernet MAC MII Address Register */</span>
<a name="l06576"></a>06576 <span class="preprocessor">#define ETH_MACMIIAR_PA   ((uint32_t)0x0000F800)  </span><span class="comment">/* Physical layer address */</span> 
<a name="l06577"></a>06577 <span class="preprocessor">#define ETH_MACMIIAR_MR   ((uint32_t)0x000007C0)  </span><span class="comment">/* MII register in the selected PHY */</span> 
<a name="l06578"></a>06578 <span class="preprocessor">#define ETH_MACMIIAR_CR   ((uint32_t)0x0000001C)  </span><span class="comment">/* CR clock range: 6 cases */</span> 
<a name="l06579"></a>06579 <span class="preprocessor">  #define ETH_MACMIIAR_CR_Div42   ((uint32_t)0x00000000)  </span><span class="comment">/* HCLK:60-100 MHz; MDC clock= HCLK/42 */</span>
<a name="l06580"></a>06580 <span class="preprocessor">  #define ETH_MACMIIAR_CR_Div62   ((uint32_t)0x00000004)  </span><span class="comment">/* HCLK:100-150 MHz; MDC clock= HCLK/62 */</span>
<a name="l06581"></a>06581 <span class="preprocessor">  #define ETH_MACMIIAR_CR_Div16   ((uint32_t)0x00000008)  </span><span class="comment">/* HCLK:20-35 MHz; MDC clock= HCLK/16 */</span>
<a name="l06582"></a>06582 <span class="preprocessor">  #define ETH_MACMIIAR_CR_Div26   ((uint32_t)0x0000000C)  </span><span class="comment">/* HCLK:35-60 MHz; MDC clock= HCLK/26 */</span>
<a name="l06583"></a>06583 <span class="preprocessor">  #define ETH_MACMIIAR_CR_Div102  ((uint32_t)0x00000010)  </span><span class="comment">/* HCLK:150-168 MHz; MDC clock= HCLK/102 */</span>  
<a name="l06584"></a>06584 <span class="preprocessor">#define ETH_MACMIIAR_MW   ((uint32_t)0x00000002)  </span><span class="comment">/* MII write */</span> 
<a name="l06585"></a>06585 <span class="preprocessor">#define ETH_MACMIIAR_MB   ((uint32_t)0x00000001)  </span><span class="comment">/* MII busy */</span> 
<a name="l06586"></a>06586   
<a name="l06587"></a>06587 <span class="comment">/* Bit definition for Ethernet MAC MII Data Register */</span>
<a name="l06588"></a>06588 <span class="preprocessor">#define ETH_MACMIIDR_MD   ((uint32_t)0x0000FFFF)  </span><span class="comment">/* MII data: read/write data from/to PHY */</span>
<a name="l06589"></a>06589 
<a name="l06590"></a>06590 <span class="comment">/* Bit definition for Ethernet MAC Flow Control Register */</span>
<a name="l06591"></a>06591 <span class="preprocessor">#define ETH_MACFCR_PT     ((uint32_t)0xFFFF0000)  </span><span class="comment">/* Pause time */</span>
<a name="l06592"></a>06592 <span class="preprocessor">#define ETH_MACFCR_ZQPD   ((uint32_t)0x00000080)  </span><span class="comment">/* Zero-quanta pause disable */</span>
<a name="l06593"></a>06593 <span class="preprocessor">#define ETH_MACFCR_PLT    ((uint32_t)0x00000030)  </span><span class="comment">/* Pause low threshold: 4 cases */</span>
<a name="l06594"></a>06594 <span class="preprocessor">  #define ETH_MACFCR_PLT_Minus4   ((uint32_t)0x00000000)  </span><span class="comment">/* Pause time minus 4 slot times */</span>
<a name="l06595"></a>06595 <span class="preprocessor">  #define ETH_MACFCR_PLT_Minus28  ((uint32_t)0x00000010)  </span><span class="comment">/* Pause time minus 28 slot times */</span>
<a name="l06596"></a>06596 <span class="preprocessor">  #define ETH_MACFCR_PLT_Minus144 ((uint32_t)0x00000020)  </span><span class="comment">/* Pause time minus 144 slot times */</span>
<a name="l06597"></a>06597 <span class="preprocessor">  #define ETH_MACFCR_PLT_Minus256 ((uint32_t)0x00000030)  </span><span class="comment">/* Pause time minus 256 slot times */</span>      
<a name="l06598"></a>06598 <span class="preprocessor">#define ETH_MACFCR_UPFD   ((uint32_t)0x00000008)  </span><span class="comment">/* Unicast pause frame detect */</span>
<a name="l06599"></a>06599 <span class="preprocessor">#define ETH_MACFCR_RFCE   ((uint32_t)0x00000004)  </span><span class="comment">/* Receive flow control enable */</span>
<a name="l06600"></a>06600 <span class="preprocessor">#define ETH_MACFCR_TFCE   ((uint32_t)0x00000002)  </span><span class="comment">/* Transmit flow control enable */</span>
<a name="l06601"></a>06601 <span class="preprocessor">#define ETH_MACFCR_FCBBPA ((uint32_t)0x00000001)  </span><span class="comment">/* Flow control busy/backpressure activate */</span>
<a name="l06602"></a>06602 
<a name="l06603"></a>06603 <span class="comment">/* Bit definition for Ethernet MAC VLAN Tag Register */</span>
<a name="l06604"></a>06604 <span class="preprocessor">#define ETH_MACVLANTR_VLANTC ((uint32_t)0x00010000)  </span><span class="comment">/* 12-bit VLAN tag comparison */</span>
<a name="l06605"></a>06605 <span class="preprocessor">#define ETH_MACVLANTR_VLANTI ((uint32_t)0x0000FFFF)  </span><span class="comment">/* VLAN tag identifier (for receive frames) */</span>
<a name="l06606"></a>06606 
<a name="l06607"></a>06607 <span class="comment">/* Bit definition for Ethernet MAC Remote Wake-UpFrame Filter Register */</span> 
<a name="l06608"></a>06608 <span class="preprocessor">#define ETH_MACRWUFFR_D   ((uint32_t)0xFFFFFFFF)  </span><span class="comment">/* Wake-up frame filter register data */</span>
<a name="l06609"></a>06609 <span class="comment">/* Eight sequential Writes to this address (offset 0x28) will write all Wake-UpFrame Filter Registers.</span>
<a name="l06610"></a>06610 <span class="comment">   Eight sequential Reads from this address (offset 0x28) will read all Wake-UpFrame Filter Registers. */</span>
<a name="l06611"></a>06611 <span class="comment">/* Wake-UpFrame Filter Reg0 : Filter 0 Byte Mask</span>
<a name="l06612"></a>06612 <span class="comment">   Wake-UpFrame Filter Reg1 : Filter 1 Byte Mask</span>
<a name="l06613"></a>06613 <span class="comment">   Wake-UpFrame Filter Reg2 : Filter 2 Byte Mask</span>
<a name="l06614"></a>06614 <span class="comment">   Wake-UpFrame Filter Reg3 : Filter 3 Byte Mask</span>
<a name="l06615"></a>06615 <span class="comment">   Wake-UpFrame Filter Reg4 : RSVD - Filter3 Command - RSVD - Filter2 Command - </span>
<a name="l06616"></a>06616 <span class="comment">                              RSVD - Filter1 Command - RSVD - Filter0 Command</span>
<a name="l06617"></a>06617 <span class="comment">   Wake-UpFrame Filter Re5 : Filter3 Offset - Filter2 Offset - Filter1 Offset - Filter0 Offset</span>
<a name="l06618"></a>06618 <span class="comment">   Wake-UpFrame Filter Re6 : Filter1 CRC16 - Filter0 CRC16</span>
<a name="l06619"></a>06619 <span class="comment">   Wake-UpFrame Filter Re7 : Filter3 CRC16 - Filter2 CRC16 */</span>
<a name="l06620"></a>06620 
<a name="l06621"></a>06621 <span class="comment">/* Bit definition for Ethernet MAC PMT Control and Status Register */</span> 
<a name="l06622"></a>06622 <span class="preprocessor">#define ETH_MACPMTCSR_WFFRPR ((uint32_t)0x80000000)  </span><span class="comment">/* Wake-Up Frame Filter Register Pointer Reset */</span>
<a name="l06623"></a>06623 <span class="preprocessor">#define ETH_MACPMTCSR_GU     ((uint32_t)0x00000200)  </span><span class="comment">/* Global Unicast */</span>
<a name="l06624"></a>06624 <span class="preprocessor">#define ETH_MACPMTCSR_WFR    ((uint32_t)0x00000040)  </span><span class="comment">/* Wake-Up Frame Received */</span>
<a name="l06625"></a>06625 <span class="preprocessor">#define ETH_MACPMTCSR_MPR    ((uint32_t)0x00000020)  </span><span class="comment">/* Magic Packet Received */</span>
<a name="l06626"></a>06626 <span class="preprocessor">#define ETH_MACPMTCSR_WFE    ((uint32_t)0x00000004)  </span><span class="comment">/* Wake-Up Frame Enable */</span>
<a name="l06627"></a>06627 <span class="preprocessor">#define ETH_MACPMTCSR_MPE    ((uint32_t)0x00000002)  </span><span class="comment">/* Magic Packet Enable */</span>
<a name="l06628"></a>06628 <span class="preprocessor">#define ETH_MACPMTCSR_PD     ((uint32_t)0x00000001)  </span><span class="comment">/* Power Down */</span>
<a name="l06629"></a>06629 
<a name="l06630"></a>06630 <span class="comment">/* Bit definition for Ethernet MAC Status Register */</span>
<a name="l06631"></a>06631 <span class="preprocessor">#define ETH_MACSR_TSTS      ((uint32_t)0x00000200)  </span><span class="comment">/* Time stamp trigger status */</span>
<a name="l06632"></a>06632 <span class="preprocessor">#define ETH_MACSR_MMCTS     ((uint32_t)0x00000040)  </span><span class="comment">/* MMC transmit status */</span>
<a name="l06633"></a>06633 <span class="preprocessor">#define ETH_MACSR_MMMCRS    ((uint32_t)0x00000020)  </span><span class="comment">/* MMC receive status */</span>
<a name="l06634"></a>06634 <span class="preprocessor">#define ETH_MACSR_MMCS      ((uint32_t)0x00000010)  </span><span class="comment">/* MMC status */</span>
<a name="l06635"></a>06635 <span class="preprocessor">#define ETH_MACSR_PMTS      ((uint32_t)0x00000008)  </span><span class="comment">/* PMT status */</span>
<a name="l06636"></a>06636 
<a name="l06637"></a>06637 <span class="comment">/* Bit definition for Ethernet MAC Interrupt Mask Register */</span>
<a name="l06638"></a>06638 <span class="preprocessor">#define ETH_MACIMR_TSTIM     ((uint32_t)0x00000200)  </span><span class="comment">/* Time stamp trigger interrupt mask */</span>
<a name="l06639"></a>06639 <span class="preprocessor">#define ETH_MACIMR_PMTIM     ((uint32_t)0x00000008)  </span><span class="comment">/* PMT interrupt mask */</span>
<a name="l06640"></a>06640 
<a name="l06641"></a>06641 <span class="comment">/* Bit definition for Ethernet MAC Address0 High Register */</span>
<a name="l06642"></a>06642 <span class="preprocessor">#define ETH_MACA0HR_MACA0H   ((uint32_t)0x0000FFFF)  </span><span class="comment">/* MAC address0 high */</span>
<a name="l06643"></a>06643 
<a name="l06644"></a>06644 <span class="comment">/* Bit definition for Ethernet MAC Address0 Low Register */</span>
<a name="l06645"></a>06645 <span class="preprocessor">#define ETH_MACA0LR_MACA0L   ((uint32_t)0xFFFFFFFF)  </span><span class="comment">/* MAC address0 low */</span>
<a name="l06646"></a>06646 
<a name="l06647"></a>06647 <span class="comment">/* Bit definition for Ethernet MAC Address1 High Register */</span>
<a name="l06648"></a>06648 <span class="preprocessor">#define ETH_MACA1HR_AE       ((uint32_t)0x80000000)  </span><span class="comment">/* Address enable */</span>
<a name="l06649"></a>06649 <span class="preprocessor">#define ETH_MACA1HR_SA       ((uint32_t)0x40000000)  </span><span class="comment">/* Source address */</span>
<a name="l06650"></a>06650 <span class="preprocessor">#define ETH_MACA1HR_MBC      ((uint32_t)0x3F000000)  </span><span class="comment">/* Mask byte control: bits to mask for comparison of the MAC Address bytes */</span>
<a name="l06651"></a>06651 <span class="preprocessor">  #define ETH_MACA1HR_MBC_HBits15_8    ((uint32_t)0x20000000)  </span><span class="comment">/* Mask MAC Address high reg bits [15:8] */</span>
<a name="l06652"></a>06652 <span class="preprocessor">  #define ETH_MACA1HR_MBC_HBits7_0     ((uint32_t)0x10000000)  </span><span class="comment">/* Mask MAC Address high reg bits [7:0] */</span>
<a name="l06653"></a>06653 <span class="preprocessor">  #define ETH_MACA1HR_MBC_LBits31_24   ((uint32_t)0x08000000)  </span><span class="comment">/* Mask MAC Address low reg bits [31:24] */</span>
<a name="l06654"></a>06654 <span class="preprocessor">  #define ETH_MACA1HR_MBC_LBits23_16   ((uint32_t)0x04000000)  </span><span class="comment">/* Mask MAC Address low reg bits [23:16] */</span>
<a name="l06655"></a>06655 <span class="preprocessor">  #define ETH_MACA1HR_MBC_LBits15_8    ((uint32_t)0x02000000)  </span><span class="comment">/* Mask MAC Address low reg bits [15:8] */</span>
<a name="l06656"></a>06656 <span class="preprocessor">  #define ETH_MACA1HR_MBC_LBits7_0     ((uint32_t)0x01000000)  </span><span class="comment">/* Mask MAC Address low reg bits [7:0] */</span> 
<a name="l06657"></a>06657 <span class="preprocessor">#define ETH_MACA1HR_MACA1H   ((uint32_t)0x0000FFFF)  </span><span class="comment">/* MAC address1 high */</span>
<a name="l06658"></a>06658 
<a name="l06659"></a>06659 <span class="comment">/* Bit definition for Ethernet MAC Address1 Low Register */</span>
<a name="l06660"></a>06660 <span class="preprocessor">#define ETH_MACA1LR_MACA1L   ((uint32_t)0xFFFFFFFF)  </span><span class="comment">/* MAC address1 low */</span>
<a name="l06661"></a>06661 
<a name="l06662"></a>06662 <span class="comment">/* Bit definition for Ethernet MAC Address2 High Register */</span>
<a name="l06663"></a>06663 <span class="preprocessor">#define ETH_MACA2HR_AE       ((uint32_t)0x80000000)  </span><span class="comment">/* Address enable */</span>
<a name="l06664"></a>06664 <span class="preprocessor">#define ETH_MACA2HR_SA       ((uint32_t)0x40000000)  </span><span class="comment">/* Source address */</span>
<a name="l06665"></a>06665 <span class="preprocessor">#define ETH_MACA2HR_MBC      ((uint32_t)0x3F000000)  </span><span class="comment">/* Mask byte control */</span>
<a name="l06666"></a>06666 <span class="preprocessor">  #define ETH_MACA2HR_MBC_HBits15_8    ((uint32_t)0x20000000)  </span><span class="comment">/* Mask MAC Address high reg bits [15:8] */</span>
<a name="l06667"></a>06667 <span class="preprocessor">  #define ETH_MACA2HR_MBC_HBits7_0     ((uint32_t)0x10000000)  </span><span class="comment">/* Mask MAC Address high reg bits [7:0] */</span>
<a name="l06668"></a>06668 <span class="preprocessor">  #define ETH_MACA2HR_MBC_LBits31_24   ((uint32_t)0x08000000)  </span><span class="comment">/* Mask MAC Address low reg bits [31:24] */</span>
<a name="l06669"></a>06669 <span class="preprocessor">  #define ETH_MACA2HR_MBC_LBits23_16   ((uint32_t)0x04000000)  </span><span class="comment">/* Mask MAC Address low reg bits [23:16] */</span>
<a name="l06670"></a>06670 <span class="preprocessor">  #define ETH_MACA2HR_MBC_LBits15_8    ((uint32_t)0x02000000)  </span><span class="comment">/* Mask MAC Address low reg bits [15:8] */</span>
<a name="l06671"></a>06671 <span class="preprocessor">  #define ETH_MACA2HR_MBC_LBits7_0     ((uint32_t)0x01000000)  </span><span class="comment">/* Mask MAC Address low reg bits [70] */</span>
<a name="l06672"></a>06672 <span class="preprocessor">#define ETH_MACA2HR_MACA2H   ((uint32_t)0x0000FFFF)  </span><span class="comment">/* MAC address1 high */</span>
<a name="l06673"></a>06673 
<a name="l06674"></a>06674 <span class="comment">/* Bit definition for Ethernet MAC Address2 Low Register */</span>
<a name="l06675"></a>06675 <span class="preprocessor">#define ETH_MACA2LR_MACA2L   ((uint32_t)0xFFFFFFFF)  </span><span class="comment">/* MAC address2 low */</span>
<a name="l06676"></a>06676 
<a name="l06677"></a>06677 <span class="comment">/* Bit definition for Ethernet MAC Address3 High Register */</span>
<a name="l06678"></a>06678 <span class="preprocessor">#define ETH_MACA3HR_AE       ((uint32_t)0x80000000)  </span><span class="comment">/* Address enable */</span>
<a name="l06679"></a>06679 <span class="preprocessor">#define ETH_MACA3HR_SA       ((uint32_t)0x40000000)  </span><span class="comment">/* Source address */</span>
<a name="l06680"></a>06680 <span class="preprocessor">#define ETH_MACA3HR_MBC      ((uint32_t)0x3F000000)  </span><span class="comment">/* Mask byte control */</span>
<a name="l06681"></a>06681 <span class="preprocessor">  #define ETH_MACA3HR_MBC_HBits15_8    ((uint32_t)0x20000000)  </span><span class="comment">/* Mask MAC Address high reg bits [15:8] */</span>
<a name="l06682"></a>06682 <span class="preprocessor">  #define ETH_MACA3HR_MBC_HBits7_0     ((uint32_t)0x10000000)  </span><span class="comment">/* Mask MAC Address high reg bits [7:0] */</span>
<a name="l06683"></a>06683 <span class="preprocessor">  #define ETH_MACA3HR_MBC_LBits31_24   ((uint32_t)0x08000000)  </span><span class="comment">/* Mask MAC Address low reg bits [31:24] */</span>
<a name="l06684"></a>06684 <span class="preprocessor">  #define ETH_MACA3HR_MBC_LBits23_16   ((uint32_t)0x04000000)  </span><span class="comment">/* Mask MAC Address low reg bits [23:16] */</span>
<a name="l06685"></a>06685 <span class="preprocessor">  #define ETH_MACA3HR_MBC_LBits15_8    ((uint32_t)0x02000000)  </span><span class="comment">/* Mask MAC Address low reg bits [15:8] */</span>
<a name="l06686"></a>06686 <span class="preprocessor">  #define ETH_MACA3HR_MBC_LBits7_0     ((uint32_t)0x01000000)  </span><span class="comment">/* Mask MAC Address low reg bits [70] */</span>
<a name="l06687"></a>06687 <span class="preprocessor">#define ETH_MACA3HR_MACA3H   ((uint32_t)0x0000FFFF)  </span><span class="comment">/* MAC address3 high */</span>
<a name="l06688"></a>06688 
<a name="l06689"></a>06689 <span class="comment">/* Bit definition for Ethernet MAC Address3 Low Register */</span>
<a name="l06690"></a>06690 <span class="preprocessor">#define ETH_MACA3LR_MACA3L   ((uint32_t)0xFFFFFFFF)  </span><span class="comment">/* MAC address3 low */</span>
<a name="l06691"></a>06691 
<a name="l06692"></a>06692 <span class="comment">/******************************************************************************/</span>
<a name="l06693"></a>06693 <span class="comment">/*                Ethernet MMC Registers bits definition                      */</span>
<a name="l06694"></a>06694 <span class="comment">/******************************************************************************/</span>
<a name="l06695"></a>06695 
<a name="l06696"></a>06696 <span class="comment">/* Bit definition for Ethernet MMC Contol Register */</span>
<a name="l06697"></a>06697 <span class="preprocessor">#define ETH_MMCCR_MCFHP      ((uint32_t)0x00000020)  </span><span class="comment">/* MMC counter Full-Half preset */</span>
<a name="l06698"></a>06698 <span class="preprocessor">#define ETH_MMCCR_MCP        ((uint32_t)0x00000010)  </span><span class="comment">/* MMC counter preset */</span>
<a name="l06699"></a>06699 <span class="preprocessor">#define ETH_MMCCR_MCF        ((uint32_t)0x00000008)  </span><span class="comment">/* MMC Counter Freeze */</span>
<a name="l06700"></a>06700 <span class="preprocessor">#define ETH_MMCCR_ROR        ((uint32_t)0x00000004)  </span><span class="comment">/* Reset on Read */</span>
<a name="l06701"></a>06701 <span class="preprocessor">#define ETH_MMCCR_CSR        ((uint32_t)0x00000002)  </span><span class="comment">/* Counter Stop Rollover */</span>
<a name="l06702"></a>06702 <span class="preprocessor">#define ETH_MMCCR_CR         ((uint32_t)0x00000001)  </span><span class="comment">/* Counters Reset */</span>
<a name="l06703"></a>06703 
<a name="l06704"></a>06704 <span class="comment">/* Bit definition for Ethernet MMC Receive Interrupt Register */</span>
<a name="l06705"></a>06705 <span class="preprocessor">#define ETH_MMCRIR_RGUFS     ((uint32_t)0x00020000)  </span><span class="comment">/* Set when Rx good unicast frames counter reaches half the maximum value */</span>
<a name="l06706"></a>06706 <span class="preprocessor">#define ETH_MMCRIR_RFAES     ((uint32_t)0x00000040)  </span><span class="comment">/* Set when Rx alignment error counter reaches half the maximum value */</span>
<a name="l06707"></a>06707 <span class="preprocessor">#define ETH_MMCRIR_RFCES     ((uint32_t)0x00000020)  </span><span class="comment">/* Set when Rx crc error counter reaches half the maximum value */</span>
<a name="l06708"></a>06708 
<a name="l06709"></a>06709 <span class="comment">/* Bit definition for Ethernet MMC Transmit Interrupt Register */</span>
<a name="l06710"></a>06710 <span class="preprocessor">#define ETH_MMCTIR_TGFS      ((uint32_t)0x00200000)  </span><span class="comment">/* Set when Tx good frame count counter reaches half the maximum value */</span>
<a name="l06711"></a>06711 <span class="preprocessor">#define ETH_MMCTIR_TGFMSCS   ((uint32_t)0x00008000)  </span><span class="comment">/* Set when Tx good multi col counter reaches half the maximum value */</span>
<a name="l06712"></a>06712 <span class="preprocessor">#define ETH_MMCTIR_TGFSCS    ((uint32_t)0x00004000)  </span><span class="comment">/* Set when Tx good single col counter reaches half the maximum value */</span>
<a name="l06713"></a>06713 
<a name="l06714"></a>06714 <span class="comment">/* Bit definition for Ethernet MMC Receive Interrupt Mask Register */</span>
<a name="l06715"></a>06715 <span class="preprocessor">#define ETH_MMCRIMR_RGUFM    ((uint32_t)0x00020000)  </span><span class="comment">/* Mask the interrupt when Rx good unicast frames counter reaches half the maximum value */</span>
<a name="l06716"></a>06716 <span class="preprocessor">#define ETH_MMCRIMR_RFAEM    ((uint32_t)0x00000040)  </span><span class="comment">/* Mask the interrupt when when Rx alignment error counter reaches half the maximum value */</span>
<a name="l06717"></a>06717 <span class="preprocessor">#define ETH_MMCRIMR_RFCEM    ((uint32_t)0x00000020)  </span><span class="comment">/* Mask the interrupt when Rx crc error counter reaches half the maximum value */</span>
<a name="l06718"></a>06718 
<a name="l06719"></a>06719 <span class="comment">/* Bit definition for Ethernet MMC Transmit Interrupt Mask Register */</span>
<a name="l06720"></a>06720 <span class="preprocessor">#define ETH_MMCTIMR_TGFM     ((uint32_t)0x00200000)  </span><span class="comment">/* Mask the interrupt when Tx good frame count counter reaches half the maximum value */</span>
<a name="l06721"></a>06721 <span class="preprocessor">#define ETH_MMCTIMR_TGFMSCM  ((uint32_t)0x00008000)  </span><span class="comment">/* Mask the interrupt when Tx good multi col counter reaches half the maximum value */</span>
<a name="l06722"></a>06722 <span class="preprocessor">#define ETH_MMCTIMR_TGFSCM   ((uint32_t)0x00004000)  </span><span class="comment">/* Mask the interrupt when Tx good single col counter reaches half the maximum value */</span>
<a name="l06723"></a>06723 
<a name="l06724"></a>06724 <span class="comment">/* Bit definition for Ethernet MMC Transmitted Good Frames after Single Collision Counter Register */</span>
<a name="l06725"></a>06725 <span class="preprocessor">#define ETH_MMCTGFSCCR_TGFSCC     ((uint32_t)0xFFFFFFFF)  </span><span class="comment">/* Number of successfully transmitted frames after a single collision in Half-duplex mode. */</span>
<a name="l06726"></a>06726 
<a name="l06727"></a>06727 <span class="comment">/* Bit definition for Ethernet MMC Transmitted Good Frames after More than a Single Collision Counter Register */</span>
<a name="l06728"></a>06728 <span class="preprocessor">#define ETH_MMCTGFMSCCR_TGFMSCC   ((uint32_t)0xFFFFFFFF)  </span><span class="comment">/* Number of successfully transmitted frames after more than a single collision in Half-duplex mode. */</span>
<a name="l06729"></a>06729 
<a name="l06730"></a>06730 <span class="comment">/* Bit definition for Ethernet MMC Transmitted Good Frames Counter Register */</span>
<a name="l06731"></a>06731 <span class="preprocessor">#define ETH_MMCTGFCR_TGFC    ((uint32_t)0xFFFFFFFF)  </span><span class="comment">/* Number of good frames transmitted. */</span>
<a name="l06732"></a>06732 
<a name="l06733"></a>06733 <span class="comment">/* Bit definition for Ethernet MMC Received Frames with CRC Error Counter Register */</span>
<a name="l06734"></a>06734 <span class="preprocessor">#define ETH_MMCRFCECR_RFCEC  ((uint32_t)0xFFFFFFFF)  </span><span class="comment">/* Number of frames received with CRC error. */</span>
<a name="l06735"></a>06735 
<a name="l06736"></a>06736 <span class="comment">/* Bit definition for Ethernet MMC Received Frames with Alignement Error Counter Register */</span>
<a name="l06737"></a>06737 <span class="preprocessor">#define ETH_MMCRFAECR_RFAEC  ((uint32_t)0xFFFFFFFF)  </span><span class="comment">/* Number of frames received with alignment (dribble) error */</span>
<a name="l06738"></a>06738 
<a name="l06739"></a>06739 <span class="comment">/* Bit definition for Ethernet MMC Received Good Unicast Frames Counter Register */</span>
<a name="l06740"></a>06740 <span class="preprocessor">#define ETH_MMCRGUFCR_RGUFC  ((uint32_t)0xFFFFFFFF)  </span><span class="comment">/* Number of good unicast frames received. */</span>
<a name="l06741"></a>06741 
<a name="l06742"></a>06742 <span class="comment">/******************************************************************************/</span>
<a name="l06743"></a>06743 <span class="comment">/*               Ethernet PTP Registers bits definition                       */</span>
<a name="l06744"></a>06744 <span class="comment">/******************************************************************************/</span>
<a name="l06745"></a>06745 
<a name="l06746"></a>06746 <span class="comment">/* Bit definition for Ethernet PTP Time Stamp Contol Register */</span>
<a name="l06747"></a>06747 <span class="preprocessor">#define ETH_PTPTSCR_TSCNT       ((uint32_t)0x00030000)  </span><span class="comment">/* Time stamp clock node type */</span>
<a name="l06748"></a>06748 <span class="preprocessor">#define ETH_PTPTSSR_TSSMRME     ((uint32_t)0x00008000)  </span><span class="comment">/* Time stamp snapshot for message relevant to master enable */</span>
<a name="l06749"></a>06749 <span class="preprocessor">#define ETH_PTPTSSR_TSSEME      ((uint32_t)0x00004000)  </span><span class="comment">/* Time stamp snapshot for event message enable */</span>
<a name="l06750"></a>06750 <span class="preprocessor">#define ETH_PTPTSSR_TSSIPV4FE   ((uint32_t)0x00002000)  </span><span class="comment">/* Time stamp snapshot for IPv4 frames enable */</span>
<a name="l06751"></a>06751 <span class="preprocessor">#define ETH_PTPTSSR_TSSIPV6FE   ((uint32_t)0x00001000)  </span><span class="comment">/* Time stamp snapshot for IPv6 frames enable */</span>
<a name="l06752"></a>06752 <span class="preprocessor">#define ETH_PTPTSSR_TSSPTPOEFE  ((uint32_t)0x00000800)  </span><span class="comment">/* Time stamp snapshot for PTP over ethernet frames enable */</span>
<a name="l06753"></a>06753 <span class="preprocessor">#define ETH_PTPTSSR_TSPTPPSV2E  ((uint32_t)0x00000400)  </span><span class="comment">/* Time stamp PTP packet snooping for version2 format enable */</span>
<a name="l06754"></a>06754 <span class="preprocessor">#define ETH_PTPTSSR_TSSSR       ((uint32_t)0x00000200)  </span><span class="comment">/* Time stamp Sub-seconds rollover */</span>
<a name="l06755"></a>06755 <span class="preprocessor">#define ETH_PTPTSSR_TSSARFE     ((uint32_t)0x00000100)  </span><span class="comment">/* Time stamp snapshot for all received frames enable */</span>
<a name="l06756"></a>06756 
<a name="l06757"></a>06757 <span class="preprocessor">#define ETH_PTPTSCR_TSARU    ((uint32_t)0x00000020)  </span><span class="comment">/* Addend register update */</span>
<a name="l06758"></a>06758 <span class="preprocessor">#define ETH_PTPTSCR_TSITE    ((uint32_t)0x00000010)  </span><span class="comment">/* Time stamp interrupt trigger enable */</span>
<a name="l06759"></a>06759 <span class="preprocessor">#define ETH_PTPTSCR_TSSTU    ((uint32_t)0x00000008)  </span><span class="comment">/* Time stamp update */</span>
<a name="l06760"></a>06760 <span class="preprocessor">#define ETH_PTPTSCR_TSSTI    ((uint32_t)0x00000004)  </span><span class="comment">/* Time stamp initialize */</span>
<a name="l06761"></a>06761 <span class="preprocessor">#define ETH_PTPTSCR_TSFCU    ((uint32_t)0x00000002)  </span><span class="comment">/* Time stamp fine or coarse update */</span>
<a name="l06762"></a>06762 <span class="preprocessor">#define ETH_PTPTSCR_TSE      ((uint32_t)0x00000001)  </span><span class="comment">/* Time stamp enable */</span>
<a name="l06763"></a>06763 
<a name="l06764"></a>06764 <span class="comment">/* Bit definition for Ethernet PTP Sub-Second Increment Register */</span>
<a name="l06765"></a>06765 <span class="preprocessor">#define ETH_PTPSSIR_STSSI    ((uint32_t)0x000000FF)  </span><span class="comment">/* System time Sub-second increment value */</span>
<a name="l06766"></a>06766 
<a name="l06767"></a>06767 <span class="comment">/* Bit definition for Ethernet PTP Time Stamp High Register */</span>
<a name="l06768"></a>06768 <span class="preprocessor">#define ETH_PTPTSHR_STS      ((uint32_t)0xFFFFFFFF)  </span><span class="comment">/* System Time second */</span>
<a name="l06769"></a>06769 
<a name="l06770"></a>06770 <span class="comment">/* Bit definition for Ethernet PTP Time Stamp Low Register */</span>
<a name="l06771"></a>06771 <span class="preprocessor">#define ETH_PTPTSLR_STPNS    ((uint32_t)0x80000000)  </span><span class="comment">/* System Time Positive or negative time */</span>
<a name="l06772"></a>06772 <span class="preprocessor">#define ETH_PTPTSLR_STSS     ((uint32_t)0x7FFFFFFF)  </span><span class="comment">/* System Time sub-seconds */</span>
<a name="l06773"></a>06773 
<a name="l06774"></a>06774 <span class="comment">/* Bit definition for Ethernet PTP Time Stamp High Update Register */</span>
<a name="l06775"></a>06775 <span class="preprocessor">#define ETH_PTPTSHUR_TSUS    ((uint32_t)0xFFFFFFFF)  </span><span class="comment">/* Time stamp update seconds */</span>
<a name="l06776"></a>06776 
<a name="l06777"></a>06777 <span class="comment">/* Bit definition for Ethernet PTP Time Stamp Low Update Register */</span>
<a name="l06778"></a>06778 <span class="preprocessor">#define ETH_PTPTSLUR_TSUPNS  ((uint32_t)0x80000000)  </span><span class="comment">/* Time stamp update Positive or negative time */</span>
<a name="l06779"></a>06779 <span class="preprocessor">#define ETH_PTPTSLUR_TSUSS   ((uint32_t)0x7FFFFFFF)  </span><span class="comment">/* Time stamp update sub-seconds */</span>
<a name="l06780"></a>06780 
<a name="l06781"></a>06781 <span class="comment">/* Bit definition for Ethernet PTP Time Stamp Addend Register */</span>
<a name="l06782"></a>06782 <span class="preprocessor">#define ETH_PTPTSAR_TSA      ((uint32_t)0xFFFFFFFF)  </span><span class="comment">/* Time stamp addend */</span>
<a name="l06783"></a>06783 
<a name="l06784"></a>06784 <span class="comment">/* Bit definition for Ethernet PTP Target Time High Register */</span>
<a name="l06785"></a>06785 <span class="preprocessor">#define ETH_PTPTTHR_TTSH     ((uint32_t)0xFFFFFFFF)  </span><span class="comment">/* Target time stamp high */</span>
<a name="l06786"></a>06786 
<a name="l06787"></a>06787 <span class="comment">/* Bit definition for Ethernet PTP Target Time Low Register */</span>
<a name="l06788"></a>06788 <span class="preprocessor">#define ETH_PTPTTLR_TTSL     ((uint32_t)0xFFFFFFFF)  </span><span class="comment">/* Target time stamp low */</span>
<a name="l06789"></a>06789 
<a name="l06790"></a>06790 <span class="comment">/* Bit definition for Ethernet PTP Time Stamp Status Register */</span>
<a name="l06791"></a>06791 <span class="preprocessor">#define ETH_PTPTSSR_TSTTR    ((uint32_t)0x00000020)  </span><span class="comment">/* Time stamp target time reached */</span>
<a name="l06792"></a>06792 <span class="preprocessor">#define ETH_PTPTSSR_TSSO     ((uint32_t)0x00000010)  </span><span class="comment">/* Time stamp seconds overflow */</span>
<a name="l06793"></a>06793 
<a name="l06794"></a>06794 <span class="comment">/******************************************************************************/</span>
<a name="l06795"></a>06795 <span class="comment">/*                 Ethernet DMA Registers bits definition                     */</span>
<a name="l06796"></a>06796 <span class="comment">/******************************************************************************/</span>
<a name="l06797"></a>06797 
<a name="l06798"></a>06798 <span class="comment">/* Bit definition for Ethernet DMA Bus Mode Register */</span>
<a name="l06799"></a>06799 <span class="preprocessor">#define ETH_DMABMR_AAB       ((uint32_t)0x02000000)  </span><span class="comment">/* Address-Aligned beats */</span>
<a name="l06800"></a>06800 <span class="preprocessor">#define ETH_DMABMR_FPM        ((uint32_t)0x01000000)  </span><span class="comment">/* 4xPBL mode */</span>
<a name="l06801"></a>06801 <span class="preprocessor">#define ETH_DMABMR_USP       ((uint32_t)0x00800000)  </span><span class="comment">/* Use separate PBL */</span>
<a name="l06802"></a>06802 <span class="preprocessor">#define ETH_DMABMR_RDP       ((uint32_t)0x007E0000)  </span><span class="comment">/* RxDMA PBL */</span>
<a name="l06803"></a>06803 <span class="preprocessor">  #define ETH_DMABMR_RDP_1Beat    ((uint32_t)0x00020000)  </span><span class="comment">/* maximum number of beats to be transferred in one RxDMA transaction is 1 */</span>
<a name="l06804"></a>06804 <span class="preprocessor">  #define ETH_DMABMR_RDP_2Beat    ((uint32_t)0x00040000)  </span><span class="comment">/* maximum number of beats to be transferred in one RxDMA transaction is 2 */</span>
<a name="l06805"></a>06805 <span class="preprocessor">  #define ETH_DMABMR_RDP_4Beat    ((uint32_t)0x00080000)  </span><span class="comment">/* maximum number of beats to be transferred in one RxDMA transaction is 4 */</span>
<a name="l06806"></a>06806 <span class="preprocessor">  #define ETH_DMABMR_RDP_8Beat    ((uint32_t)0x00100000)  </span><span class="comment">/* maximum number of beats to be transferred in one RxDMA transaction is 8 */</span>
<a name="l06807"></a>06807 <span class="preprocessor">  #define ETH_DMABMR_RDP_16Beat   ((uint32_t)0x00200000)  </span><span class="comment">/* maximum number of beats to be transferred in one RxDMA transaction is 16 */</span>
<a name="l06808"></a>06808 <span class="preprocessor">  #define ETH_DMABMR_RDP_32Beat   ((uint32_t)0x00400000)  </span><span class="comment">/* maximum number of beats to be transferred in one RxDMA transaction is 32 */</span>                
<a name="l06809"></a>06809 <span class="preprocessor">  #define ETH_DMABMR_RDP_4xPBL_4Beat   ((uint32_t)0x01020000)  </span><span class="comment">/* maximum number of beats to be transferred in one RxDMA transaction is 4 */</span>
<a name="l06810"></a>06810 <span class="preprocessor">  #define ETH_DMABMR_RDP_4xPBL_8Beat   ((uint32_t)0x01040000)  </span><span class="comment">/* maximum number of beats to be transferred in one RxDMA transaction is 8 */</span>
<a name="l06811"></a>06811 <span class="preprocessor">  #define ETH_DMABMR_RDP_4xPBL_16Beat  ((uint32_t)0x01080000)  </span><span class="comment">/* maximum number of beats to be transferred in one RxDMA transaction is 16 */</span>
<a name="l06812"></a>06812 <span class="preprocessor">  #define ETH_DMABMR_RDP_4xPBL_32Beat  ((uint32_t)0x01100000)  </span><span class="comment">/* maximum number of beats to be transferred in one RxDMA transaction is 32 */</span>
<a name="l06813"></a>06813 <span class="preprocessor">  #define ETH_DMABMR_RDP_4xPBL_64Beat  ((uint32_t)0x01200000)  </span><span class="comment">/* maximum number of beats to be transferred in one RxDMA transaction is 64 */</span>
<a name="l06814"></a>06814 <span class="preprocessor">  #define ETH_DMABMR_RDP_4xPBL_128Beat ((uint32_t)0x01400000)  </span><span class="comment">/* maximum number of beats to be transferred in one RxDMA transaction is 128 */</span>  
<a name="l06815"></a>06815 <span class="preprocessor">#define ETH_DMABMR_FB        ((uint32_t)0x00010000)  </span><span class="comment">/* Fixed Burst */</span>
<a name="l06816"></a>06816 <span class="preprocessor">#define ETH_DMABMR_RTPR      ((uint32_t)0x0000C000)  </span><span class="comment">/* Rx Tx priority ratio */</span>
<a name="l06817"></a>06817 <span class="preprocessor">  #define ETH_DMABMR_RTPR_1_1     ((uint32_t)0x00000000)  </span><span class="comment">/* Rx Tx priority ratio */</span>
<a name="l06818"></a>06818 <span class="preprocessor">  #define ETH_DMABMR_RTPR_2_1     ((uint32_t)0x00004000)  </span><span class="comment">/* Rx Tx priority ratio */</span>
<a name="l06819"></a>06819 <span class="preprocessor">  #define ETH_DMABMR_RTPR_3_1     ((uint32_t)0x00008000)  </span><span class="comment">/* Rx Tx priority ratio */</span>
<a name="l06820"></a>06820 <span class="preprocessor">  #define ETH_DMABMR_RTPR_4_1     ((uint32_t)0x0000C000)  </span><span class="comment">/* Rx Tx priority ratio */</span>  
<a name="l06821"></a>06821 <span class="preprocessor">#define ETH_DMABMR_PBL    ((uint32_t)0x00003F00)  </span><span class="comment">/* Programmable burst length */</span>
<a name="l06822"></a>06822 <span class="preprocessor">  #define ETH_DMABMR_PBL_1Beat    ((uint32_t)0x00000100)  </span><span class="comment">/* maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 */</span>
<a name="l06823"></a>06823 <span class="preprocessor">  #define ETH_DMABMR_PBL_2Beat    ((uint32_t)0x00000200)  </span><span class="comment">/* maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 */</span>
<a name="l06824"></a>06824 <span class="preprocessor">  #define ETH_DMABMR_PBL_4Beat    ((uint32_t)0x00000400)  </span><span class="comment">/* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */</span>
<a name="l06825"></a>06825 <span class="preprocessor">  #define ETH_DMABMR_PBL_8Beat    ((uint32_t)0x00000800)  </span><span class="comment">/* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */</span>
<a name="l06826"></a>06826 <span class="preprocessor">  #define ETH_DMABMR_PBL_16Beat   ((uint32_t)0x00001000)  </span><span class="comment">/* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */</span>
<a name="l06827"></a>06827 <span class="preprocessor">  #define ETH_DMABMR_PBL_32Beat   ((uint32_t)0x00002000)  </span><span class="comment">/* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */</span>                
<a name="l06828"></a>06828 <span class="preprocessor">  #define ETH_DMABMR_PBL_4xPBL_4Beat   ((uint32_t)0x01000100)  </span><span class="comment">/* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */</span>
<a name="l06829"></a>06829 <span class="preprocessor">  #define ETH_DMABMR_PBL_4xPBL_8Beat   ((uint32_t)0x01000200)  </span><span class="comment">/* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */</span>
<a name="l06830"></a>06830 <span class="preprocessor">  #define ETH_DMABMR_PBL_4xPBL_16Beat  ((uint32_t)0x01000400)  </span><span class="comment">/* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */</span>
<a name="l06831"></a>06831 <span class="preprocessor">  #define ETH_DMABMR_PBL_4xPBL_32Beat  ((uint32_t)0x01000800)  </span><span class="comment">/* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */</span>
<a name="l06832"></a>06832 <span class="preprocessor">  #define ETH_DMABMR_PBL_4xPBL_64Beat  ((uint32_t)0x01001000)  </span><span class="comment">/* maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 */</span>
<a name="l06833"></a>06833 <span class="preprocessor">  #define ETH_DMABMR_PBL_4xPBL_128Beat ((uint32_t)0x01002000)  </span><span class="comment">/* maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 */</span>
<a name="l06834"></a>06834 <span class="preprocessor">#define ETH_DMABMR_EDE       ((uint32_t)0x00000080)  </span><span class="comment">/* Enhanced Descriptor Enable */</span>
<a name="l06835"></a>06835 <span class="preprocessor">#define ETH_DMABMR_DSL       ((uint32_t)0x0000007C)  </span><span class="comment">/* Descriptor Skip Length */</span>
<a name="l06836"></a>06836 <span class="preprocessor">#define ETH_DMABMR_DA        ((uint32_t)0x00000002)  </span><span class="comment">/* DMA arbitration scheme */</span>
<a name="l06837"></a>06837 <span class="preprocessor">#define ETH_DMABMR_SR        ((uint32_t)0x00000001)  </span><span class="comment">/* Software reset */</span>
<a name="l06838"></a>06838 
<a name="l06839"></a>06839 <span class="comment">/* Bit definition for Ethernet DMA Transmit Poll Demand Register */</span>
<a name="l06840"></a>06840 <span class="preprocessor">#define ETH_DMATPDR_TPD      ((uint32_t)0xFFFFFFFF)  </span><span class="comment">/* Transmit poll demand */</span>
<a name="l06841"></a>06841 
<a name="l06842"></a>06842 <span class="comment">/* Bit definition for Ethernet DMA Receive Poll Demand Register */</span>
<a name="l06843"></a>06843 <span class="preprocessor">#define ETH_DMARPDR_RPD      ((uint32_t)0xFFFFFFFF)  </span><span class="comment">/* Receive poll demand  */</span>
<a name="l06844"></a>06844 
<a name="l06845"></a>06845 <span class="comment">/* Bit definition for Ethernet DMA Receive Descriptor List Address Register */</span>
<a name="l06846"></a>06846 <span class="preprocessor">#define ETH_DMARDLAR_SRL     ((uint32_t)0xFFFFFFFF)  </span><span class="comment">/* Start of receive list */</span>
<a name="l06847"></a>06847 
<a name="l06848"></a>06848 <span class="comment">/* Bit definition for Ethernet DMA Transmit Descriptor List Address Register */</span>
<a name="l06849"></a>06849 <span class="preprocessor">#define ETH_DMATDLAR_STL     ((uint32_t)0xFFFFFFFF)  </span><span class="comment">/* Start of transmit list */</span>
<a name="l06850"></a>06850 
<a name="l06851"></a>06851 <span class="comment">/* Bit definition for Ethernet DMA Status Register */</span>
<a name="l06852"></a>06852 <span class="preprocessor">#define ETH_DMASR_TSTS       ((uint32_t)0x20000000)  </span><span class="comment">/* Time-stamp trigger status */</span>
<a name="l06853"></a>06853 <span class="preprocessor">#define ETH_DMASR_PMTS       ((uint32_t)0x10000000)  </span><span class="comment">/* PMT status */</span>
<a name="l06854"></a>06854 <span class="preprocessor">#define ETH_DMASR_MMCS       ((uint32_t)0x08000000)  </span><span class="comment">/* MMC status */</span>
<a name="l06855"></a>06855 <span class="preprocessor">#define ETH_DMASR_EBS        ((uint32_t)0x03800000)  </span><span class="comment">/* Error bits status */</span>
<a name="l06856"></a>06856   <span class="comment">/* combination with EBS[2:0] for GetFlagStatus function */</span>
<a name="l06857"></a>06857 <span class="preprocessor">  #define ETH_DMASR_EBS_DescAccess      ((uint32_t)0x02000000)  </span><span class="comment">/* Error bits 0-data buffer, 1-desc. access */</span>
<a name="l06858"></a>06858 <span class="preprocessor">  #define ETH_DMASR_EBS_ReadTransf      ((uint32_t)0x01000000)  </span><span class="comment">/* Error bits 0-write trnsf, 1-read transfr */</span>
<a name="l06859"></a>06859 <span class="preprocessor">  #define ETH_DMASR_EBS_DataTransfTx    ((uint32_t)0x00800000)  </span><span class="comment">/* Error bits 0-Rx DMA, 1-Tx DMA */</span>
<a name="l06860"></a>06860 <span class="preprocessor">#define ETH_DMASR_TPS         ((uint32_t)0x00700000)  </span><span class="comment">/* Transmit process state */</span>
<a name="l06861"></a>06861 <span class="preprocessor">  #define ETH_DMASR_TPS_Stopped         ((uint32_t)0x00000000)  </span><span class="comment">/* Stopped - Reset or Stop Tx Command issued  */</span>
<a name="l06862"></a>06862 <span class="preprocessor">  #define ETH_DMASR_TPS_Fetching        ((uint32_t)0x00100000)  </span><span class="comment">/* Running - fetching the Tx descriptor */</span>
<a name="l06863"></a>06863 <span class="preprocessor">  #define ETH_DMASR_TPS_Waiting         ((uint32_t)0x00200000)  </span><span class="comment">/* Running - waiting for status */</span>
<a name="l06864"></a>06864 <span class="preprocessor">  #define ETH_DMASR_TPS_Reading         ((uint32_t)0x00300000)  </span><span class="comment">/* Running - reading the data from host memory */</span>
<a name="l06865"></a>06865 <span class="preprocessor">  #define ETH_DMASR_TPS_Suspended       ((uint32_t)0x00600000)  </span><span class="comment">/* Suspended - Tx Descriptor unavailabe */</span>
<a name="l06866"></a>06866 <span class="preprocessor">  #define ETH_DMASR_TPS_Closing         ((uint32_t)0x00700000)  </span><span class="comment">/* Running - closing Rx descriptor */</span>
<a name="l06867"></a>06867 <span class="preprocessor">#define ETH_DMASR_RPS         ((uint32_t)0x000E0000)  </span><span class="comment">/* Receive process state */</span>
<a name="l06868"></a>06868 <span class="preprocessor">  #define ETH_DMASR_RPS_Stopped         ((uint32_t)0x00000000)  </span><span class="comment">/* Stopped - Reset or Stop Rx Command issued */</span>
<a name="l06869"></a>06869 <span class="preprocessor">  #define ETH_DMASR_RPS_Fetching        ((uint32_t)0x00020000)  </span><span class="comment">/* Running - fetching the Rx descriptor */</span>
<a name="l06870"></a>06870 <span class="preprocessor">  #define ETH_DMASR_RPS_Waiting         ((uint32_t)0x00060000)  </span><span class="comment">/* Running - waiting for packet */</span>
<a name="l06871"></a>06871 <span class="preprocessor">  #define ETH_DMASR_RPS_Suspended       ((uint32_t)0x00080000)  </span><span class="comment">/* Suspended - Rx Descriptor unavailable */</span>
<a name="l06872"></a>06872 <span class="preprocessor">  #define ETH_DMASR_RPS_Closing         ((uint32_t)0x000A0000)  </span><span class="comment">/* Running - closing descriptor */</span>
<a name="l06873"></a>06873 <span class="preprocessor">  #define ETH_DMASR_RPS_Queuing         ((uint32_t)0x000E0000)  </span><span class="comment">/* Running - queuing the recieve frame into host memory */</span>
<a name="l06874"></a>06874 <span class="preprocessor">#define ETH_DMASR_NIS        ((uint32_t)0x00010000)  </span><span class="comment">/* Normal interrupt summary */</span>
<a name="l06875"></a>06875 <span class="preprocessor">#define ETH_DMASR_AIS        ((uint32_t)0x00008000)  </span><span class="comment">/* Abnormal interrupt summary */</span>
<a name="l06876"></a>06876 <span class="preprocessor">#define ETH_DMASR_ERS        ((uint32_t)0x00004000)  </span><span class="comment">/* Early receive status */</span>
<a name="l06877"></a>06877 <span class="preprocessor">#define ETH_DMASR_FBES       ((uint32_t)0x00002000)  </span><span class="comment">/* Fatal bus error status */</span>
<a name="l06878"></a>06878 <span class="preprocessor">#define ETH_DMASR_ETS        ((uint32_t)0x00000400)  </span><span class="comment">/* Early transmit status */</span>
<a name="l06879"></a>06879 <span class="preprocessor">#define ETH_DMASR_RWTS       ((uint32_t)0x00000200)  </span><span class="comment">/* Receive watchdog timeout status */</span>
<a name="l06880"></a>06880 <span class="preprocessor">#define ETH_DMASR_RPSS       ((uint32_t)0x00000100)  </span><span class="comment">/* Receive process stopped status */</span>
<a name="l06881"></a>06881 <span class="preprocessor">#define ETH_DMASR_RBUS       ((uint32_t)0x00000080)  </span><span class="comment">/* Receive buffer unavailable status */</span>
<a name="l06882"></a>06882 <span class="preprocessor">#define ETH_DMASR_RS         ((uint32_t)0x00000040)  </span><span class="comment">/* Receive status */</span>
<a name="l06883"></a>06883 <span class="preprocessor">#define ETH_DMASR_TUS        ((uint32_t)0x00000020)  </span><span class="comment">/* Transmit underflow status */</span>
<a name="l06884"></a>06884 <span class="preprocessor">#define ETH_DMASR_ROS        ((uint32_t)0x00000010)  </span><span class="comment">/* Receive overflow status */</span>
<a name="l06885"></a>06885 <span class="preprocessor">#define ETH_DMASR_TJTS       ((uint32_t)0x00000008)  </span><span class="comment">/* Transmit jabber timeout status */</span>
<a name="l06886"></a>06886 <span class="preprocessor">#define ETH_DMASR_TBUS       ((uint32_t)0x00000004)  </span><span class="comment">/* Transmit buffer unavailable status */</span>
<a name="l06887"></a>06887 <span class="preprocessor">#define ETH_DMASR_TPSS       ((uint32_t)0x00000002)  </span><span class="comment">/* Transmit process stopped status */</span>
<a name="l06888"></a>06888 <span class="preprocessor">#define ETH_DMASR_TS         ((uint32_t)0x00000001)  </span><span class="comment">/* Transmit status */</span>
<a name="l06889"></a>06889 
<a name="l06890"></a>06890 <span class="comment">/* Bit definition for Ethernet DMA Operation Mode Register */</span>
<a name="l06891"></a>06891 <span class="preprocessor">#define ETH_DMAOMR_DTCEFD    ((uint32_t)0x04000000)  </span><span class="comment">/* Disable Dropping of TCP/IP checksum error frames */</span>
<a name="l06892"></a>06892 <span class="preprocessor">#define ETH_DMAOMR_RSF       ((uint32_t)0x02000000)  </span><span class="comment">/* Receive store and forward */</span>
<a name="l06893"></a>06893 <span class="preprocessor">#define ETH_DMAOMR_DFRF      ((uint32_t)0x01000000)  </span><span class="comment">/* Disable flushing of received frames */</span>
<a name="l06894"></a>06894 <span class="preprocessor">#define ETH_DMAOMR_TSF       ((uint32_t)0x00200000)  </span><span class="comment">/* Transmit store and forward */</span>
<a name="l06895"></a>06895 <span class="preprocessor">#define ETH_DMAOMR_FTF       ((uint32_t)0x00100000)  </span><span class="comment">/* Flush transmit FIFO */</span>
<a name="l06896"></a>06896 <span class="preprocessor">#define ETH_DMAOMR_TTC       ((uint32_t)0x0001C000)  </span><span class="comment">/* Transmit threshold control */</span>
<a name="l06897"></a>06897 <span class="preprocessor">  #define ETH_DMAOMR_TTC_64Bytes       ((uint32_t)0x00000000)  </span><span class="comment">/* threshold level of the MTL Transmit FIFO is 64 Bytes */</span>
<a name="l06898"></a>06898 <span class="preprocessor">  #define ETH_DMAOMR_TTC_128Bytes      ((uint32_t)0x00004000)  </span><span class="comment">/* threshold level of the MTL Transmit FIFO is 128 Bytes */</span>
<a name="l06899"></a>06899 <span class="preprocessor">  #define ETH_DMAOMR_TTC_192Bytes      ((uint32_t)0x00008000)  </span><span class="comment">/* threshold level of the MTL Transmit FIFO is 192 Bytes */</span>
<a name="l06900"></a>06900 <span class="preprocessor">  #define ETH_DMAOMR_TTC_256Bytes      ((uint32_t)0x0000C000)  </span><span class="comment">/* threshold level of the MTL Transmit FIFO is 256 Bytes */</span>
<a name="l06901"></a>06901 <span class="preprocessor">  #define ETH_DMAOMR_TTC_40Bytes       ((uint32_t)0x00010000)  </span><span class="comment">/* threshold level of the MTL Transmit FIFO is 40 Bytes */</span>
<a name="l06902"></a>06902 <span class="preprocessor">  #define ETH_DMAOMR_TTC_32Bytes       ((uint32_t)0x00014000)  </span><span class="comment">/* threshold level of the MTL Transmit FIFO is 32 Bytes */</span>
<a name="l06903"></a>06903 <span class="preprocessor">  #define ETH_DMAOMR_TTC_24Bytes       ((uint32_t)0x00018000)  </span><span class="comment">/* threshold level of the MTL Transmit FIFO is 24 Bytes */</span>
<a name="l06904"></a>06904 <span class="preprocessor">  #define ETH_DMAOMR_TTC_16Bytes       ((uint32_t)0x0001C000)  </span><span class="comment">/* threshold level of the MTL Transmit FIFO is 16 Bytes */</span>
<a name="l06905"></a>06905 <span class="preprocessor">#define ETH_DMAOMR_ST        ((uint32_t)0x00002000)  </span><span class="comment">/* Start/stop transmission command */</span>
<a name="l06906"></a>06906 <span class="preprocessor">#define ETH_DMAOMR_FEF       ((uint32_t)0x00000080)  </span><span class="comment">/* Forward error frames */</span>
<a name="l06907"></a>06907 <span class="preprocessor">#define ETH_DMAOMR_FUGF      ((uint32_t)0x00000040)  </span><span class="comment">/* Forward undersized good frames */</span>
<a name="l06908"></a>06908 <span class="preprocessor">#define ETH_DMAOMR_RTC       ((uint32_t)0x00000018)  </span><span class="comment">/* receive threshold control */</span>
<a name="l06909"></a>06909 <span class="preprocessor">  #define ETH_DMAOMR_RTC_64Bytes       ((uint32_t)0x00000000)  </span><span class="comment">/* threshold level of the MTL Receive FIFO is 64 Bytes */</span>
<a name="l06910"></a>06910 <span class="preprocessor">  #define ETH_DMAOMR_RTC_32Bytes       ((uint32_t)0x00000008)  </span><span class="comment">/* threshold level of the MTL Receive FIFO is 32 Bytes */</span>
<a name="l06911"></a>06911 <span class="preprocessor">  #define ETH_DMAOMR_RTC_96Bytes       ((uint32_t)0x00000010)  </span><span class="comment">/* threshold level of the MTL Receive FIFO is 96 Bytes */</span>
<a name="l06912"></a>06912 <span class="preprocessor">  #define ETH_DMAOMR_RTC_128Bytes      ((uint32_t)0x00000018)  </span><span class="comment">/* threshold level of the MTL Receive FIFO is 128 Bytes */</span>
<a name="l06913"></a>06913 <span class="preprocessor">#define ETH_DMAOMR_OSF       ((uint32_t)0x00000004)  </span><span class="comment">/* operate on second frame */</span>
<a name="l06914"></a>06914 <span class="preprocessor">#define ETH_DMAOMR_SR        ((uint32_t)0x00000002)  </span><span class="comment">/* Start/stop receive */</span>
<a name="l06915"></a>06915 
<a name="l06916"></a>06916 <span class="comment">/* Bit definition for Ethernet DMA Interrupt Enable Register */</span>
<a name="l06917"></a>06917 <span class="preprocessor">#define ETH_DMAIER_NISE      ((uint32_t)0x00010000)  </span><span class="comment">/* Normal interrupt summary enable */</span>
<a name="l06918"></a>06918 <span class="preprocessor">#define ETH_DMAIER_AISE      ((uint32_t)0x00008000)  </span><span class="comment">/* Abnormal interrupt summary enable */</span>
<a name="l06919"></a>06919 <span class="preprocessor">#define ETH_DMAIER_ERIE      ((uint32_t)0x00004000)  </span><span class="comment">/* Early receive interrupt enable */</span>
<a name="l06920"></a>06920 <span class="preprocessor">#define ETH_DMAIER_FBEIE     ((uint32_t)0x00002000)  </span><span class="comment">/* Fatal bus error interrupt enable */</span>
<a name="l06921"></a>06921 <span class="preprocessor">#define ETH_DMAIER_ETIE      ((uint32_t)0x00000400)  </span><span class="comment">/* Early transmit interrupt enable */</span>
<a name="l06922"></a>06922 <span class="preprocessor">#define ETH_DMAIER_RWTIE     ((uint32_t)0x00000200)  </span><span class="comment">/* Receive watchdog timeout interrupt enable */</span>
<a name="l06923"></a>06923 <span class="preprocessor">#define ETH_DMAIER_RPSIE     ((uint32_t)0x00000100)  </span><span class="comment">/* Receive process stopped interrupt enable */</span>
<a name="l06924"></a>06924 <span class="preprocessor">#define ETH_DMAIER_RBUIE     ((uint32_t)0x00000080)  </span><span class="comment">/* Receive buffer unavailable interrupt enable */</span>
<a name="l06925"></a>06925 <span class="preprocessor">#define ETH_DMAIER_RIE       ((uint32_t)0x00000040)  </span><span class="comment">/* Receive interrupt enable */</span>
<a name="l06926"></a>06926 <span class="preprocessor">#define ETH_DMAIER_TUIE      ((uint32_t)0x00000020)  </span><span class="comment">/* Transmit Underflow interrupt enable */</span>
<a name="l06927"></a>06927 <span class="preprocessor">#define ETH_DMAIER_ROIE      ((uint32_t)0x00000010)  </span><span class="comment">/* Receive Overflow interrupt enable */</span>
<a name="l06928"></a>06928 <span class="preprocessor">#define ETH_DMAIER_TJTIE     ((uint32_t)0x00000008)  </span><span class="comment">/* Transmit jabber timeout interrupt enable */</span>
<a name="l06929"></a>06929 <span class="preprocessor">#define ETH_DMAIER_TBUIE     ((uint32_t)0x00000004)  </span><span class="comment">/* Transmit buffer unavailable interrupt enable */</span>
<a name="l06930"></a>06930 <span class="preprocessor">#define ETH_DMAIER_TPSIE     ((uint32_t)0x00000002)  </span><span class="comment">/* Transmit process stopped interrupt enable */</span>
<a name="l06931"></a>06931 <span class="preprocessor">#define ETH_DMAIER_TIE       ((uint32_t)0x00000001)  </span><span class="comment">/* Transmit interrupt enable */</span>
<a name="l06932"></a>06932 
<a name="l06933"></a>06933 <span class="comment">/* Bit definition for Ethernet DMA Missed Frame and Buffer Overflow Counter Register */</span>
<a name="l06934"></a>06934 <span class="preprocessor">#define ETH_DMAMFBOCR_OFOC   ((uint32_t)0x10000000)  </span><span class="comment">/* Overflow bit for FIFO overflow counter */</span>
<a name="l06935"></a>06935 <span class="preprocessor">#define ETH_DMAMFBOCR_MFA    ((uint32_t)0x0FFE0000)  </span><span class="comment">/* Number of frames missed by the application */</span>
<a name="l06936"></a>06936 <span class="preprocessor">#define ETH_DMAMFBOCR_OMFC   ((uint32_t)0x00010000)  </span><span class="comment">/* Overflow bit for missed frame counter */</span>
<a name="l06937"></a>06937 <span class="preprocessor">#define ETH_DMAMFBOCR_MFC    ((uint32_t)0x0000FFFF)  </span><span class="comment">/* Number of frames missed by the controller */</span>
<a name="l06938"></a>06938 
<a name="l06939"></a>06939 <span class="comment">/* Bit definition for Ethernet DMA Current Host Transmit Descriptor Register */</span>
<a name="l06940"></a>06940 <span class="preprocessor">#define ETH_DMACHTDR_HTDAP   ((uint32_t)0xFFFFFFFF)  </span><span class="comment">/* Host transmit descriptor address pointer */</span>
<a name="l06941"></a>06941 
<a name="l06942"></a>06942 <span class="comment">/* Bit definition for Ethernet DMA Current Host Receive Descriptor Register */</span>
<a name="l06943"></a>06943 <span class="preprocessor">#define ETH_DMACHRDR_HRDAP   ((uint32_t)0xFFFFFFFF)  </span><span class="comment">/* Host receive descriptor address pointer */</span>
<a name="l06944"></a>06944 
<a name="l06945"></a>06945 <span class="comment">/* Bit definition for Ethernet DMA Current Host Transmit Buffer Address Register */</span>
<a name="l06946"></a>06946 <span class="preprocessor">#define ETH_DMACHTBAR_HTBAP  ((uint32_t)0xFFFFFFFF)  </span><span class="comment">/* Host transmit buffer address pointer */</span>
<a name="l06947"></a>06947 
<a name="l06948"></a>06948 <span class="comment">/* Bit definition for Ethernet DMA Current Host Receive Buffer Address Register */</span>
<a name="l06949"></a>06949 <span class="preprocessor">#define ETH_DMACHRBAR_HRBAP  ((uint32_t)0xFFFFFFFF)  </span><span class="comment">/* Host receive buffer address pointer */</span>
<a name="l06950"></a>06950 
<a name="l06959"></a>06959 <span class="preprocessor">#ifdef USE_STDPERIPH_DRIVER</span>
<a name="l06960"></a>06960 <span class="preprocessor"></span><span class="preprocessor">  #include &quot;stm32f4xx_conf.h&quot;</span>
<a name="l06961"></a>06961 <span class="preprocessor">#endif </span><span class="comment">/* USE_STDPERIPH_DRIVER */</span>
<a name="l06962"></a>06962 
<a name="l06967"></a>06967 <span class="preprocessor">#define SET_BIT(REG, BIT)     ((REG) |= (BIT))</span>
<a name="l06968"></a>06968 <span class="preprocessor"></span>
<a name="l06969"></a>06969 <span class="preprocessor">#define CLEAR_BIT(REG, BIT)   ((REG) &amp;= ~(BIT))</span>
<a name="l06970"></a>06970 <span class="preprocessor"></span>
<a name="l06971"></a>06971 <span class="preprocessor">#define READ_BIT(REG, BIT)    ((REG) &amp; (BIT))</span>
<a name="l06972"></a>06972 <span class="preprocessor"></span>
<a name="l06973"></a>06973 <span class="preprocessor">#define CLEAR_REG(REG)        ((REG) = (0x0))</span>
<a name="l06974"></a>06974 <span class="preprocessor"></span>
<a name="l06975"></a>06975 <span class="preprocessor">#define WRITE_REG(REG, VAL)   ((REG) = (VAL))</span>
<a name="l06976"></a>06976 <span class="preprocessor"></span>
<a name="l06977"></a>06977 <span class="preprocessor">#define READ_REG(REG)         ((REG))</span>
<a name="l06978"></a>06978 <span class="preprocessor"></span>
<a name="l06979"></a>06979 <span class="preprocessor">#define MODIFY_REG(REG, CLEARMASK, SETMASK)  WRITE_REG((REG), (((READ_REG(REG)) &amp; (~(CLEARMASK))) | (SETMASK)))</span>
<a name="l06980"></a>06980 <span class="preprocessor"></span>
<a name="l06985"></a>06985 <span class="preprocessor">#ifdef __cplusplus</span>
<a name="l06986"></a>06986 <span class="preprocessor"></span>}
<a name="l06987"></a>06987 <span class="preprocessor">#endif </span><span class="comment">/* __cplusplus */</span>
<a name="l06988"></a>06988 
<a name="l06989"></a>06989 <span class="preprocessor">#endif </span><span class="comment">/* __STM32F4xx_H */</span>
<a name="l06990"></a>06990 
<a name="l06999"></a>06999 <span class="comment">/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/</span>
</pre></div></div><!-- contents -->


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